LT5506
1
5506fa
IF INPUT POWER EACH TONE (dBm)
–60
THD (dBc)
–30
–35
–40
–45
–50
–55
–60 –50 –40 –30 –20
5506 TA01b
–10
f
IF, 1
= 280MHz
f
IF, 2
= 280.1MHz
f
2xLO
= 570MHz
800mV
P-P
DIFFERENTIAL OUT
■
Wide Range 1.8V to 5.25V Supply
■
Frequency Range: 40MHz to 500MHz
■
–4dB to 59dB Variable Power Gain
■
THD < 0.12% (–58dBc)
at 800mV
P-P
Differential Output Level
■
8.8MHz I/Q Lowpass Output Noise Filters
■
IF Overload Detector
■
Baseband I/Q Amplitude Imbalance: 0.2dB
■
Baseband I/Q Phase Imbalance: 0.6°
■
6.8dB Noise Figure at Max Gain
■
Input IP3 at Low Gain: –0.5dBm
■
Low Supply Current: 27mA
■
Low Delay Shift Over Gain Control Range: 2ps/dB
■
Outputs Biased Up While in Standby
■
16-Lead QFN 4mm x 4mm Package with Exposed Pad
40MHz to 500MHz
Quadrature Demodulator
with VGA
, LTC and LT are registered trademarks of Linear Technology Corporation.
Total Harmonic Distortion vs
IF Input Level at 1.8V Supply
■
IEEE802.11
■
High Speed Wireless LAN
■
Wireless Local Loop
2xLO
+
2xLO
–
IF
+
IF
–
EN STBY
V
CC
I
OUT+
I
OUT–
Q
OUT+
Q
OUT–
GND
1.8V
C2
1µFC1
1nF
C3
1.8pF
STANDBY
2xLO
560MHz
INPUT
280MHz
IF INPUT
C3
10pF
5506 TA01
÷2
LT5506
L1
15nH
L2
15nH
L3
39nH
C5
3.3pF
C4
3.3pF
GAIN CONTROL
ENABLE
IF DET
V
CTRL
The LT
®
5506 is a 40MHz to 500MHz monolithic integrated
quadrature demodulator with variable gain amplifier (VGA),
designed for low voltage operation. It supports standards
that use a linear modulation format. The chip consists of
a VGA, quadrature down-converting mixers and lowpass
noise filters. The LO port consists of a divide-by-two stage
and LO buffers. The IC provides all building blocks for IF
down-conversion to I and Q baseband signals with a single
supply voltage of 1.8V to 5.25V. The VGA gain has a linear-
in-dB relationship to the control input voltage. Hard-clip-
ping amplifiers at the mixer outputs reduce the recovery
time from a signal overload condition. The lowpass filters
reduce the out-of-band noise and spurious frequency
components. The cut-off frequency of the noise filters is
approximately 8.8MHz. The external 2xLO frequency is
required to be twice the IF input frequency for the mixers.
The standby mode provides reduced supply current and
fast transient response into the normal operating mode
when the I/Q outputs are AC-coupled to a baseband chip.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
LT5506
2
5506fa
Supply Voltage ....................................................... 5.5V
Differential Voltage Between 2xLO
+
and 2xLO
–
..........
4V
IF
+
, IF
–
............................................. –500mV to 500mV
I
OUT+
, I
OUT–
, Q
OUT+
, Q
OUT–
..................V
CC
– 1.8V to V
CC
Operating Ambient Temperature
(Note 2) ...................................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Voltage on Any Pin
Not to Exceed ........................ –500mV to V
CC
+ 500mV
ORDER PART
NUMBER
T
JMAX
= 125°C, θ
JA
= 37°C/W
EXPOSED PAD (PIN 17) IS GROUND
MUST BE SOLDERED TO PCB
LT5506EUF
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
VCC = 3V. f2xLO = 570MHz, P2xLO = –5dBm (Note 5), fIF = 284MHz,
PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
16 15 14 13
5 6 7 8
TOP VIEW
17
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
9
10
11
12
4
3
2
1GND
IF+
IF–
GND
STBY
2xLO+
2xLO–
EN
IOUT+
IOUT–
QOUT+
QOUT–
VCC
VCTRL
IF DET
VCC
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IF Input
f
IF
Frequency Range 40 to 500 MHz
Nominal Input Level R
SOURCE
= 200Ω Differential –79 to –22 dBm
Input Impedance IF
+
, IF
–
to GND, EN = V
CC
100Ω//1.2pF
IF
+
, IF
–
to GND, EN = GND 1pF
NF Noise Figure at Max Gain V
CTRL
= 1.7V 6.8 dB
G
L
Min Gain (Note 4) V
CTRL
= 0.2V 0.9 8 dB
G
H
Max Gain (Note 4) V
CTRL
= 1.7V 50 59 dB
IIP3 Input IP3, Min Gain P
IF
= –22.5dBm (Note 7) –0.5 dBm
Input IP3, Max Gain P
IF
= –75dBm (Note 7) –49 dBm
IIP2 Input IP2, Max Gain V
CTRL
= 1.7V –8 dBm
Demodulator I/Q Output
Nominal Voltage Swing (Note 6) 0.8 V
P-P
Clipping Level (Note 6) 1.25 V
P-P
DC Common Mode Voltage V
CC
– 1.19 V
I/Q Amplitude Imbalance (Note 8) 0.2 0.5 dB
I/Q Phase Imbalance (Note 8) 0.6 3 Deg
DC Offset (Notes 6, 8) 28 mV
Output Driving Capability Single Ended, C
LOAD
≤ 10pF 2 1.5 kΩ
STBY to Turn-On Delay 0.3 µs
I/Q Output 1dB Compression –11.5 dBm
I/Q Output IM3 P
IF, 1
= –25.5dBm, 280MHz –50 dBc
P
IF, 2
= –25.5dBm, 280.1MHz (Note 7)
LT5506
3
5506fa
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm (Note 5), fIF = 284MHz,
PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Specifications over the –40°C to 85°C temperature range are
assured by design, characterization and correlation with statistical process
controls.
Note 3: Tests are performed as shown in the configuration of Figure 6. The
IF input transformer loss is substracted from the measured values.
Note 4: Power gain is defined here as the I (or Q) output power into a 4kΩ
differential load, divided by the IF input power in dB. To calculate the
voltage gain between the differential I output (or Q output) and the IF
input, including ideal matching network, 10 • log(4kΩ/50) = 19dB has to
be added to this power gain.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Variable Gain Amplifier (VGA)
Gain Slope Linearity Error V
CTRL
= 0V to 1.4V ±0.5 dB
Temperature Gain Shift T = –40°C to 85°C, V
CTRL
= 0V to 1.4V ±0.3 dB
Gain Control Response Time Settled within 10% of Final Value 100 ns
Gain Control Voltage Range 0 to 1.7 V
Gain Control Slope 43 dB/V
Gain Control Input Impedance To Internal 0.2V 25 kΩ
Delay Shift Over Gain Control Measured Over 10dB Step 2 ps/dB
Baseband Lowpass Filter
–3dB Cutoff Frequency 7.2 8.8 10.4 MHz
Group Delay Ripple 5ns
2xLO Input
f
2xLO
Frequency Range 80 to 1000 MHz
P
2xLO
Input Power 1:2 Transformer with 240Ω Shunt Resistor (Note 5) –20 –5 dBm
Input Power LC Balun (Note 5) –10 dBm
Input Impedance Differential Between 2xLO
+
and 2xLO
–
800Ω//0.4pF
DC Common Mode Voltage V
CC
– 0.4 V
IF Detector
IF Detector Range Referred to IF Input –30 to 8 dBm
Output Voltage Range For P
IF
= –30dBm to 8dBm 0.3 to 1.2 V
Detector Response Time With External 1.8pF Load, 100 ns
Settling within 10% of Final Value
Power Supply
V
CC
Supply Voltage 1.8 5.25 V
I
CC
Supply Current EN = High, STBY = Low or High 26.5 36 mA
I
OFF
Shutdown Current EN, STBY < 350mV 0.2 30 µA
I
STBY
Standby Current EN = Low; STBY = High 3.6 5.5 mA
Mode
Enable Enable Pin Voltage EN = High 1 V
Disable Enable Pin Voltage EN = Low 0.5 V
Standby Standby Pin Voltage STBY = High 1 V
No Standby Standby Pin Voltage STBY = Low 0.5 V
Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2
transformer with 240Ω shunt resistor, 2xLO input power can be reduced
to –10dBm, without degrading the phase imbalance. See Figure 11 and
Figure 6.
Note 6: Differential between I
OUT+
and I
OUT–
(or differential between
Q
OUT+
and Q
OUT–
).
Note 7: The gain control voltage V
CTRL
is set in such a way that the
differential output voltage between I
OUT+
and I
OUT–
(or differential between
Q
OUT+
and Q
OUT–
) is 800mV
P-P
, with the given input power P
IF
.
Note 8: The typical parameter is defined as the mean of the absolute
values of the data distribution.
LT5506
4
5506fa
Supply Current vs Supply Voltage Gain and Noise Figure
vs Control Voltage at 3V Supply
Gain and Noise Figure
vs Control Voltage at 1.8V Supply Gain Flatness
vs Control Voltage at 1.8V Supply
Gain and Noise Figure
vs Control Voltage and VCC
Gain and Noise Figure
vs IF Frequency
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SUPPLY VOLTAGE (V)
1.75
SUPPLY CURRENT (mA)
32
30
28
26
24
22
20 2.25 2.75 3.25 3.75
5506 G01
4.25 4.75 5.25
–40°C
25°C
85°C
V
CTRL
(V)
0
G, NF (dB)
1.5
5506 G02
0.6
GAIN
NF
60
50
40
30
20
10
0
–10 0.3 0.9 1.2 1.8
GAIN AT 25°C
NF AT 25°C
GAIN AT –40°C
NF AT –40°C
GAIN AT 85°C
NF AT 85°C
f
IF
= 284MHz
f
2xLO
= 570MHz
VCTRL (V)
0
G, NF (dB)
1.5
5506 G03
0.6
GAIN
NF
60
50
40
30
20
10
0
–10 0.3 0.9 1.2 1.8
GAIN AT –40°C
NF AT –40°C
GAIN AT 25°C
NF AT 25°C
GAIN AT 85°C
NF AT 85°C
fIF = 284MHz
f2xLO = 570MHz
VCTRL (V)
0
–0.5
GAIN DEVIATIN FROM LINEAR FIT (dB)
–0.3
–0.1
0.1
0.3 0.6 0.9
5506 G04
1.2
0.3
0.5
–0.4
–0.2
0
0.2
0.4
1.5
–40°C
85°C
25°C
V
CTRL
(V)
0
G, NF (dB)
1.2 1.8
5506 G05
0.3
GAIN
NF
0.6 0.9 1.5
60
50
40
30
20
10
0
–10
GAIN AT 1.8V
NF AT 1.8V
GAIN AT 3V
NF AT 3V
GAIN AT 5.25V
NF AT 5.25V
f
IF
= 284MHz
f
2xLO
= 570MHz
IF FREQUENCY (MHz)
10
–10
0
G, NF (dB)
10
20
30
40
60
100 1000
5506 G06
50 GAIN, V
CTRL
= 1.6V
GAIN, V
CTRL
= 0.9V
GAIN, V
CTRL
= 0.2V
NF, V
CTRL
= 1.6V
NF, V
CTRL
= 0.9V
NF, V
CTRL
= 0.2V
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm
(Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC,
unless otherwise noted. (Note 3)
LT5506
5
5506fa
Total Harmonic Distortion
vs IF Input Power at 3V Supply
and 800mVP-P Differential Out
Total Harmonic Distortion
vs IF Input Power and IF
Frequency
Total Harmonic Distortion
vs IF Input Power at 1.8V Supply
and 800mVP-P Differential Out
IF INPUT POWER EACH TONE (dBm)
–60
THD (dBc)
–30
5506 G07
–50 –40 –20
–30
–35
–40
–45
–50
–55
–60
–65
–40°C
25°C
85°C
f
IF,1
= 280MHz
f
IF,2
= 280.1MHz
f
2xLO
= 570MHz
IF INPUT POWER EACH TONE (dBm)
–60
THD (dBc)
–30
5506 G08
–50 –40 –20
–30
–35
–40
–45
–50
–55
–60
f
IF
= 280MHz
f
IF
= 40MHz
800mV
P-P
DIFFERENTIAL OUT
3V SUPPLY
f
IF
= 550MHz
IF INPUT POWER EACH TONE (dBm)
–60
THD (dBc)
–30
5506 G09
–50 –40 –20
–30
–35
–40
–45
–50
–55
–60
f
IF,1
= 280MHz
f
IF,2
= 280.1MHz
f
2xLO
= 570MHz
25°C
–40°C
85°C
Total Harmonic Distortion vs IF
Input Power and Supply Voltage
IF INPUT POWER EACH TONE (dBm)
–60
THD (dBc)
–30
5506 G10
–50 –40 –20
–30
–35
–40
–45
–50
–55
–60
3V
1.8V
5.25V
800mV
P-P
DIFFERENTIAL OUT
f
IF,1
= 280MHz
f
IF,2
= 280.1MHz
f
2xLO
= 570MHz
LPF Frequency Response
vs Baseband Frequency
and Temperature
LPF Frequency Response
vs Baseband Frequency and
Supply Voltage
Total Harmonic Distortion
vs IF Input Power at 500mVP-P
Differential Out
IF INPUT POWER EACH TONE (dBm)
–45
–70
THD (dBc)
–65
–60
–55
–50
–45
–40
–40 –35 –30
–40°C
25°C85°C
–25
5506 G11
–20
f
IF,1
= 280MHz
f
IF,2
= 280.1MHz
f
2xLO
= 570MHz
BASEBAND FREQUENCY (MHz)
0
–25
MAGNITUDE (dB)
–20
–15
–10
–5
0
510
25°C
85°C
–40°C
15 20
5505 G12
25
V
CC
= 3V
BASEBAND FREQUENCY (MHz)
0
–25
MAGNITUDE (dB)
–20
–15
–10
–5
0
510
3V
1.8V
5.25V
15 20
5505 G13
25
IF INPUT CW POWER (dBm)
–40
0.2
IF DET OUTPUT (V)
0.4
0.6
0.8
1.0
1.2
1.4
–30
85°C–40°C
–20 –10 0
5506 G14
10
25°C
f
IF
= 280MHz
IF INPUT CW POWER (dBm)
–40
0.2
IF DET OUTPUT (V)
0.4
0.6
0.8
1.0
1.2
1.4
–30
85°C–40°C
–20 –10 0
5506 G15
10
25°C
f
IF
= 280MHz
IF Detector Output Voltage vs
IF Input CW Power at 3V Supply IF Detector Output Voltage vs
IF Input CW Power at 1.8V Supply
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm
(Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC,
unless otherwise noted. (Note 3)
LT5506
6
5506fa
IF Detector Output Voltage vs IF
Input CW Power and IF Frequency
IF Detector Output Voltage
vs IF Input CW Power and
Supply Voltage Phase Relation Between I and Q
Outputs vs LO Input Power
IF INPUT CW POWER (dBm)
–40
0.2
IF DET OUTPUT (V)
0.4
0.6
0.8
1.0
1.2
1.4
–30 –20 –10 0
5506 G16
10
3V
f
IF
= 280MHz
1.8V
5.25V
IF INPUT CW POWER (dBm)
–40
1.2
1.4
1.6
0
5506 G17
1.0
0.8
–30 –20 –10 10
0.6
0.4
0.2
IF DET OUTPUT (V)
V
CC
= 3V
f
IF
= 550MHz
f
IF
= 280MHz
f
IF
= 40MHz
LO INPUT POWER (dBm)
–20
95
94
93
92
91
90
89
88 –5 5
5506 G18
–15 –10 010
PHASE (DEG)
f
IF
= 284MHz, 25°C
f
IF
= 284MHz, –40°C
f
IF
= 284MHz, 85°C
f
IF
= 40MHz, 25°C
f
IF
= 550MHz, 25°C
GND (Pins 1, 4, 17): Ground. Pins 1 and 4 are connected
to each other internally. The Exposed Pad (Pin 17) is not
connected internally to Pins 1 and 4. For chip functionality,
the Exposed Pad and either Pin 1 or Pin 4 must be
connected to ground. For best RF performance, Pin 1,
Pin␣ 4 and the Exposed Pad should be connected to RF
ground.
IF
+
,
IF
–
(Pins 2, 3): Differential Inputs for the IF Signal.
Each pin must be DC grounded through an external
inductor or RF transformer with central ground tap. This
path should have a DC resistance lower than 2Ω to ground.
V
CC
(Pins 5 and 8): Power Supply. These pins should be
decoupled to ground using 1000pF and 0.1µF capacitors.
V
CTRL
(Pin 6): VGA Gain Control Input. This pin controls
the IF gain and its typical input voltage range is 0.2V to
1.7V. It is internally biased via a 25k resistor to 0.2V,
setting a low gain if the V
CTRL
pin is left floating.
IF DET (Pin 7): IF Detector Output. For strong IF input
signals, the DC level at this pin is a function of the IF input
signal level.
EN (Pin 9): Enable Input. When the enable pin voltage is
higher than 1V, the IC is completely turned on. When the
input voltage is less than 0.5V, the IC is turned off, except
the part of the circuit associated with standby mode.
2xLO
–
,
2xLO
+
(Pins 10, 11): Differential Inputs for the
2xLO Input. The 2xLO input frequency must be twice that
of the IF frequency. The internal bias voltage is V
CC
– 0.4V.
STBY (Pin 12): Standby Input. When the STBY pin is
higher than 1V, the standby mode circuit is turned on to
prebias the I/Q buffers. When the STBY pin is less than
0.5V, the standby mode circuit is turned off.
Q
OUT–
,
Q
OUT+
(Pins 13, 14): Differential Baseband Out-
puts of the Q Channel. Internally biased at V
CC
– 1.19V.
I
OUT–
, I
OUT+
(Pins 15, 16): Differential Baseband Outputs
of the I Channel. Internally biased at V
CC
– 1.19V.
UU
U
PI FU CTIO S
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm
(Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC,
unless otherwise noted. (Note 3)
LT5506
7
5506fa
BLOCK DIAGRA
W
2×LO
+
2×LO
–
IF
+
IF
–
IF DET
EN STBY
I
OUT+
I
OUT–
Q
OUT+
Q
OUT–
90°
0°
5506 BD
÷2
2
7
14
13
15
16
3
6
11
10
9 12
V
CTRL
VGA I-MIXER
Q-MIXER
CLIPPER
CLIPPER LPF
LPF
The LT5506 consists of variable gain amplifier (VGA),
I/Q demodulator, quadrature LO generator, hard clipping
amplifiers (clippers), lowpass filters (LPFs) and bias
circuitry.
The IF signal is fed to the inputs of the VGA. The VGA gain
is typically set by an external signal in such a way that the
amplified IF signal delivered to the I/Q mixers is constant.
The IF signal is then converted into I/Q baseband signals
using the I/Q down-converting mixers. The quadrature LO
signals that drive the mixers are internally generated from
the on-chip divide-by-two circuit. The I/Q signals are
passed through a pair of hard-clipping amplifiers (clip-
pers), which protect the subsequent lowpass filters from
overloading. After externally setting the required gain,
these amplifiers should not clip. However, in the event of
overload, they reduce the settling time of the (optional)
external AC coupling capacitors by preventing asymmetri-
cal charging and discharging effects. The second order
baseband lowpass filters remove the out-of-band noise
and harmonic content generated by the mixers and the
clippers. The I/Q baseband outputs are buffered by output
drivers.
VGA and Input Matching
The VGA has a nominal 60dB gain control range with a
frequency range of 40MHz to 500MHz. The inputs of the
VGA must have a DC return to ground. This can be done
using a transformer with a central tap (on secondary) or an
LC matching circuit with a matched impedance at the
frequency of interest and near zero impedance at DC. The
APPLICATIO S I FOR ATIO
WUUU
differential AC input impedance of the LT5506 is about
200Ω, thus a 1:4 (impedance ratio) RF transformer with
central tap can be used. In Figure 6, the evaluation board
schematic is shown using a 1:4 transformer. The mea-
sured input sensitivity of this board is about –82.6dBm for
a 10dB signal-to-noise ratio. In the case of an LC matching
circuit, the circuit of Figure 1 can be used. In Table 1 the
values are given for a range of IF frequencies. The match-
ing circuit of Figure 1 approaches 180° phase shift be-
tween IF
+
and IF
–
in a broad range around its center
frequency. However, some amplitude mismatch occurs if
the circuit is not tuned to the center frequency. This leads
to reduced circuit linearity performance, because one of
the inputs carries a higher signal compared to the perfectly
balanced case. A 10% frequency shift from the center
frequency results in about a 2dB gain difference between
the IF
+
and IF
–
inputs. This results in a 1.5dB higher IM3
contribution from the input stage which leads to a 0.75dB
drop in IIP3. Moreover, the IIP2 of the circuit is also
reduced which can lead to a higher second order harmonic
contribution. The circuit can be driven single ended, but
this is not recommended because it leads to a 3dB drop in
gain and a considerable increase in IM5 and IM7 compo-
nents. The single-ended noise figure increases by 4dB if
one IF input is directly grounded and increases by 1.5dB
if one IF input is grounded via a 1µH inductor. An IF input
cannot be left open or connected via a resistor to ground
because this will disturb the internal biasing, reducing the
gain, noise and linearity performance. For optimal perfor-
mance, it is important to keep the DC impedance to ground
LT5506
8
5506fa
APPLICATIO S I FOR ATIO
WUUU
of both IF inputs lower than 2Ω. In the matching network
of Figure 1, inductor L3 is used for supplying the DC bias
current to the IF
+
input. To keep the DC resistance of L3
below 2Ω, 120nH is used. This disturbs the matching
network slightly by causing the frequency where the S11
is minimal to be lower than the frequency where the
amplitudes of IF
+
and IF
–
are equal. To compensate for
this, the value of coupling capacitor C3 is lowered and will
contribute some correcting reactance. For low frequen-
cies, it might not be possible to find any practical inductor
value for L3 with DC resistance smaller than 2Ω. In that
case it is recommended to use a transformer with central
tap. The tolerance for the components in Figure 1 can be
10% for a return loss higher than 16dB and a gain
reduction due to mismatch less than 0.3dB.
It is possible to simplify the input matching circuit and
compromise the performance. In Figure 2a, the simplified
matching network is given.
Figure 1. IF Input Matching Network at 280MHz
C3
56pF
C1
5.6pF C2
5.6pF
L1
56nH
L3
120nH L2
56nH
TO IF
+
TO IF
–
5506 F01
IF
INPUT
Table 1. The Component Values of Matching Network L1, L2, L3,
C1, C2 and C3.
f
IF
(MHz) L1, L2(nH) C1, C2(pF) L3(nH) C3(pF)
50 340 34 1800 820
100 159 15.9 470 220
150 106 10.6 470 220
200 80 8.0 470 220
250 64 6.4 120 56
300 53 5.3 120 56
350 45 4.5 120 56
400 40 4.0 120 56
450 35 3.5 120 56
500 32 3.2 120 56
This matching network can deliver equal amplitudes to the
IF
+
and IF
–
inputs for a narrow frequency region, but the
phase difference between the inputs will not be exactly 180
degrees. In practice, the phase shift will be around 145
degrees, depending on the quality factor of the network.
This will result in a reduction in the gain. The higher the
chosen quality factor, the closer the phase difference will
approach 180 degrees. However, a higher quality factor
will reduce bandwidth and create more loss in the match-
ing network. For minimum board space, 0402 compo-
nents are used. The measured noise figure for maximum
gain with this matching network is about 8dB, and the
maximum gain about 57dB. Assuming 0402 inductors
with Q = 35, the insertion loss of this network is about
2.5dB. The tolerance for the components in Figure 2a can
be 10% for a return loss higher than 10dB and a gain
reduction due to mismatch less than 0.5dB. The measured
input sensitivity for this matching network (see also Fig-
ure␣ 11) is about –82.7dBm for a 10dB signal-to-noise
ratio.
The gain of the VGA is set by the voltage at the V
CTRL
pin.
For high gain settings, both the noise figure and the input
IP3 will be low. From a noise figure point of view, it is
advantageous to work as closely as possible to the maxi-
mum gain point. However, if the voltage at the V
CTRL
pin
is increased beyond the maximum gain point (where
additional increase in control voltage does not give an
increase in gain), the response time of the gain control
circuit is increased. If control speed is crucial, a few dB of
gain margin should be allowed from the highest gain point
to be sure that at all temperatures, the maximum gain
setting is not crossed. At low gain settings, the noise figure
and the input IP3 will be high. Optionally, the control
Figure 2a. Simplified IF Input Matching Network at 280MHz
and Figure 2b. Simplified Circuit Schematic of the IF Inputs
75Ω
C1
10pF
L1
15nH L2
15nH
TO IF
+
IF
–
IF
+
TO IF
–
5506 F02
IF
INPUT
1mA 1mA75Ω
V
BIAS
(2a) (2b)
LT5506
9
5506fa
APPLICATIO S I FOR ATIO
WUUU
voltage V
CTRL
can be set lower than 0.2V. The normal
range is from V
CTRL
= 0.2V to 1.7V, which results in a
nominal gain range from 0.9dB to 59dB. The linear-in-dB
gain relation with the V
CTRL
voltage still holds for control
voltages as low as –0.4 V. This results in an extended gain
control range of –19.7dB to 59dB. The V
CTRL
pin is a very
sensitive input because of its high input impedance and
therefore should be well shielded. Signal pickup on the
V
CTRL
pin can lead to spurs and increased noise floor in the
I/Q baseband outputs. It can degrade the linearity perfor-
mance and it can cause asymmetry in the two-tone test. If
control speed is not important, 1µF bypass capacitors are
recommended between V
CTRL
and ground.
A fast responding peak detector is connected to the VGA
input, sensitive to signal levels above the signal levels
where the VGA is operating in the linear range. It is active
from –22dBm up to 5dBm IF input signal levels. The DC
output voltage of this detector (IF DET) can be used by the
baseband controller to quickly determine the presence of
a strong input level at the desired channel, and adjust gain
accordingly. Figure 3a shows the simplified circuit sche-
matic of the IF DET output.
I/Q Demodulators
The quadrature demodulators are double balanced mix-
ers, down-converting the amplified IF signal from the VGA
into I/Q baseband signals. The quadrature LO signals are
generated internally from a double frequency external CW
signal. The nominal output voltage of the differential I/Q
baseband signals should be set to 0.8V
P-P
or lower,
depending on the linearity requirements. The magnitudes
of I and Q are well matched and their phases are 90° apart.
Quadrature LO Generator
The quadrature LO generator consists of a divide-by-two
circuit and LO buffers. An input signal (2xLO) with twice
the desired IF signal frequency is used as the clock for the
divide-by-two circuit, producing the quadrature LO signals
for the demodulators. The outputs are buffered and then
drive the down-converting mixers. With a fully differential
approach, the quadrature LO signals are well matched.
Second harmonic content (or higher order even harmon-
ics) in the external 2xLO signal can degrade the 90° phase
shift between I and Q. Therefore, such content should be
minimized. Figure 3b shows the simplified circuit sche-
matic of the 2xLO inputs. Depending on the application,
different 2xLO input matching networks can be chosen. In
Figure 4, three examples are given. The first network pro-
vides the best 2xLO input sensitivity because it can boost
up the 2xLO differential input signal using a narrow-band
resonant approach. The second network gives a wide-band
match, but the 2xLO input sensitivity is about 2dB lower.
The third network gives a simple and less expensive wide-
band match, but 2xLO input sensitivity drops by about 9dB.
The IF input sensitivity doesn’t change significantly using
either of the three 2xLO matching networks.
Baseband Circuit
The baseband circuit consists of I/Q hard limiters (clip-
pers), I/Q lowpass filters and I/Q output buffers. The hard
limiter operates as a linear amplifier normally. However, if
a high level input temporarily overloads the linear ampli-
fier, then the circuit will limit symmetrically, which will
help to prevent the filter and output buffer from overload-
ing. This speeds up recovery from an overload event,
Figure 3a. Simplified Circuit Schematic of the
IF DET Output and Figure 3b. The 2xLO Inputs
3.8k
1k
8k 8k
5506 F03
IF DET
V
CC
V
CC
+
–400mV
2xLO
+
2xLO
–
(3a) (3b)
Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band
Tuned to 570MHz, 4b) Wide Band, 4c) Single-Ended Wide Band
39nH
5506 F04
TO 2xLO
+
TO 2xLO
+
TO 2xLO
–
TO 2xLO
–
2xLO
INPUT
2xLO
INPUT
2xLO
INPUT
240Ω
1:4
3.3pF 100pF
100pF
3.3pF
56Ω
(4a) (4b) (4c)
TO 2xLO
+
TO 2xLO
–
LT5506
10
5506fa
APPLICATIO S I FOR ATIO
WUUU
which can occur during the gain settling. It also helps to
reduce the high frequency spectral content at the I/Q
outputs during overload. The second order integrated
lowpass filters are used for filtering the down-converted
baseband signals for both the I channel and the Q channel.
They serve as antialiasing and pulse-shaping filters. The
I/Q filters are well matched in gain response and group
delay. The 3dB corner frequency is typically 8.8MHz with
a group delay ripple of 5ns. The I/Q outputs can drive 2kΩ
in parallel with a maximum capacitive loading of 10pF,
from all four pins to ground. The outputs are internally
biased at V
CC
– 1.19V. Figure 5 shows the simplified
output circuit schematic of the I channel or Q channel.
The I/Q baseband outputs can be DC-coupled to the inputs
of a baseband chip. For AC-coupled applications with large
capacitors, the STBY pin can be used to pre-bias the
outputs to nominal V
CC
– 1.19V at much reduced current.
This mode draws only 3.6mA supply current. When the EN
pin is then driven high (>1V), the chip is quickly switched
to normal operating mode, avoiding the introduction of
large charging time constants. Table 2 shows the logic of
Table 2. The Logic of Different Operating Modes
EN STBY Comments
Low Low Shutdown Mode
Low High Standby Mode
High Low or High Normal Operation Mode
Figure 5. Simplified Circuit Schematic of I Channel
(or Q Channel) Outputs and STBY (or EN) Input
300µA
300µA
V
CC
I CHANNEL (OR
Q CHANNEL):
DIFFERENTIAL
SIGNALS
FROM LPF
I
OUT+
(OR Q
OUT+
)
I
OUT–
(OR Q
OUT–
)
5506 F05
STBY
(OR EN)
V
CC
22k
the EN pin and STBY pin. In both normal operating mode
and standby mode, the maximum discharging current is
about 300µA, and the maximum charging current is more
than 4mA. In Figure 5 the simplified circuit schematic of
the STBY (or EN) input is shown.
Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers
–
+
1
2
3
4
12
11
10
9
STBY
2XLO
+
2XLO
–
EN
GND
IF
+
IF
–
GND
U1
LT5506
T1, 1:4,TR-R
JTX-4-10T
MINI-CIRCUITS
IF
IN
R48
3.09k
R47
49.9Ω
R51
100Ω
C32
2.2pF R40
3.09k
C29
2.2pF
R52
240Ω
R36
20k
R35
20k
C34
0.1µF
C35
4.7µFC38
0.1µF
C37
0.1µF
SW1
1 = EN
2 = STBY
16
1
6
–
+
C45
22nF
77
6 6
4 4
3
2
3
2
J1
I
OUT
I
OUT+
I
OUT–
Q
OUT+
Q
OUT–
I
OUT+
I
OUT–
Q
OUT+
Q
OUT–
Q
OUT
J3 J4
C22
1µF
C33
0.1µF
C31
1µFR44
49.9ΩJ2
C30
1µF
U3
LT1809CS U2
LT1809CS
V
CC1
V
CC2
V
CTRL
V
CC
V
CTRL
V
CC
C26
1.8pF
C25
1.5pF
C16
1nF
C15
1nF C39
1µF
V
CC3
C36
4.7µF
R46
3.09k
R45
1k
C28
0.1µF
R42
2k
R49
2k
R39
3.09k
R41
1k
R50
2k
C27
0.1µF
R43
2k
2XLO
OVERLOAD
IF
DET
16 15 14 13
5 6 7 8 0 GND
NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED
COMPONENTS ARE INCLUDED FOR MEASUREMENT PURPOSES ONLY.
BOARD NUMBER: DC468A (NARROW-BAND VERSION: DC535A)
C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL
5506 F04
T2, 1:4, TR-R
JTX-4-10T
MINI-CIRCUITS
C43
22nF
LT5506
11
5506fa
Figure 7. Component Side Silkscreen of Evaluation Board Figure 8. Component Side Layout of Evaluation Board
Figure 9. Bottom Side Silkscreen of Evaluation Board Figure 10. Bottom Side Layout of Evaluation Board
APPLICATIO S I FOR ATIO
WUUU
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT5506
12
5506fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
LT/TP 1003 1K REV A • PRINTED IN USA
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Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)
EN
STBY
V
CC
0°
90°
1.8V
1µF 1nF
280MHz
IF SAW BP FILTER
10pF
5506 F11
f/2
LT5506
16
15
7
6
14
13
12
9
2
3
11
10
15nH
15nH
39nH
3.3pF
3.3pF
IF DET
V
CTRL
I-MIXER
Q-MIXER
HARD
CLIPPER
HARD
CLIPPER LPF
LPF
5, 8
RX
FRONT END
MAIN
SYNTHESIZER
AUX
SYNTHESIZER
RX INPUT:
2.4GHz TO 2.5GHz
Q-OUTPUTS
I-OUTPUTS A/D
A/D
D/A
A/D
BASEBAND
PROCESSOR
0,1,4
1ST LO,
2.12GHz
TO 2.22GHz
2ND LO,
560MHz
–10dBm
VGA
PACKAGE DESCRIPTIO
U
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
APPLICATIO S I FOR ATIO
WUUU
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
PIN 1
TOP MARK
0.55 ± 0.20
1615
1
2
BOTTOM VIEW—EXPOSED PAD
2.15 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.30 ± 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
(UF) QFN 0503
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.72 ±0.05
0.30 ±0.05
0.65 BSC
2.15 ± 0.05
(4 SIDES)
2.90 ± 0.05
4.35 ± 0.05
PACKAGE
OUTLINE
