1
LTC1735
1735fc
High Efficiency
Synchronous Step-Down
Switching Regulator
The LTC
®
1735 is a synchronous step-down switching
regulator controller that drives external N-channel power
MOSFETs using a fixed frequency architecture. Burst
Mode
TM
operation provides high efficiency at low load
currents. The precision 0.8V reference is compatible with
future generation microprocessors. OPTI-LOOP compen-
sation allows the transient response to be optimized over
a wide range of output capacitance and ESR values.
The operating frequency (synchronizable up to 500kHz) is
set by an external capacitor allowing maximum flexibility
in optimizing efficiency. A forced continuous control pin
reduces noise and RF interference and can assist second-
ary winding regulation by disabling Burst Mode operation
when the main output is lightly loaded.
Protection features include internal foldback current lim-
iting, output overvoltage crowbar and optional short-
circuit shutdown. Soft-start is provided by an external
capacitor that can be used to properly sequence supplies.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 4V to 30V (36V maximum).
■
Synchronizable/Programmable Fixed Frequency
■
OPTI-LOOP
TM
Compensation Minimizes C
OUT
■
±
1% Output Voltage Accuracy
■
Dual N-Channel MOSFET Synchronous Drive
■
Wide V
IN
Range: 4V to 36V Operation
■
V
OUT
Range: 0.8V to 6V
■
Internal Current Foldback
■
Output Overvoltage Crowbar Protection
■
Latched Short-Circuit Shutdown Timer
with Defeat Option
■
Very Low Dropout Operation: 99% Duty Cycle
■
Forced Continuous Control Pin
■
Optional Programmable Soft-Start
■
Remote Output Voltage Sense
■
Power Good Output (LTC1735F Only)
■
Logic Controlled Micropower Shutdown: I
Q
< 25µA
■
LTC1435 Pin Compatible with
Minor Component Changes
■
Available in 16-Lead Narrow SSOP, SO Packages and
20-Lead TSSOP Package (LTC1735F Only)
Figure 1. High Efficiency Step-Down Converter
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.
■
Notebook and Palmtop Computers, PDAs
■
Cellular Telephones and Wireless Modems
■
DC Power Distribution Systems
C
OSC
RUN/SS
TG
BOOST
LTC1735
C
B
0.22µF
100pF
C
C
330pF
R
C
33k R
SENSE
0.005ΩV
OUT
1.6V
9A
C
OUT
: PANASONIC EEFUEOG181R
C
IN
: MARCON THCR70E1H226ZT
L1: PANASONIC ETQP6F2R0HFA
R
SENSE
: IRC LRF2010-01-R005J
1000pF
C
SS
0.1µFC
OSC
47pF
+
4.7µF
+
C
OUT
180µF
4V
×4
SP
C
IN
22µF
50V
M1
FDS6680A
M2
FDS6680A
1735 F01
D
B
CMDSH-3
D1
MBRS340T3
V
IN
5V TO 24V
L1
2µH
C
C2
100pF
R2
20k
1%
R1
20k
1%
SGND
V
OSENSE
SENSE
–
SENSE
+
INTV
CC
BG
PGND
I
TH
SW
V
IN
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1735
1735fc
ABSOLUTE AXI U RATI GS
W
WW
U
Input Supply Voltage (V
IN
).........................36V to –0.3V
Topside Driver Supply Voltage (BOOST)....42V to –0.3V
Switch Voltage (SW) ....................................36V to –5V
EXTV
CC
Voltage ...........................................7V to –0.3V
Boosted Driver Voltage (BOOST – SW) .......7V to –0.3V
SENSE
+
, SENSE
–
Voltages ..........1.1 (INTV
CC
) to –0.3V
FCB Voltage ............................(INTV
CC
+ 0.3V) to –0.3V
I
TH
, V
OSENSE
Voltages ...............................2.7V to –0.3V
RUN/SS, PGOOD (LTC1735F Only)
Voltages.......................................................7V to –0.3V
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
Peak Driver Output Current <10µs (TG, BG) .............. 3A
INTV
CC
Output Current ......................................... 50mA
Operating Ambient Temperature Range
LTC1735C ............................................... 0°C to 85°C
LTC1735I/LTC1735E (Note 8) ............ –40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
(Note 1)
PACKAGE/ORDER I FOR ATIO
UUW
ORDER PART
NUMBER
LTC1735CGN
LTC1735CS
LTC1735IGN
LTC1735IS
LTC1735EGN
T
JMAX
= 125°C, θ
JA
= 130°C/W (GN)
T
JMAX
= 125°C, θ
JA
= 110°C/W (S)
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
GN PACKAGE
16-LEAD NARROW
PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
GN PART MARKING
1735
1735I
1735E
Consult LTC marketing for parts specified with wider operating temperature ranges.
ORDER PART
NUMBER
LTC1735CF
LTC1735IF
T
JMAX
= 125°C, θ
JA
= 110°C/W
1
2
3
4
5
6
7
8
9
10
TOP VIEW
F PACKAGE
20-LEAD PLASTIC TSSOP
20
19
18
17
16
15
14
13
12
11
NC
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
PGOOD
SENSE
–
SENSE
+
NC
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
NC
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
I
VOSENSE
Feedback Current (Note 3) –4 –25 nA
V
OSENSE
Feedback Voltage (Note 3) ●0.792 0.8 0.808 V
∆V
LINEREG
Reference Voltage Line Regulation V
IN
= 3.6V to 30V (Note 3) 0.001 0.02 %/V
∆V
LOADREG
Output Voltage Load Regulation (Note 3)
Measured in Servo Loop; V
ITH
= 0.7V ● 0.1 0.3 %
Measured in Servo Loop; V
ITH
= 2V ●–0.1 –0.3 %
DF Max Maximum Duty Factor In Dropout 98 99.4 %
g
m
Transconductance Amplifier g
m
1.3 mmho
V
FCB
Forced Continuous Threshold ●0.76 0.8 0.84 V
I
FCB
Forced Continuous Current V
FCB
= 0.85V – 0.17 –0.3 µA
3
LTC1735
1735fc
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
V
OVL
Feedback Overvoltage Lockout ●0.84 0.86 0.88 V
I
Q
Input DC Supply Current (Note 4)
Normal Mode 450 µA
Shutdown V
RUN/SS
= 0V 15 25 µA
V
RUN/SS
Run Pin Start Threshold V
RUN/SS
, Ramping Positive 1.0 1.5 1.9 V
V
RUN/SS
Run Pin Begin Latchoff Threshold V
RUN/SS
, Ramping Positive 4.1 4.5 V
I
RUN/SS
Soft-Start Charge Current V
RUN/SS
= 0V –0.7 –1.2 µA
I
SCL
RUN/SS Discharge Current Soft Short Condition, V
OSENSE
= 0.5V, 0.5 2 4 µA
V
RUN/SS
= 4.5V
UVLO Undervoltage Lockout Measured at V
IN
Pin (V
IN
Ramping Down) ●3.5 3.9 V
∆V
SENSE(MAX)
Maximum Current Sense Threshold V
OSENSE
= 0.7V ●60 75 85 mV
I
SENSE
Sense Pins Total Source Current V
SENSE–
= V
SENSE+
= 0V 60 80 µA
t
ON(MIN)
Minimum On-Time Tested with a Square Wave (Note 6) 160 200 ns
TG Transition Time: (Note 7)
TG t
r
Rise Time C
LOAD
= 3300pF 50 90 ns
TG t
f
Fall Time C
LOAD
= 3300pF 50 90 ns
BG Transition Time: (Note 7)
BG t
r
Rise Time C
LOAD
= 3300pF 50 90 ns
BG t
f
Fall Time C
LOAD
= 3300pF 40 80 ns
TG/BG t
1D
Top Gate Off to Synchronous C
LOAD
= 3300pF Each Driver 100 ns
Gate On Delay Time
TG/BG t
2D
Synchronous Gate Off to Top C
LOAD
= 3300pF Each Driver 70 ns
Gate On Delay Time
Internal V
CC
Regulator
V
INTVCC
Internal V
CC
Voltage 6V < V
IN
< 30V, V
EXTVCC
= 4V 5.0 5.2 5.4 V
V
LDO(INT)
Internal V
CC
Load Regulation I
CC
= 0 to 20mA, V
EXTVCC
= 4V 0.2 1 %
V
LDO(EXT)
EXTV
CC
Drop Voltage I
CC
= 20mA, V
EXTVCC
= 5V 130 200 mV
V
EXTVCC
EXTV
CC
Switchover Voltage I
CC
= 20mA, EXTV
CC
Ramping Positive ●4.5 4.7 V
V
EXTVCC(HYS)
EXTV
CC
Hysteresis 0.2 V
Oscillator
f
OSC
Oscillator Frequency C
OSC
= 43pF (Note 5) 265 300 335 kHz
f
H
/f
OSC
Maximum Sync Frequency Ratio 1.3
f
FCB(SYNC)
FCB Pin Threshold For Sync Ramping Negative 0.9 1.2 V
PGOOD Output (LTC1735F Only)
V
PGL
PGOOD Voltage Low I
PGOOD
= 2mA 110 200 mV
I
PGOOD
PGOOD Leakage Current V
PGOOD
= 5V ±1µA
V
PG
PGOOD Trip Level V
OSENSE
with Respect to Set Output Voltage
V
OSENSE
Ramping Negative –6.0 –7.5 –9.5 %
V
OSENSE
Ramping Positive 6.0 7.5 9.5 %
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired. Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LTC1735CS, LTC1735IS: T
J
= T
A
+ (P
D
• 110 °C/W)
LTC1735CGN, LTC1735IGN, LTC1735EGN: T
J
= T
A
+ (P
D
• 130°C/W)
LTC1735CF, LTC1735IF: T
J
= T
A
+ (P
D
• 110°C/W)
4
LTC1735
1735fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency vs Load Current
(3 Operating Modes) Efficiency vs Load Current Efficiency vs Input Voltage
LOAD CURRENT (A)
0.001
EFFICIENCY (%)
60
70
80 BURST
SYNC
10
1735 G01
50
40
20 0.01 0.1 1
30
100
90
V
IN
= 10V
V
OUT
= 3.3V
R
S
= 0.01Ω
f
O
= 300kHz
EXTV
CC
OPEN
CONTINUOUS
LOAD CURRENT (A)
0.01 0.1 1 10
EFFICIENCY (%)
1735 G02
100
90
80
70
60
50
40
V
IN
= 5V
EXTV
CC
= 5V
FIGURE 1
V
IN
= 24V
V
IN
= 15V
INPUT VOLTAGE (V)
0
70
EFFICIENCY (%)
75
80
85
90
100
510 15 20
1735 G03
25 30
95
EXTVCC = 5V
VOUT = 1.6V
FIGURE 1
IOUT = 5A
IOUT = 0.5A
Efficiency vs Input Voltage Load Regulation VIN – VOUT Dropout Voltage
vs Load Current
INPUT VOLTAGE (V)
0
70
EFFICIENCY (%)
75
80
85
90
100
510 15 20
1735 G04
25 30
95
EXTVCC OPEN
VOUT = 1.6V
FIGURE 1
IOUT = 5A
IOUT = 0.5A
LOAD CURRENT (A)
0
NORMALIZED V
OUT
(%)
–0.2
–0.1
8
1735 G05
–0.3
–0.4 24610
0FCB = 0V
V
IN
= 15V
FIGURE 1
LOAD CURRENT (A)
0
0
V
IN
– V
OUT
(mV)
500
400
300
200
100
2468
1735 G06
10
R
SENSE
= 0.005Ω
V
OUT
= 5V – 5% DROP
Note 3: The LTC1735 is tested in a feedback loop that servos V
OSENSE
to
the balance point for the error amplifier (V
ITH
= 1.2V).
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5: Oscillator frequency is tested by measuring the C
OSC
charge
current (I
OSC
) and applying the formula:
fCpF I I
OSC OSC CHG DIS
=+
+
8 477 10
11
11
11 1
.()
()
–
Note 6: The minimum on-time condition corresponds to an inductor peak-
to-peak ripple current ≥40% of I
MAX
(see Minimum On-Time
Considerations in the Applications Information section).
Note 7: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 8: The LTC1735E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC1735I specifications are
guaranteed over the full –40°C to 85°C operating temperature range.
ELECTRICAL CHARACTERISTICS
5
LTC1735
1735fc
Maximum Current Sense Threshold
vs Normalized Output Voltage
(Foldback)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Maximum Current Sense Threshold
vs VRUN/SS
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Maximum Current Sense Threshold
vs ITH Voltage VITH vs VRUN/SS
Maximum Current Sense Threshold
vs Temperature
NORMALIZED OUTPUT VOLTAGE (%)
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
40
50
60
100
1735 G10
30
20
025 50 75
10
80
70
V
RUN/SS
(V)
0
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
20
40
60
80
1234
1735 G11
56
V
SENSE(CM)
= 1.6V
COMMON MODE VOLTAGE (V)
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
72
76
80
4
1735 G12
68
64
60 1235
V
ITH
(V)
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
30
50
70
90
2
1735 G13
10
–10
20
40
60
80
0
–20
–30 0.5 11.5 2.5
V
RUN/SS
(V)
0
0
V
ITH
(V)
0.5
1.0
1.5
2.0
2.5
1234
1735 G15
56
V
OSENSE
= 0.7V
TEMPERATURE (°C)
–40
60
MAXIMUM CURRENT SENSE THRESHOLD (mV)
65
70
75
80
–15 10 35 60
1735 G18
85 110 135
V
SENSE(CM)
= 1.6V
Input and Shutdown Currents
vs Input Voltage INTVCC Line Regulation
INPUT VOLTAGE (V)
05
0
INPUT CURRENT (µA)
SHUTDOWN CURRENT (µA)
200
500
10 20 25
1735 G07
100
400
300
0
40
100
20
80
60
15 30 35
EXTVCC OPEN
SHUTDOWN
EXTVCC = 5V
INPUT VOLTAGE (V)
0
INTV
CC
VOLTAGE (V)
4
5
6
15 25
1735 G08
3
2
510 20 30 35
1
0
1mA LOAD
EXTVCC Switch Drop
vs INTVCC Load Current
INTV
CC
LOAD CURRENT (mA)
0
EXTV
CC
– INTV
CC
(mV)
300
400
500
40
1735 G09
200
100
010 20 30 50
6
LTC1735
1735fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–40 –15
250
FREQUENCY (kHz)
270
300
10 60 85
1735 G19
260
290
280
35 110 135
C
OSC
= 47pF
RUN/SS Pin Current
vs Temperature
TEMPERATURE (°C)
–40 –15
–5
RUN/SS CURRENT (µA)
–3
0
10 60 85
1735 G20
–4
–1
–2
35 110 135
V
RUN/SS
= 0V
TEMPERATURE (°C)
–40 –15
–1.0
FCB CURRENT (µA)
–0.6
0
10 60 85
1735 G21
–0.8
–0.2
–0.4
35 110 135
V
FCB
= 0.85V
FCB Pin Current vs Temperature
Output Current vs Duty Cycle
SENSE Pins Total Source Current ITH Voltage vs Load Current
DUTY CYCLE (%)
0
0
AVERAGE OUTPUT CURRENT IOUT/IMAX (%)
20
40
60
80
100
20 40 60 80
1735 G14
100
fSYNC = fO
IOUT/IMAX (SYNC)
IOUT/IMAX
(FREE RUN)
V
SENSE
COMMON MODE VOLTAGE (V)
0
I
SENSE
(µA)
0
1735 G16
–50
–100 24
50
100
6
LOAD CURRENT (A)
0
0
ITH VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
1234
1735 G17
56
VIN = 10V
VOUT = 3.3V
RSENSE = 0.01Ω
fO = 300kHz
CONTINUOUS
MODE
Burst Mode
OPERATION
SYNCHRONIZED f = fO
Supply Current in Shutdown
vs VRUN/SS
V
RUN/SS
0
0
SUPPLY CURRENT (µA)
10
30
40
50
100
70
0.5 1
1735 G28
20
80
90
60
1.5 2
TEMPERATURE (°C)
–50
0
SUPPLY CURRENT (µA)
5
10
15
20
25
30
0 50 100 150
1735 G29
Supply Current in Shutdown
vs Temperature
7
LTC1735
1735fc
PI FU CTIO S
UUU
VOUT(RIPPLE)
(Burst Mode Operation) Load Step (Burst Mode Operation) Load Step (Continuous Mode)
V
OUT
50mV/DIV
I
L
5A/DIV
0A TO 10µs/DIV
9A LOAD STEP
FCB = 0V
V
IN
= 15V
V
OUT
= 1.6V
V
OUT
50mV/DIV
I
L
5A/DIV
V
OUT
20mV/DIV
I
L
5A/DIV
FCB = 5V 5µs/DIV
V
IN
= 15V
V
OUT
= 1.6V
10mA TO 10µs/DIV
9A LOAD STEP
FCB = 5V
V
IN
= 15V
V
OUT
= 1.6V
1735 G27 1735 G26 1735 G25
FIGURE 1 FIGURE 1 FIGURE 1I
LOAD
= 1.5A
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Start-Up
V
OUT
1V/DIV
V
RUN/SS
5V/DIV
I
L
5A/DIV
V
IN
= 15V 5ms/DIV
V
OUT
= 1.6V
R
LOAD
= 0.16Ω
VOUT(RIPPLE) (Synchronized)
V
OUT
10mV/DIV
I
L
5A/DIV
EXT SYNC f = f
O
10µs/DIV
V
IN
= 15V
V
OUT
= 1.6V
V
OUT
20mV/DIV
I
L
5A/DIV
VOUT(RIPPLE)
(Burst Mode Operation)
FCB = 5V 50µs/DIV
V
IN
= 15V
V
OUT
= 1.6V
1735 G22 1735 G23 1735 G24
FIGURE 1 FIGURE 1I
LOAD
= 10mA I
LOAD
= 50mA
C
OSC
: External capacitor C
OSC
from this pin to ground sets
the operating frequency.
RUN/SS: Combination of Soft-Start and Run Control In-
puts. A capacitor to ground at this pin sets the ramp time
to full output current. The time is approximately 1.25s/µF.
Forcing this pin below 1.5V causes the device to shut
down. (See Applications Information section for quiescent
current note.) In shutdown all functions, including INTV
CC
,
are disabled. Latchoff overcurrent protection is also in-
voked via this pin as described in the Applications Infor-
mation section.
I
TH
: Error Amplifier Compensation Point. The current
comparator threshold increases with this control voltage.
Nominal voltage range for this pin is 0V to 2.4V.
FCB: Forced Continuous/Synchronization Input. Tie this
pin to ground for continuous synchronous operation, to a
resistive divider from the secondary output when using a
secondary winding or to INTV
CC
to enable Burst Mode
operation at low load currents. Clocking this pin with a
signal above 1.5V
P–P
disables Burst Mode operation but
allows cycle-skipping at low load currents and synchro-
nizes the internal oscillator with the external clock. The
FCB pin must not be driven when the device is shut down
(RUN/SS pin low).
SGND: Small-Signal Ground. All small-signal components
such as C
OSC
, C
SS
, the feedback divider plus the loop com-
pensation resistor and capacitor(s) should single-point tie
to this pin. This pin should, in turn, connect to PGND.
8
LTC1735
1735fc
V
OSENSE
: Receives the feedback voltage from an external
resistive divider across the output.
SENSE
–
: The (–) Input to the Current Comparator.
SENSE
+
: The (+) Input to the Current Comparator. Built-in
offsets between SENSE
–
and SENSE
+
pins in conjunction
with R
SENSE
set the current trip threshold.
PGOOD (LTC1735F Only): Open-Drain Logic Output.
PGOOD is pulled to ground when the voltage on the
V
OSENSE
pin is not within ±7.5% of its set point.
EXTV
CC
: Input to the Internal Switch Connected to INTV
CC
.
This switch closes and supplies V
CC
power whenever
EXTV
CC
is higher than 4.7V. See EXTV
CC
connection in the
Applications Information section. Do not exceed 7V on
this pin and ensure EXTV
CC
≤ V
IN
.
PGND: Driver Power Ground. Connects to the source of
bottom N-channel MOSFET, the anode of the Schottky
diode, and the (–) terminal of C
IN
.
BG: High Current Gate Drive for Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTV
CC
.
INTV
CC
: Output of the Internal 5.2V Regulator and EXTV
CC
Switch. The driver and control circuits are powered from
this voltage. Decouple to power ground with a 1µF ceramic
capacitor placed directly adjacent to the IC together with a
minimum of 4.7µF tantalum or other low ESR capacitor.
V
IN
: Main Supply Pin. Must be closely decoupled to power
ground.
SW: Switch Node Connection to Inductor and Bootstrap
Capacitor. Voltage swing at this pin is from a Schottky
diode (external) voltage drop below ground to V
IN
.
BOOST: Supply to Topside Floating Driver. The bootstrap
capacitor is returned to this pin. Voltage swing at this pin
is from a diode drop below INTV
CC
to (V
IN
+ INTV
CC
).
TG: High Current Gate Drive for Top N-Channel MOSFET.
This is the output of a floating driver with a voltage swing
equal to INTV
CC
superimposed on the switch node voltage
SW.
PI FU CTIO S
UUU
9
LTC1735
1735fc
FU CTIO AL DIAGRA
UU
W
SW
–
+
+
–
0.86V
–
+
0.55V
2.4V
0.8V 0.86V
I1+
–I2
+
–EA
A
BURST
DISABLE
FC
OV
gm =1.3m
B
–
+
4.7V
IREV
+
–
+
–FFC
S
RQ
DROP
OUT
DET
0.8V
REF
SWITCH
LOGIC
SD
6V
R1
RUN/SS
CSS
RC
VOSENSE VFB
1.2µARUN
SOFT-
START
+
OVER-
CURRENT
LATCHOFF
SD
ITH
CC
0.17µA
OSC
4(VFB)BUFFERED
ITH
SLOPE COMP
+– –+
3mV
ICMP
R2
2k 45k
BOT
TOP ON
FORCE BOT
45k
30k 30k
SENSE+SENSE–
SYNC
1.2V 0.8V
C
TOP
UVL
BOT
INTVCC 5.2V
LDO
REG
VIN +
CINTVCC
VOUT
VSEC
INTVCC
BG
PGND
VIN
VIN
BOOST
TG
INTVCC
CB
DB
D1
COSC
+CIN
+CSEC
+COUT
EXTVCC
FCBSGNDCOSC
RSENSE
1735 FD
PGOOD
LTC1735F
ONLY
Ω
+
–
0.74V
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC1735 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch and turned off when the main current
comparator I1 resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on Pin 3 (ITH), which is the output of error
amplifier EA. Pin␣ 6 (VOSENSE), described in the pin func-
tions, allows EA to receive an output feedback voltage VFB
from an external resistive divider. When the load current
increases, it causes a slight decrease in VFB relative to the
0.8V refer
ence, which in turn causes the I
TH
voltage to
increase until the average inductor current matches the
new load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I
2
, or
the beginning of the next cycle.
The top MOSFET driver is powered from a floating boot-
strap capacitor C
B
. This capacitor is normally recharged
from INTV
CC
through an external diode when the top
MOSFET is turned off. As V
IN
decreases towards V
OUT
, the
converter will attempt to turn on the top MOSFET continu-
ously (“dropout’’). A dropout counter detects this condi-
tion and forces the top MOSFET to turn off for about 500ns
every tenth cycle to recharge the bootstrap capacitor.
10
LTC1735
1735fc
OPERATIO
U
(Refer to Functional Diagram)
When the FCB pin is driven by an external oscillator, a low
noise cycle-skipping mode is invoked and the internal
oscillator is synchronized to the external clock by com-
parator C. In this mode the 25% minimum inductor
current clamp is removed, providing constant frequency
discontinuous operation over the widest possible output
current range. This constant frequency operation is not
quite as efficient as Burst Mode operation, but provides a
lower noise, constant frequency spectrum.
Tying the FCB pin to ground enables forced continuous
operation. This is the least efficient mode, but is desirable
in certain applications. The output can source or sink
current in this mode. When sinking current while in forced
continuous operation, current will be forced back into the
main power supply potentially boosting the input supply to
dangerous voltage levels—BEWARE.
Foldback Current, Short-Circuit Detection and
Short-Circuit Latchoff
The RUN/SS capacitor, C
SS
, is used initially to limit the
inrush current of the switching regulator. After the con-
troller has been started and been given adequate time to
charge up the output capacitors and provide full load cur-
rent, C
SS
is used as a short-circuit time-out circuit. If the
output voltage falls to less than 70% of its nominal output
voltage, C
SS
begins discharging on the assumption that
the output is in an overcurrent and/or short-circuit condi-
tion. If the condition lasts for a long enough period as
determined by the size of C
SS
, the controller will be shut
down until the RUN/SS pin voltage is recycled. This built-
in latchoff can be overridden by providing a current >5µA
at a compliance of 5V to the RUN/SS pin. This current
shortens the soft-start period but also prevents net dis-
charge of C
SS
during an overcurrent and/or short-circuit
condition. Foldback current limiting is activated when the
output voltage falls below 70% of its nominal level whether
or not the short-circuit latchoff circuit is enabled.
The main control loop is shut down by pulling Pin 2
(RUN/SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches 1.5V, the main control loop is enabled with the
I
TH
voltage clamped at approximately 30% of its maximum
value. As C
SS
continues to charge, I
TH
is gradually re-
leased allowing normal operation to resume. If V
OUT
has
not reached 70% of its final value when C
SS
has charged
to 4.1V, latchoff can be invoked as described in the
Applications Information section.
The internal oscillator can be synchronized to an external
clock applied to the FCB pin and can lock to a frequency
between 90% and 130% of its nominal rate set by capaci-
tor C
OSC
.
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious
conditions that may overvoltage the output. In this case,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
Foldback current limiting for an output shorted to ground
is provided by amplifier A. As V
OSENSE
drops below 0.6V,
the buffered I
TH
input to the current comparator is gradu-
ally pulled down to a 0.86V clamp. This reduces peak
inductor current to about 1/4 of its maximum value.
Low Current Operation
The LTC1735 has three low current modes controlled by
the FCB pin. Burst Mode operation is selected when the
FCB pin is above 0.8V (typically tied to INTV
CC
). In Burst
Mode operation, if the error amplifier drives the I
TH
voltage
below 0.86V, the buffered I
TH
input to the current com-
parator will be clamped at 0.86V. The inductor current
peak is then held at approximately 20mV/R
SENSE
(about
1/4 of maximum output current). If I
TH
then drops below
0.5V, the Burst Mode comparator B will turn off both
MOSFETs to maximize efficiency. The load current will be
supplied solely by the output capacitor until I
TH
rises
above the 60mV hysteresis of the comparator and switch-
ing is resumed. Burst Mode operation is disabled by
comparator F when the FCB pin is brought below 0.8V.
This forces continuous operation and can assist second-
ary winding regulation.
11
LTC1735
1735fc
INTV
CC
/EXTV
CC
POWER
Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1735 is derived from the
INTV
CC
pin. When the EXTV
CC
pin is left open, an internal
5.2V low dropout regulator supplies the INTV
CC
power
from V
IN
. If EXTV
CC
is raised above 4.7V, the internal
regulator is turned off and an internal switch connects
EXTV
CC
to INTV
CC
. This allows a high efficiency source,
such as the primary or a secondary output of the converter
itself, to provide the INTV
CC
power. Voltages up to 7V can
be applied to EXTV
CC
for additional gate drive capability.
To provide clean start-up and to protect the MOSFETs,
undervoltage lockout is used to keep both MOSFETs off
until the input voltage is above 3.5V.
PGOOD (LTC1735F Only)
A window comparator monitors the output voltage and its
open-drain output is pulled low when the divided down
output voltage is not within ±7.5% of the reference voltage
of 0.8V.
OPERATIO
U
(Refer to Functional Diagram)
APPLICATIO S I FOR ATIO
WUUU
The basic LTC1735 application circuit is shown in Figure␣ 1
on the first page. External component selection is driven
by the load requirement and begins with the selection of
R
SENSE
. Once R
SENSE
is known, C
OSC
and L can be chosen.
Next, the power MOSFETs and D1 are selected. The
operating frequency and the inductor are chosen based
largely on the desired amount of ripple current. Finally, C
IN
is selected for its ability to handle the large RMS current
into the converter and C
OUT
is chosen with low enough
ESR to meet the output voltage ripple and transient speci-
fications. The circuit shown in Figure 1 can be configured
for operation up to an input voltage of 28V (limited by the
external MOSFETs).
R
SENSE
Selection for Output Current
R
SENSE
is chosen based on the required output current.
The LTC1735 current comparator has a maximum thresh-
old of 75mV/R
SENSE
and an input common mode range of
SGND to 1.1(INTV
CC
). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current I
MAX
equal to the peak value less
half the peak-to-peak ripple current, ∆I
L
.
Allowing a margin for variations in the LTC1735 and
external component values yields:
RmV
I
SENSE MAX
=50
C
OSC
Selection for Operating Frequency and
Synchronization
The choice of operating frequency and inductor value is a
trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation re-
quires more inductance for a given amount of ripple
current.
The LTC1735 uses a constant frequency architecture with
the frequency determined by an external oscillator capaci-
tor C
OSC
. Each time the topside MOSFET turns on, the
voltage on C
OSC
is reset to ground. During the on-time,
C
OSC
is charged by a fixed current. When the voltage on the
capacitor reaches 1.19V, C
OSC
is reset to ground. The
process then repeats.
The value of C
OSC
is calculated from the desired operating
frequency assuming no external clock input on the FCB
pin:
CpFFrequency
OSC
() .( )–=
16110 11
7
A graph for selecting C
OSC
versus frequency is shown in
Figure 2. The maximum recommended switching fre-
quency is 550kHz .
12
LTC1735
1735fc
The internal oscillator runs at its nominal frequency (f
O
)
when the FCB pin is pulled high to INTV
CC
or connected to
ground. Clocking the FCB pin above and below 0.8V will
cause the internal oscillator to injection lock to an external
clock signal applied to the FCB pin with a frequency
between 0.9f
O
and 1.3f
O
. The clock high level must exceed
1.3V for at least 0.3µs and the clock low level must be less
than 0.3V for at least 0.3µs. The top MOSFET turn-on will
synchronize with the rising edge of the clock.
Attempting to synchronize to too high an external fre-
quency (above 1.3f
O
) can result in inadequate slope com-
pensation and possible loop instability. If this condition
exists simply lower the value of C
OSC
so f
EXT
= f
O
according
to Figure 2.
APPLICATIO S I FOR ATIO
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of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic trade
off, the effect of inductor value on ripple current and low
current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current ∆I
L
decreases with higher induc-
tance or frequency and increases with higher V
IN
or V
OUT
:
∆IfLVV
V
L OUT OUT
IN
=
11
()() –
Accepting larger values of ∆I
L
allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆I
L
= 0.3 to 0.4(I
MAX
). Remember,
the maximum ∆I
L
occurs at the maximum input voltage.
The inductor value also has an effect on low current
operation. The transition to low current operation begins
when the inductor current reaches zero while the bottom
MOSFET is on. Burst Mode operation begins when the
average inductor current required results in a peak current
below 25% of the current limit determined by R
SENSE
.
Lower inductor values (higher ∆I
L
) will cause this to occur
at higher load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ
®
cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
Figure 2. Timing Capacitor Value
OPERATING FREQUENCY (kHZ)
0 100 200 300 400 500 600
C
OSC
VALUE (pF)
1735 F02
100.0
87.5
75.0
62.5
50.0
37.5
25.0
12.5
0
When synchronized to an external clock, Burst Mode
operation is disabled but the inductor current is not
allowed to reverse. The 25% minimum inductor current
clamp present in Burst Mode operation is removed,
providing constant frequency discontinuous operation
over the widest possible output current range. In this
mode the synchronous MOSFET is forced on once every
10 clock cycles to recharge the bootstrap capacitor. This
minimizes audible noise while maintaining reasonably
high efficiency.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use Kool Mµ is a registered trademark of Magnetics, Inc.
13
LTC1735
1735fc
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1735: An N-channel MOSFET for the top
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak gate drive levels are set by the INTV
CC
voltage. This voltage is typically 5.2V during start-up (see
EXTV
CC
pin connection). Consequently, logic-level thresh-
old MOSFETs must be used in most LTC1735 applica-
tions. The only exception is when low input voltage is
expected (V
IN
< 5V); then, sub-logic level threshold
MOSFETs (V
GS(TH)
< 3V) should be used. Pay close
attention to the BV
DSS
specification for the MOSFETs as
well; many of the logic level MOSFETs are limited to 30V
or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage and maximum output current. When the
LTC1735 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Main SwitchDuty Cycle V
V
OUT
IN
=
Synchronous SwitchDuty Cycle VV
V
IN OUT
IN
=–
APPLICATIO S I FOR ATIO
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The MOSFET power dissipations at maximum output
current are given by:
PV
VIR
kV I C f
MAIN OUT
IN MAX DS ON
IN MAX RSS
=
()
+
()
+
()( )( )()
2
2
1
δ
()
PVV
VIR
SYNC IN OUT
IN MAX DS ON
=
()
+
()
–
()
2
1
δ
where δ is the temperature dependency of R
DS(ON)
and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I
2
R losses while the topside
N-channel equation includes an additional term for transi-
tion losses, which are highest at high input voltages. For
V
IN
< 20V the high current efficiency generally improves
with larger MOSFETs, while for V
IN
> 20V the transition
losses rapidly increase to the point that the use of a higher
R
DS(ON)
device with lower C
RSS
actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short-circuit when the
duty cycle in this switch is nearly 100%.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs Temperature curve, but
δ␣ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
RSS
is usually specified in the
MOSFET characteristics. The constant k = 1.7 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts during the
dead-time between the conduction of the two power MOSFETs.
This prevents the body diode of the bottom MOSFET from
turning on and storing charge during the dead-time, which
could cost as much as 1% in efficiency. A 3A Schottky is
generally a good size for 10A to 12A regulators due to the
relatively small average current. Larger diodes can result in
additional transition losses due to their larger junction capaci-
tance. The diode may be omitted if the efficiency loss can be
tolerated.
14
LTC1735
1735fc
C
IN
Selection
In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:
II V
V
V
V
RMS O MAX OUT
IN
IN
OUT
≅
()
/
–1
12
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
␣=␣I
O(MAX)
/2. This simple worst case condition is com-
monly used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours of
life. This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult the
manufacturer if there is any question.
C
OUT
Selection
The selection of COUT is primarily determined by the
effective series resistance (ESR) to minimize voltage
ripple. The output ripple (∆VOUT) in continuous mode is
determined by:
∆∆V I ESR fC
OUT L OUT
≈+
1
8
Where f = operating frequency, C
OUT
= output capaci-
tance and ∆I
L
= ripple current in the inductor. The output
ripple is highest at maximum input voltage since ∆I
L
increases with input voltage. Typically, once the ESR
requirement for C
OUT
has been met, the RMS current
rating generally far exceeds the I
RIPPLE(P–P)
requirement.
With ∆I
L
= 0.3I
OUT(MAX)
and allowing 2/3 of the ripple due
to ESR the output ripple will be less than 50mV at max V
IN
assuming:
C
OUT
required ESR < 2.2 R
SENSE
C
OUT
> 1/(8fR
SENSE
)
APPLICATIO S I FOR ATIO
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The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The I
TH
pin OPTI-LOOP compensation compo-
nents can be optimized to provide stable, high perfor-
mance transient response regardless of the output capaci-
tors selected.
The selection of output capacitors for CPU or other appli-
cations with large load current transients is primarily
determined by the voltage tolerance specifications of the
load. The resistive component of the capacitor, ESR,
multiplied by the load current change plus any output
voltage ripple must be within the voltage tolerance of the
load (CPU).
The required ESR due to a load current step is:
R
ESR
< ∆V/∆I
where ∆I is the change in current from full load to zero load
(or minimum load) and ∆V is the allowed voltage deviation
(not including any droop due to finite capacitance).
The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
must be sufficient to absorb the change in inductor current
when a high current to low current transition occurs. The
opposite load current transition is generally determined by
the control loop OPTI-LOOP components, so make sure
not to over compensate and slow down the response. The
minimum capacitance to assure the inductors’ energy is
adequately absorbed is:
CLI
VV
OUT OUT
>()
()
∆
∆
2
2
where ∆I is the change in load current.
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor electrolyte
15
LTC1735
1735fc
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications, ESR, RMS current han-
dling and load step specifications may require multiple
capacitors in parallel. Aluminum electrolytic, dry tantalum
and special polymer capacitors are available in surface
mount packages. Special polymer surface mount capaci-
tors offer very low ESR but have much lower capacitive
density per unit volume than other capacitor types. These
capacitors offer a very cost-effective output capacitor
solution and are an ideal choice when combined with a
controller having high loop bandwidth. Tantalum capaci-
tors offer the highest capacitance density and are often
used as output capacitors for switching regulators having
controlled soft-start. Several excellent surge-tested choices
are the AVX TPS, AVX TPSV or the KEMET T510 series of
surface mount tantalums, available in case heights rang-
ing from 1.5mm to 4.1mm. Aluminum electrolytic capaci-
tors can be used in cost-driven applications, provided that
consideration is given to ripple current ratings, tempera-
ture and long-term reliability. A typical application will
require several to many aluminum electrolytic capacitors
in parallel. A combination of the above mentioned capaci-
tors will often result in maximizing performance and
minimizing overall cost. Other capacitor types include
Nichicon PL series, NEC Neocap, Panasonic SP and
Sprague 595D series. Consult manufacturers for other
specific recommendations.
Like all components, capacitors are not ideal. Each ca-
pacitor has its own benefits and limitations. Combina-
tions of different capacitor types have proven to be a very
cost effective solution. Remember also to include high
frequency decoupling capacitors. They should be placed
as close as possible to the power pins of the load. Any
inductance present in the circuit board traces negates
their usefulness.
INTV
CC
Regulator
An internal P-channel low dropout regulator produces the
5.2V supply that powers the drivers and internal circuitry
within the LTC1735. The INTV
CC
pin can supply a maxi-
mum RMS current of 50mA and must be bypassed to
ground with a minimum of 4.7µF tantalum, 10µF special
polymer or low ESR type electrolytic capacitor. A 1µF
ceramic capacitor placed directly adjacent to the INTV
CC
and PGND IC pins is highly recommended. Good bypass-
ing is required to supply the high transient currents
required by the MOSFET gate drivers.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1735 to be
exceeded. The system supply current is normally domi-
nated by the gate charge current. Additional loading of
INTV
CC
also needs to be taken into account for the power
dissipation calculations. The total INTV
CC
current can be
supplied by either the 5.2V internal linear regulator or by
the EXTV
CC
input pin. When the voltage applied to the
EXTV
CC
pin is less than 4.7V, all of the INTV
CC
current is
supplied by the internal 5.2V linear regulator. Power
dissipation for the IC in this case is highest: (V
IN
)(I
INTVCC
)
and overall efficiency is lowered. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction tempera-
ture can be estimated by using the equations given in
Note␣ 2 of the Electrical Characteristics. For example, the
LTC1735CS is limited to less than 17mA from a 30V
supply when not using the EXTV
CC
pin as follows:
T
J
= 70°C + (17mA)(30V)(110°C/W) = 126°C
Use of the EXTV
CC
input pin reduces the junction tempera-
ture to:
T
J
= 70°C + (17mA)(5V)(110°C/W) = 79°C
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked
operating in continuous mode at maximum V
IN
.
EXTV
CC
Connection
The LTC1735 contains an internal P-channel MOSFET
switch connected between the EXTV
CC
and INTV
CC
pins.
Whenever the EXTV
CC
pin is above 4.7V, the internal 5.2V
regulator shuts off, the switch closes and INTV
CC
power is
supplied via EXTV
CC
until EXTV
CC
drops below 4.5V. This
allows the MOSFET gate drive and control power to be
APPLICATIO S I FOR ATIO
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16
LTC1735
1735fc
APPLICATIO S I FOR ATIO
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derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up, short circuit) power is supplied from the internal
regulator. Do not apply greater than 7V to the EXTV
CC
pin
and ensure that EXTV
CC
≤ V
IN
.
Significant efficiency gains can be realized by powering
INTV
CC
from the output, since the V
IN
current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
simply means connecting the EXTV
CC
pin directly to V
OUT
.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTV
CC
power
from the output.
The following list summarizes the four possible connec-
tions for EXTV
CC:
1. EXTV
CC
left open (or grounded). This will cause INTV
CC
to be powered from the internal 5.2V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.
2. EXTV
CC
connected directly to V
OUT
. This is the normal
connection for a 5V output regulator and provides the
highest efficiency. For output voltages higher than 5V,
EXTV
CC
is required to connect to V
OUT
so the SENSE pins’
absolute maximum ratings are not exceeded.
3. EXTV
CC
connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency gains
can still be realized by connecting EXTV
CC
to an output-
derived voltage that has been boosted to greater than
4.7V. This can be done with either the inductive boost
winding as shown in Figure 3a or the capacitive charge
pump shown in Figure 3b. The charge pump has the
advantage of simple magnetics.
4. EXTV
CC
connected to an external supply. If an external
supply is available in the 5V to 7V range (EXTV
CC
≤ V
IN
),
such as notebook main 5V system power, it may be used
to power EXTV
CC
providing it is compatible with the
MOSFET gate drive requirements. This is the typical case
as the 5V power is almost always present and is derived by
another high efficiency regulator.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following formula:
VV
R
R
OUT
=+
08 1 2
1
.
The resistive divider is connected to the output as shown
in Figure 4 allowing remote voltage sensing.
Figure 3a. Secondary Output Loop and EXTVCC Connection
Figure 3b. Capacitive Charge Pump for EXTVCC
EXTV
CC
FCB
SGND
V
IN
TG
SW
BG
PGND
LTC1735
R
SENSE
V
OUT
V
SEC
6.8V
+
C
OUT
+
1µF
1735 F03a
N-CH
N-CH
R4
+
C
IN
V
IN
L1
1:N
1N4148
OPTIONAL EXTV
CC
CONNECTION
5V ≤ V
SEC
≤ 7V
R3
EXTVCC
VIN
TG
SW
BG
PGND
LTC1735
RSENSE VOUT
VN2222LL
+COUT
1735 F03b
N-CH
N-CH
+
CIN
+1µF
VIN
L1
BAT85 BAT85
BAT85
0.22µF
17
LTC1735
1735fc
Topside MOSFET Driver Supply (C
B
, D
B
)
An external bootstrap capacitor CB connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. Note that the voltage across CB is about a diode
drop below INTVCC. When the topside MOSFET is to be
turned on, the driver places the CB voltage across the
gate-source of the MOSFET. This enhances the MOSFET
and turns on the topside switch. The switch node voltage
SW rises to VIN and the BOOST pin rises to VIN + INTVCC.
The value of the boost capacitor CB needs to be 100 times
greater than the total input capacitance of the topside
MOSFET. In most applications 0.1µF to 0.33µF is ad-
equate. The reverse breakdown on DB must be greater
than VIN(MAX).
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.
SENSE
+
/SENSE
–
Pins
The common mode input range of the current comparator
is from 0V to 1.1(INTV
CC
). Continuous linear operation in
step-down applications is guaranteed throughout this
range allowing output voltages anywhere from 0.8V to 7V.
A differential NPN input stage is used and is biased with
internal resistors from an internal 2.4V source as shown
in the Functional Diagram. This causes current to either be
sourced or sunk by the sense pins depending on the
output voltage. If the output voltage is below 2.4V current
will flow out of both sense pins to the main output. This
forces a minimum load current that can be fulfilled by the
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Figure 4. Setting the LTC1735 Output Voltage
V
OSENSE
SGND
V
OUT
R2
1735 F04
LTC1735 R1
47pF
V
OUT
resistive divider. The maximum current flowing out
of the sense pins is:
I
SENSE+
+ I
SENSE–
= (2.4V – V
OUT
)/24k
Since V
OSENSE
is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 4 to have a maximum value to
absorb this current:
Rk
V
VV
MAX OUT
124
08
24
()
.
.–
=
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that at output voltages above
2.4V no maximum value of R1 is necessary to absorb the
sense pin currents; however, R1 is still bounded by the
V
OSENSE
feedback current.
Soft-Start/Run Function
The RUN/SS pin is a multipurpose pin that provides a soft-
start function and a means to shut down the LTC1735.
Soft-start reduces surge currents from V
IN
by gradually
increasing the controller’s current limit I
TH(MAX)
. This pin
can also be used for power supply sequencing.
Pulling the RUN/SS pin below 1.5V puts the LTC1735 into
shutdown. This pin can be driven directly from logic as
shown in Figure 5. The V
IN
quiescent current is a function
of RUN/SS voltage (refer to Typical Performance Charac-
teristics graphs on page 6). Releasing the RUN/SS pin
allows an internal 1.2µA current source to charge up the
external soft-start capacitor C
SS.
If RUN/SS has been
pulled all the way to ground there is a delay before starting
of approximately:
tV
ACsFC
DELAY SS SS
=µ=µ
()
15
12 125
.
../
When the voltage on RUN/SS reaches 1.5V the LTC1735
begins operating with a current limit at approximately
25mV/R
SENSE
. As the voltage on the RUN/SS pin increases
from 1.5V to 3.0V, the internal current limit is increased
from 25mV/R
SENSE
to 75mV/R
SENSE
. The output current
limit ramps up slowly, taking an additional 1.25s/µF to
reach full current. The output current thus ramps up
slowly, reducing the starting surge current required from
the input power supply.
18
LTC1735
1735fc
Diode D1 in Figure 5 reduces the start delay while allowing
C
SS
to charge up slowly for the soft-start function. This
diode and C
SS
can be deleted if soft-start is not needed.
The RUN/SS pin has an internal 6V zener clamp (See
Functional Diagram).
capacitor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from V
IN
as in
Figure␣ 6a, current latchoff is always defeated. A diode
connecting this pull-up resistor to INTV
CC
, as in Figure␣ 6b,
eliminates any extra supply current during controller shut-
down while eliminating the INTV
CC
loading from prevent-
ing controller start-up. If the voltage on C
SS
does not
exceed 4.1V, the overcurrent latch is not armed and the
function is disabled.
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off. Defeating this feature will easily allow trouble-
shooting of the circuit and PC layout. The internal short-
circuit and foldback current limiting still remains active,
thereby protecting the power supply system from failure.
After the design is complete, a decision can be made
whether to enable the latchoff feature.
The value of the soft-start capacitor C
SS
will need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS
> (C
OUT
)(V
OUT
)(10
–4
)(R
SENSE
)
The minimum recommended soft-start capacitor of
C
SS
␣=␣0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The LTC1735 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/R
SENSE
.
The LTC1735 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is defeated. If the output
falls by more than half, then the maximum sense voltage
is progressively lowered from 75mV to 30mV. Under
short-circuit conditions with very low duty cycle, the
LTC1735 will begin cycle skipping in order to limit the
short-circuit current. In this situation the bottom MOSFET
will be conducting the peak current. The short-circuit
ripple current is determined by the minimum on-time
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Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
Figure 5. RUN/SS Pin Interfacing
3.3V OR 5V RUN/SS RUN/SS
D1
C
SS
C
SS
1735 F05
3.3V OR 5V RUN/SS
V
IN
INTV
CC
RUN/SS
D1
D1
C
SS
R
SS
C
SS
R
SS
1735 F06
(a) (b)
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to shut off the
controller and latch off when an overcurrent condition is
detected. The RUN/SS capacitor, C
SS
,
is used initially to
turn on and limit the inrush current of the controller. After
the controller has been started and given adequate time to
charge up the output capacitor and provide full load
current, C
SS
is used as a short-circuit timer. If the output
voltage falls to less than 70% of its nominal output voltage
after C
SS
reaches 4.1V
, the assumption is made that the
output is in a severe overcurrent and/or short-circuit
condition, so C
SS
begins discharging. If the condition lasts
for a long enough period as determined by the size of C
SS
,
the controller will be shut down until the RUN/SS pin
voltage is recycled.
This built-in latchoff can be overridden by providing a
current >5µA at a compliance of 5V to the RUN/SS pin as
shown in Figure␣ 6. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS
19
LTC1735
1735fc
t
ON(MIN)
of the LTC1735 (approximately 200ns), the input
voltage and inductor value:
∆I
L(SC)
= t
ON(MIN)
V
IN
/L
The resulting short-circuit current is:
ImV
RI
SC SENSE LSC
=+
30 1
2∆()
The current foldback function is always active and is not
effected by the current latchoff function.
Fault Conditions: Output Overvoltage Protection
(Crowbar)
The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the
regulator rises much higher than nominal levels. This
condition causes huge currents to flow, much greater than
in normal operation. This feature is designed to protect
against a shorted top MOSFET; it does not protect against
a failure of the controller itself.
The comparator (OV in the Functional Diagram) detects
overvoltage faults greater than 7.5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the 0V condition persists; if V
OUT
returns to a safe
level, normal operation automatically resumes.
Note that dynamically changing the output voltage may
cause overvoltage protection to be momentarily activated
during programmed output voltage decreases. This will
not cause permanent latchoff nor will it disrupt the desired
voltage change. With soft-latch overvoltage protection,
dynamically changing the output voltage is allowed and
the overvoltage protection tracks the newly programmed
output voltage, always protecting the load.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC1735 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit and care should be taken to ensure that:
tV
Vf
ON MIN OUT
IN
() ()
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1735 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and voltage will increase.
The minimum on-time for the LTC1735 in a properly
configured application is generally less than 200ns. How-
ever, as the peak sense voltage decreases, the minimum
on-time gradually increases as shown in Figure 7. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
to provide sufficient ripple amplitude to meet the mini-
mum on-time requirement.
As a general rule, keep the
inductor ripple current equal or greater than 30% of
I
OUT(MAX)
at V
IN(MAX)
.
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∆I
L
/I
OUT(MAX)
(%)
0
MINIMUM ON-TIME (ns)
100
150
40
1735 F07
50
010 20 30
250
200
Figure 7. Minimum On-Time vs ∆I
L
20
LTC1735
1735fc
FCB Pin Operation
When the FCB pin drops below its 0.8V threshold, continu-
ous mode operation is forced. In this case, the top and
bottom MOSFETs continue to be driven synchronously
regardless of the load on the main output. Burst Mode
operation is disabled and current reversal is allowed in the
inductor.
In addition to providing a logic input to force continuous
synchronous operation and external synchronization, the
FCB pin provides a means to regulate a flyback winding
output (refer to Figure 3a). During continuous mode,
current flows continuously in the transformer primary.
The secondary winding(s) draw current only when the
bottom, synchronous switch is on. When primary load
currents are low and/or the V
IN
/V
OUT
ratio is low, the
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings provided there is sufficient synchro-
nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.
The secondary output voltage V
SEC
is normally set as
shown in Figure␣ 3a by the turns ratio N of the transformer:
V
SEC
≅ (N + 1)V
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
SEC
will droop. An external resistive divider from
V
SEC
to the FCB pin sets a minimum voltage V
SEC(MIN)
:
VV
R
R
SEC MIN()
.≈+
08 1 4
3
If V
SEC
drops below this level, the FCB voltage forces
continuous switching operation until V
SEC
is again above
its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.17µA
internal current source pulling the pin high. Remember to
include this current when choosing resistor values R3
and R4.
The internal LTC1735 oscillator can be synchronized to an
external oscillator by applying and clocking the FCB pin
with a signal above 1.5V
P–P
. When synchronized to an
external frequency, Burst Mode operation is disabled but
cycle skipping is allowed at low load currents since current
reversal is inhibited. The bottom gate will come on every
10 clock cycles to assure the bootstrap cap is kept re-
freshed. The rising edge of an external clock applied to the
FCB pin starts a new cycle. The FCB pin must not be driven
when the device is in shutdown (RUN/SS pin low).
The range of synchronization is from 0.9f
O
to 1.3f
O
, with
f
O
set by C
OSC
. Attempting to synchronize to a higher
frequency than 1.3f
O
can result in inadequate slope com-
pensation and cause loop instability with high duty cycles
(duty cycle > 50%). If loop instability is observed while
synchronized, additional slope compensation can be ob-
tained by simply decreasing C
OSC
.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 1
FCB Pin Condition
DC Voltage: 0V to 0.7V Burst Disabled/Forced Continuous
Current Reversal Enabled
DC Voltage: ≥ 0.9V Burst Mode Operation,
No Current Reversal
Feedback Resistors Regulating a Secondary Winding
Ext Clock: (0V to V
FCBSYNC
) Burst Mode Operation Disabled
(V
FCBSYNC
> 1.5V) No Current Reversal
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
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21
LTC1735
1735fc
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC1735 circuits: 1) V
IN
current, 2)␣ INTV
CC
current, 3) I
2
R losses, 4) Topside MOSFET transition
losses.
1) The V
IN
current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small (<0.1%)
loss that increases with V
IN
.
2) INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
CC
to
ground. The resulting dQ/dt is a current out of INTV
CC
that
is typically much larger than the control circuit current. In
continuous mode, I
GATECHG
= f(Q
T
+Q
B
), where Q
T
and Q
B
are the gate charges of the topside and bottom-side
MOSFETs.
Supplying INTV
CC
power through the EXTV
CC
switch input
from an output-derived or other high efficiency source will
scale the V
IN
current required for the driver and control
circuits by a factor of (Duty Cycle)/(Efficiency). For ex-
ample, in a 20V to 5V application, 10mA of INTV
CC
current
results in approximately 3mA of V
IN
current. This reduces
the mid-current loss from 10% or more (if the driver was
powered directly from V
IN
) to only a few percent.
3) I
2
R losses are predicted from the DC resistances of the
MOSFET, inductor and current shunt. In continuous mode
the average output current flows through L and R
SENSE
,
but is “chopped” between the topside main MOSFET and
the synchronous MOSFET. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance of
one MOSFET can simply be summed with the resistances
of L and R
SENSE
to obtain I
2
R losses. For example, if each
R
DS(ON)
= 0.03Ω, R
L
= 0.05Ω and R
SENSE
= 0.01Ω, then
the total resistance is 0.09Ω. This results in losses ranging
from 2% to 9% as the output current increases from 1A to
5A for a 5V output, or a 3% to 14% loss for a 3.3V output.
Effeciency varies as the inverse square of V
OUT
for the
same external components and output power level. I
2
R
losses cause the efficiency to drop at high output currents.
4) Transition losses apply only to the topside MOSFET(s)
and only become significant when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) V
IN2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and fuse resis-
tance losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a maxi-
mum of 0.01Ω to 0.02Ω of ESR. Other losses including
Schottky conduction losses during dead-time and induc-
tor core losses generally account for less than 2% total
additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, V
OUT
shifts by an amount equal
to ∆I
LOAD
(ESR), where ESR is the effective series resis-
tance of C
OUT
. ∆I
LOAD
also begins to charge or discharge
C
OUT
, generating the feedback error signal that forces the
regulator to adapt to the current change and return V
OUT
to its steady-state value. During this recovery time V
OUT
can be monitored for excessive overshoot or ringing,
which would indicate a stability problem. OPTI-LOOP
compensation allows the transient response to be opti-
mized over a wide range of output capacitance and ESR
values. The availability of the I
TH
pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
TH
external components shown in the Figure␣ 1 circuit will
provide an adequate starting point for most applications.
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22
LTC1735
1735fc
The I
TH
series R
C
–C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1µs
to 10µs will produce output voltage and I
TH
pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
may not be within the bandwidth of the feedback loop, so
the standard second-order overshoot/DC ratio cannot be
used to determine phase margin. The gain of the loop will
be increased by increasing R
C
and the bandwidth of the
loop will be increased by decreasing C
C
. If R
C
is increased
by the same factor that C
C
is decreased, the zero frequency
will be kept the same, thereby keeping the phase the same
in the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica-
tion Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately (25)(C
LOAD
). Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current to
about 200mA.
Improve Transient Response and Reduce Output
Capacitance with Active Voltage Positioning
Fast load transient response, limited board space and low
cost are requirements of microprocessor power supplies.
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Active voltage positioning improves transient response
and reduces the output capacitance required to power a
microprocessor where a typical load step can be from 0.2A
to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the
microprocessor must be held to about ±0.1V of nominal
in spite of these load current steps. Since the control loop
cannot respond this fast, the output capacitors must
supply the load current until the control loop can respond.
Capacitor ESR and ESL primarily determine the amount of
droop or overshoot in the output voltage. Normally, sev-
eral capacitors in parallel are required to meet micropro-
cessor transient requirements.
Active voltage positioning is a form of deregulation. It sets
the output voltage high for light loads and low for heavy
loads. When load current suddenly increases, the output
voltage starts from a level higher than nominal so the
output voltage can droop more and stay within the speci-
fied voltage range. When load current suddenly decreases
the output voltage starts at a level lower than nominal so
the output voltage can have more overshoot and stay
within the specified voltage range. Less output capaci-
tance is required when voltage positioning is used be-
cause more voltage variation is allowed on the output
capacitors.
Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1735 and two resistors
connected to the I
TH
pin. An input voltage offset is intro-
duced when the error amplifier has to drive a resistive load.
This offset is limited to ±30mV at the input of the error
amplifier. The resulting change in output voltage is the
product of input offset and the feedback voltage divider
ratio.
Figure 8 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R4 force the input
voltage offset that adjusts the output voltage according to
the load current level. To select values for R1 and R4, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary ±0.112V. The LTC1735 reference accu-
racy is ±1%. Using 1% tolerance resistors, the total
feedback divider accuracy is about 1% because both
feedback resistors are close to the same value. The result-
ing setpoint accuracy is ±2% so the output transient
23
LTC1735
1735fc
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16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
U1
LTC1735
C2
0.1µF
C8
0.22µF
C4
100pF
C5
47pF
C3
100pF
R2
100k
R1
27k
R5
0.003Ω
GND
V
OUT
1.5V
15A
V
IN
7.5V TO
24V
GND
C6
1000pF
C1
39pF
+
C10
4.7µF
10V
C9
1µF
5V (OPTIONAL)
C11
330pF C19
1µF
+
C15 TO
C18
180µF
4V
C7
0.1µF
M1
FDS6680A
M2, M3
FDS6680A
×2
C9, C19: TAIYO YUDEN JMK107BJ105
C10: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C18: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
M1 TO M3: FAIRCHILD FDS6680A
R5: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1735CS
1735 F08
D1
CMDSH-3
R6
10k
R7
11.5k
D2
MBRS340
C12 TO C14
10µF
35V
L1
1µH
R4
100k
R3
680k
Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning
voltage cannot exceed ±0.082V. At V
OUT
= 1.5V, the
maximum output voltage change controlled by the I
TH
pin
would be:
∆=
=±=±
VInput Offset V
V
V
VmV
OSENSE OUT
REF
•
.•.
.
003 15
08 56
With the optimum resistor values at the I
TH
pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position-
ing provides an additional ±56mV to the allowable tran-
sient voltage on the output capacitors, a 68% improve-
ment over the ±82mV allowed without active voltage
positioning.
The next step is to calculate the scale factor for V
ITH
, the
I
TH
pin voltage. The V
ITH
scale factor reflects the I
TH
pin
voltage required for a given load current. V
ITH
controls the
peak sense resistor voltage, which represents the DC
output current plus one half of the peak-to-peak inductor
current. The no load to full load V
ITH
range is from 0.3V to
2.4V, which controls the sense resistor voltage from 0V to
the ∆V
SENSE(MAX)
voltage of 75mV. The calculated V
ITH
scale factor with a 0.003Ω sense resistor is:
V ScaleFactor V Range Sense sistor Value
V
VV
VVA
ITH ITH
SENSE MAX
=∆
==
•Re
(. – . )• .
../
()
24 03 0003
0 075 0 084
V
ITH
at any load current is:
VI IV ScaleFactor
V Offset
ITH OUTDC LITH
ITH
=+
∆
+
2•
24
LTC1735
1735fc
At full load current:
VA
AVA V
V
ITH MAX PP
()
•. / .
.
=+
+
=
−
15 5
20 084 0 3
177
At minimum load current:
VA
AVA V
V
ITH MIN PP
()
.•./.
.
=+
+
=
−
02 2
20 084 0 3
040
In this circuit, V
ITH
changes from 0.40V at light load to
1.77V at full load, a 1.37V change. Notice that ∆I
L
, the
peak-to-peak inductor current, changes from light load to
full load. Increasing the DC inductor current decreases the
permeability of the inductor core material, which de-
creases the inductance and increases ∆I
L
. The amount of
inductance change is a function of the inductor design.
To create the ±30mV input offset, the gain of the error
amplifier must be limited. The desired gain is:
AV
Input OffsetError
V
V
VITH
=∆==
137
2003 22 8
.
(. ) .
Connecting a resistor to the output of the transconductance
error amplifier will limit the voltage gain. The value of this
resistor is:
RA
Error Amplifier g mS k
ITH V
m
===
22 8
13 17 54
.
..
To center the output voltage variation, V
ITH
must be
centered so that no I
TH
pin current flows when the output
voltage is nominal. V
ITH(NOM)
is the average voltage be-
tween V
ITH
at maximum output current and minimum
output current:
VVVV
VVVV
ITH NOM ITH MAX ITH MIN ITH MIN() () () ()
–
.–. ..
=+
=+=
2
177 040
20 40 1 085
APPLICATIO S I FOR ATIO
WUUU
The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R4 that sources
current into the I
TH
pin and resistor R1 that sinks current
to SGND.
To calculate the resistor values, first determine the ratio
between them:
kVV
V
VV
V
INTVCC ITH NOM
ITH NOM
===
–.–.
..
()
()
52 1085
1 085 379
V
INTVCC
is equal to V
EXTVCC
or 5.2V if EXTV
CC
is not used.
Resistor R4 is:
Rk R k
ITH
4 1 3 79 1 17 54 84 0=+ = + =()• (. )•. .
Resistor R1 is:
RkR
k
kk
ITH
11 3 79 1 17 54
379 22 17=+=+=
()• (. )•.
..
Unfortunately, PCB noise can add to the voltage developed
across the sense resistor, R5, causing the I
TH
pin voltage
to be slightly higher than calculated for a given output
current. The amount of noise is proportional to the output
current level. This PCB noise does not present a serious
problem but it does change the effective value of R5 so the
calculated values of R1 and R4 may need to be adjusted to
achieve the required results. Since PCB noise is a function
of the layout, it will be the same on all boards with the same
layout.
Figures 9 and 10 show the transient response before and
after active voltage positioning is implemented. Notice
that active voltage positioning reduced the transient re-
sponse from almost 200mV
P-P
to a little over 100mV
P-P
.
Refer to Design Solutions 10 for more information about
active voltage positioning.
25
LTC1735
1735fc
APPLICATIO S I FOR ATIO
WUUU
V
IN
= 12V
V
OUT
= 1.5V
1.5V
100mV/DIV
15A
0A
10A/DIV
OUTPUT
VOLTAGE
LOAD
CURRENT
50µs/DIV 1735 F09
Figure 9. Normal Transient Response (Without R1, R4)
V
IN
= 12V
V
OUT
= 1.5V
1.582V
1.5V
1.418V
100mV/DIV
15A
0A
10A/DIV
50µs/DIV 1735 F10
Figure 10. Transient Response with Active Voltage Positioning
OUTPUT
VOLTAGE
LOAD
CURRENT Figure 11. Plugging into the Cigarette Lighter
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging
into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure␣ 11 is the most straight
forward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1735 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET BV
DSS
.
VIN
50A IPK RATING
1735 F11
LTC1735
12V
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
Design Example
As a design example, assume V
IN
= 12V(nominal),
V
IN
= 22V(max), V
OUT
= 1.8V, I
MAX
= 5A and f = 300kHz.
R
SENSE
and C
OSC
can immediately be calculated:
R
SENSE
= 50mV/5A = 0.01Ω
C
OSC
= 1.61(10
7
)/(300kHz) – 11pF = 43pF
Assume a 3.3µH inductor and check the actual value of the
ripple current. The following equation is used:
∆IV
fL
V
V
LOUT OUT
IN
=
()() –1
The highest value of the ripple current occurs at the
maximum input voltage:
∆IV
kHz H
V
VA
L
=µ
=
18
300 3 3 118
22 17
.
(. ) –..
The maximum ripple current is 33% of maximum output
current, which is about right.
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
26
LTC1735
1735fc
APPLICATIO S I FOR ATIO
WUUU
Next verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum V
IN
:
tV
Vf
V
V kHz ns
ON MIN OUT
IN MAX
() ()
.
()
== =
18
22 300 273
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the sense pin current.
Rk
V
VV
kV
VV k
MAX OUT
124
08
24
24 08
24 18 32
()
.
.–
.
.–.
=
=
=
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412ADY results
in R
DS(ON)
= 0.035Ω, C
RSS
= 100pF. At maximum input
voltage with T(estimated) = 50°C:
PV
VCC
V A pF kHz
mW
MAIN =
()
+°°
[]
Ω
()
+
()()( )( )
=
18
22 5 1 0 005 50 25 0 035
1 7 22 5 100 300
204
2
2
.( . )( – ) .
.
Because the duty cycle of the bottom MOSFET is much
greater than the top, a larger MOSFET, Siliconix Si4410DY,
(R
DS(ON)
= 0.02Ω) is chosen. The power dissipation in the
bottom MOSFET, again assuming T
A
= 50°C, is:
PVV
VA
mW
SYNC =
()()
Ω
()
=
22 1 8
22 511002
505
2
–. ..
Thanks to current foldback, the bottom MOSFET dissipa-
tion in short-circuit will be less than under full load
conditions.
C
IN
is chosen for an RMS current rating of at least 2.5A at
temperature. C
OUT
is chosen with an ESR of 0.02Ω for low
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The worst-case
output voltage ripple due to ESR is approximately:
VRI AmV
ORIPPLE ESR L P P
==Ω=
−
(). (.)∆002 23 46
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735. These items are also illustrated graphically in
the layout diagram of Figure␣ 12. Check the following in
your layout:
1) Are the signal and power grounds segregated? The
LTC1735 PGND pin should tie to the ground plane close to
the input capacitor(s). The SGND pin should then connect
to PGND, and all components that connect to SGND
should make a single point tie to the SGND pin. The
synchronous MOSFET source pins should connect to the
input capacitor(s) ground.
2) Does the V
OSENSE
pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be connected
between the (+) plate of C
OUT
and signal ground. The 47pF
to 100pF capacitor should be as close as possible to the
LTC1735. Be careful locating the feedback resistors too far
away from the LTC1735. The V
OSENSE
line should not be
routed close to any other nodes with high slew rates.
3) Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE
+
and SENSE
–
should be as close as possible to the
LTC1735. Ensure accurate current sensing with Kelvin
connections as shown in Figure 13. Series resistance can
be added to the SENSE lines to increase noise rejection.
4) Does the (+) terminal of C
IN
connect to the drain of the
topside MOSFET(s) as closely as possible? This capacitor
provides the AC current to the MOSFET(s).
5) Is the INTV
CC
decoupling capacitor connected closely
between
INTV
CC
and the power ground pin? This capaci-
tor carries the MOSFET driver peak currents. An addi-
tional 1µF ceramic capacitor placed immediately next to
27
LTC1735
1735fc
APPLICATIO S I FOR ATIO
WUUU
Figure 12. LTC1735 Layout Diagram
Figure 13. Kelvin Sensing R
SENSE
the INTV
CC
and PGND pins can help improve noise
performance.
6) Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
LTC1735
C
SS
C
C2
C
C
R
C
47pF
1000pF
+
C
OUT
C
OSC
R1
R2
C
B
D
B
R
SENSE
D1
M2
+
4.7µF
M1
+
C
IN
+
–
L1
V
IN
–
+
V
OUT
1735 F12
SENSE
+
SENSE
–
HIGH CURRENT PATH
1735 F13
CURRENT SENSE
RESISTOR
(R
SENSE
)
feedback pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” (Pin 9 to Pin 16) of the LTC1735 and occupy
minimum PC trace area.
28
LTC1735
1735fc
TYPICAL APPLICATIO S
U
1.8V/5A Converter from Design Example with Burst Mode Operation Disabled
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
LTC1735
C
SS
0.1µFC
B
0.1µF
C
C2
220pF
47pF
C
C
470pF
R
C
33k
R
SENSE
0.01ΩV
OUT
1.8V
5A
1000pF
C
OSC
43pF
+
4.7µF
+
C
OUT
150µF
6.3V
×2
PANASONIC SP
C
IN
22µF
50V
CER
M1
Si4412DY
M2
Si4410DY
C
OUT
: PANASONIC EEFUEOG151R
C
IN
: MARCON THCR70LE1H226ZT
L1: PANASONIC ETQP6F3R3HFA
R
SENSE
: IRC LR 2010-01-R010F
1735 TA02
D
B
CMDSH-3
R2
32.4k
1%
R1
25.5k
1%
MBRS140T3
V
IN
4.5V TO 22V
L1
3.3µH
OPTIONAL:
CONNECT TO 5V
SGND
CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
LTC1735
C
SS
0.1µFC
B
0.22µF
C
C2
220pF
47pF
C
C
220pF
R
C
20k
100k*
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
R
SENSE
0.004ΩV
OUT
1.5V
12A
1000pF
C
OSC
39pF
+
4.7µF
1µF
100pF
+
+
C
OUT
180µF
4V
×3
C
O
47µF
10V
C
IN
150µF
6.3V
×2
M1
FDS6680A
M2, M3
FDS6680A
×2
C
OUT
: PANASONIC EEFUEOG181R
C
IN
: PANASONIC EEFUEOJ151R
C
O
: TAIYO YUDEN LMK550BJ476MM-B
L1: COILCRAFT 1705022P-781HC
R
SENSE
: IRC LRF 2512-01-R004-J
1735 TA03
D
B
MBR0530
R2
22.6k
1%
R1
25.5k
1%
MBRD835L
V
IN
5V
L1
0.78µH
V
IN
SGND
29
LTC1735
1735fc
TYPICAL APPLICATIO S
U
Selectable Output Voltage Converter with Burst Mode Operation Disabled for CPU Power
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
NC
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
PGOOD
SENSE
–
SENSE
+
NC
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
NC
LTC1735F
C
SS
0.1µFC
B
0.22µF
0.1µF4.7Ω
C
C2
47pF
47pF
C
C
330pF
R
C
33k
R
SENSE
0.004ΩV
OUT
1.35V/1.60V
12A
1000pF
C
OSC
43pF
+
4.7µF
1µF
CER
+
C
OUT
470µF
6.3V
×3
KEMET
ON: V
OUT
= 1.60V
OFF: V
OUT
= 1.35V
C
IN
: MARCON THCR70EIH226ZT
C
OUT
: KEMET T510X447M006AS
L1: PANASONIC ETQP6F1R2HFA
R
SENSE
: IRC LRF2512-01-R004F
M1
FDS6680A
M2
FDS6680A
×2
1735 TA05
C
IN
22µF
×2
CER
D
B
CMDSH-3 R2
10k
1%
R1
14.3k
1%
47pF
47pF
10k
MBRS340T3
V
IN
4.5V TO 24V
L1
1.2µH
OPTIONAL:
CONNECT TO 5V
NC
NCNC
POWER GOOD
R3
33.2k
1%
SGND
VN2222
10Ω
10Ω
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
LTC1735
C
SS
0.1µF
C
C2
100pF
C
C
2200pF R
C
3.3k
1M
V
OUT
10k
6.2V
FMMT625
R
SENSE
0.004Ω
22Ω
T1
V
IN
4V TO 40V
6
7
10
3
47Ω
R2
113k
1% C
OUT
220µF
16V
×4
V
OUT
12V
3A
R1
8.06k
1%
3300pF
47pF
C
OSC
150pF
+
4.7µF
0.1µF
C
IN
: MARCON THCR70EIH226ZT
C
OUT
: AVX TPSV227M016R0150
T1: COILTRONICS VP5-0155
R
SENSE
: IRC LRF2512-01-R004F
M1
IRL2910S M2
Si4850EY MBRS1100
1735 TA07
+
100Ω
1nF
100V
1nF
100V
•
•
C
IN
22µF
50V
×2
CMDSH-3
4V to 40V Input to 12V Flyback Converter
30
LTC1735
1735fc
Dual Output 15W 3.3V/5V Power Supply
TYPICAL APPLICATIO S
U
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
LTC1735
C
SS
0.1µFC
B
0.1µF
C
C2
220pF
100pF
C
C
470pF
R
C
33k
R
SENSE
0.012ΩV
OUT
5V
3.5A
V
OUT2
12V
120mA
UNREG
1000pF
C
OSC
51pF
+
4.7µF
+
C
OUT
100µF
10V
×3
AVX
+
C
SEC
22µF
35V
AVX
M1
Si4802DY
M2
Si4802DY
1735 TA04
+
C
IN
22µF
30V
OS-CON
D
B
CMDSH-3
R2
105k
1%
C
IN
: SANYO OS-CON 30SC22M
C
OUT
: AVX TPSD107M010R0068
T1: 1:8 DALE LPE6562-A262
R1
20k
1%
MBRS140T3
V
IN
5.5V TO 28V
T1
1:1.8
10µH
SGND
MBRS1100T3
22Ω1000pF
10k
100Ω
100Ω
140k
5V/3.5A Converter with 12V/200mA Auxiliary Output
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
–
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
LTC1735
C
SS
0.1µFC
B
0.1µF0.01µF
C
C2
100pF
100pF
C
C
470pF
R
C
33k R
SENSE
0.01ΩV
OUT1
3.3V
2.5A
1000pF
C
OSC
47pF
+
4.7µF
+
C
OUT1
100µF
10V
×2
C
OUT2
100µF
10V
×2
V
OUT2
5V
1.5A
M1
Si4412DY
M2
Si4412DY
M3
Si4412DY
1735 TA08
C
IN
22µF
50V
D
B
CMDSH-3
R2
62.6k
1%
C
IN
: MARCON THCR70EIH226ZT
C
OUT1, 2
: AVX TPSD107M010R0065
T1: BI TECHNOLOGIES HM00-93839
R
SENSE
: IRC LRF2512-01-R010 F
R1
20k
1%
MBRS140T3
CMDSH-3 MBRS140T3
V
IN
4.5V TO 28V
T1A T1B
T1C
4.7k
18
•
V
OUT2
27
•
36
•
SGND
+
31
LTC1735
1735fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
PACKAGE DESCRIPTION
U
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
F Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)
F20 TSSOP 0502
0.09 – 0.20
(.0036 – .0079)
0° – 8°
0.45 – 0.75
(.018 – .030)
4.30 – 4.50**
(.169 – .177)
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
6.40
BSC
134
5678910
111214 13
6.40 – 6.60*
(.252 – .260)
20 19 18 17 16 15
2
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05 0.65 TYP
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
GN16 (SSOP) 0502
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 TYP.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0° – 8° TYP
.008 – .010
(0.203 – 0.254)
1
N
2345678
N/2
.150 – .157
(3.810 – 3.988)
NOTE 3
16 15 14 13
.386 – .394
(9.804 – 10.008)
NOTE 3
.228 – .244
(5.791 – 6.197)
12 11 10 9
S16 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
.245
MIN
N
123 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
32
LTC1735
1735fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPOR ATION 1998
LT/TP 0104 REV C 1K • PRINTED IN USA
TYPICAL APPLICATIO
U
3.3V to 2.5V/5A Converter with External Clock Synchronization Operating at 500kHz
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
COSC
RUN/SS
ITH
FCB
SGND
VOSENSE
SENSE–
SENSE+
TG
BOOST
SW
VIN
INTVCC
BG
PGND
EXTVCC
LTC1735
CSS
0.1µFCB
0.1µF
0.1µF
CC2
51pF
47pF
CC
330pF
RC
33k RSENSE
0.01ΩVOUT
2.5V
5A
1000pF
COSC
20pF
+
4.7µF
+
COUT
100µF
10V
AVX
×3
M1
Si4410DY
M2
Si4410DY
47pF
1735 TA06
+
CIN
100µF
10V
OS-CON
DB
CMDSH-3
R2
43.2k
1%
CIN: SANYO OS-CON 10SL100M
COUT: AVX TPSD107M010R0065
L1: COILCRAFT DO3316P-152
RSENSE: IRC LR2010-01-R010-F
R1
20k
1%
MBRS140T3
VIN
3.3V
5V
L1
1.5µH
SGND
EXT
CLOCK
500kHz
PART NUMBER DESCRIPTION COMMENTS
LTC1530 High Power Step-Down Synchronous DC/DC Controller High Efficiency 5V to 3.3V Conversion at Up to 15A
in SO-8
LTC1628/LTC3728 2-Phase, Dual Output Synchronous Step-Down Reduces C
IN
and C
OUT
, Power Good Output Signal, Synchronizable,
DC/DC Controllers 3.5V ≤ V
IN
≤ 36V, I
OUT
up to 20A, 0.8V ≤ V
OUT
≤ 5V
LTC1629/LTC3729 20A to 200A PolyPhase Synchronous Controllers Expandable from 2-Phase to 12-Phase, Uses All
Surface Mount Components, No Heat Sink, V
IN
up to 36V
LTC1702 No R
SENSE
TM 2-Phase Dual Synchronous Step-Down 550kHz, No Sense Resistor
Controller
LTC1708-PG 2-Phase, Dual Synchronous Controller with Mobile VID 3.5V ≤ V
IN
≤ 36V, VID Sets V
OUT1
, PGOOD
LTC1736 High Efficiency Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,
VID Control 3.5V ≤ V
IN
≤ 36V
LTC1778 No R
SENSE
Current Mode Synchronous Step-Down Up to 97% Efficiency, 4V ≤ V
IN
≤ 36V, 0.8V ≤ V
OUT
≤ (0.9)(V
IN
),
Controller I
OUT
up to 20A
LTC1929/ 2-Phase Synchronous Controllers Up to 42A, Uses All Surface Mount Components,
LTC1929-PG No Heat Sinks, 3.5V ≤ V
IN
≤ 36V
LTC3711 No R
SENSE
Current Mode Synchronous Step-Down Up to 97% Efficiency, Ideal for Pentium® III Processors,
Controller with Digital 5-Bit Interface 0.925V ≤ V
OUT
≤ 2V, 4V ≤ V
IN
≤ 36V, I
OUT
up to 20A
LTC3729 20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount
Components, V
IN
up to 36V
LTC3730 IMVP III 3-Phase Synchronous Controller I
OUT
Up to 60A, 0.6V ≤ V
OUT
≤ 1.75V, Integrated MOSFET Drivers
LTC3732 VRM 9.0/9.1 3-Phase DC/DC Synchronous Step-Down 1.1V ≤ V
OUT
≤ 1.85V, 4.5V ≤ V
IN
≤ 32V, SSOP-36
Controller
LTC3778 Optional R
SENSE
Current Mode Synchronous Step-Down 4V ≤ V
IN
≤ 36V, Adjustable Frequency Up to 1.2MHz, TSSOP-20
Controller
LTC3832 Low V
IN
High Power Synchronous Controller V
OUT
≥ 0.6V, I
OUT
≤ 20A, 3V ≤ V
IN
≤ 8V
LTC4008 4A Multichemistry Multicell Battery Charger NiCd, NiMH, Lead Acid, Li-Ion Batteries; 6V ≤ V
IN
≤ 28V;
1.19V ≤ V
OUT
≤ 28V
No R
SENSE
is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
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