FM21LD16
2-Mbit (128 K × 16) F-RAM Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-86192 Rev. *C Revised November 13, 2014
2-Mbit (128 K × 16) F-RAM Memory
Features
■2-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128 K × 16
❐Configurable as 256 K × 8 using UB and LB
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (see the Data Retention and
Endurance table)
❐NoDelay™ writes
❐Page mode operation to 30-ns cycle time
❐Advanced high-reliability ferroelectric process
■SRAM compatible
❐Industry-standard 128 K × 16 SRAM pinout
❐60-ns access time, 110-ns cycle time
■Advanced features
❐Software-programmable block write-protect
■Superior to battery-backed SRAM modules
❐No battery concerns
❐Monolithic reliability
❐True surface mount solution, no rework steps
❐Superior for moisture, shock, and vibration
■Low power consumption
❐Active current 8 mA (typ)
❐Standby current 90 A (typ)
■Low-voltage operation: VDD = 2.7 V to 3.6 V
■Industrial temperature: –40 C to +85 C
■48-ball fine-pitch ball grid array (FBGA) package
■Pin compatible with FM22LD16 (4-Mbit) and FM23MLD16
(8-Mbit)
■Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM21LD16 is a 128 K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM21LD16 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by CE or simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric memory
process. These features make the FM21LD16 ideal for
nonvolatile memory applications requiring frequent or rapid
writes.
The FM21LD16 includes a low voltage monitor that blocks
access to the memory array when VDD drops below VDD min.
The memory is protected against an inadvertent access and data
corruption under this condition. The device also features
software-controlled write protection. The memory array is
divided into 8 uniform blocks, each of which can be individually
write protected.
The device is available in a 48-ball FBGA package. Device speci-
fications are guaranteed over the industrial temperature range
–40 °C to +85 °C.
For a complete list of related documentation, click here.
Address Latch & Write Protect
CE
Control
Logic
WE
Block & Row Decoder
A
I/O Latch & Bus Driver
OE
DQ
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
. . .
Column Decoder
. . .
UB, LB
16-2
A1-0
15-0
A16-0
Logic Block Diagram
FM21LD16
Document Number: 001-86192 Rev. *C Page 2 of 22
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation.............................................................. 4
Memory Operation....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation.................................................. 4
Software Write Protect ................................................ 4
Software Write-Protect Timing .................................... 7
SRAM Drop-In Replacement....................................... 8
Maximum Ratings............................................................. 9
Operating Range................ ... .............. ... .............. .. ........... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance....................................... 9
Capacitance ....................... ... .............. .............. ... ........... 10
Thermal Resistance........................................................ 10
AC Test Conditions................. .............. .. .............. ... ...... 10
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle..................................................... 12
Power Cycle and Sleep Mode Timing........................... 16
Functional Truth Table................................................... 17
Byte Select Truth Table.................................................. 17
Ordering Information...................................................... 18
Ordering Code Definitions......................................... 18
Package Diagram............................................................ 19
Acronyms........................................................................ 20
Document Conventions................ ............... .. .............. .. 20
Units of Measure ....................................................... 20
Document History Page................... ... .............. ... .......... 21
Sales, Solutions, and Legal Information...................... 22
Worldwide Sales and Design Support....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community................................. 22
Technical Support ..................................................... 22
FM21LD16
Document Number: 001-86192 Rev. *C Page 3 of 22
Pinout Figure 1. 48-ball FBGA pinout
Pin Definitions
Pin Name I/O Type Description
A16–A0Input Address inputs: The 17 address lines select one of 128K words in the F-RAM array. The lowest two
address lines A1–A0 may be used for page mode read and write operations.
DQ15–DQ0Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array.
WE Input Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM21LD16 to
write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address
for page mode write cycles.
CE Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow
page mode operation.
OE Input Output Enable: When OE is LOW, the FM21LD16 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
UB Input Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 256 K × 8, the UB and LB
pins may be tied to ground.
LB Input Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 256 K × 8, the UB and LB
pins may be tied to ground.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
WE
V
DD
A
11
A
10
NC
A
6
A
0
A
3
CE
DQ
10
DQ
8
DQ
9
A
4
A
5
DQ
13
DQ
12
DQ
14
DQ
15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ
0
UB
NC
NC
A
2
A
1
LB
V
DD
DQ
2
DQ
1
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
15
A
14
A
13
A
12
NC
3
26
5
4
1
D
E
B
A
C
F
G
H
NC NC
DQ
11
(not to scale)
Top View
(× 16)
A
16
FM21LD16
Document Number: 001-86192 Rev. *C Page 4 of 22
Device Operation
The FM21LD16 is a word wide F-RAM memory logically
organized as 131,072 × 16 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE transitions LOW or the upper address
(A16–A2) changes. See the Functional Truth Table on page 17
for a complete description of read and write modes.
Memory Operation
Users access 131,072 memory locations, each with 16 data bits
through a parallel interface. The F-RAM array is organized as
eight blocks, each having 4096 rows. Each row has four column
locations, which allow fast access in page mode operation.
When an initial address is latched by the falling edge of CE,
subsequent column locations may be accessed without the need
to toggle CE. When CE is deasserted HIGH, a pre-charge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
NoDelay writes.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE causes the address to be latched and starts a
memory read cycle if WE is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE is still LOW. The minimum
cycle time for random addresses is tRC. Note that unlike SRAMs,
the FM21LD16's CE-initiated access time is faster than the
address access time.
The FM21LD16 will drive the data bus when OE and at least one
of the byte enables (UB, LB) is asserted LOW. The upper data
byte is driven when UB is LOW, and the lower data byte is driven
when LB is LOW. If OE is asserted after the memory access time
is met, the data bus will be driven with valid data. If OE is
asserted before completing the memory access, the data bus will
not be driven until valid data is available. This feature minimizes
supply current in the system by eliminating transients caused by
invalid data being driven to the bus. When OE is deasserted
HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM21LD16, writes occur in the same interval as reads. The
FM21LD16 supports both CE and WE controlled write cycles. In
both cases, the address A16–A2 is latched on the falling edge of
CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when CE falls.
In this case, the device begins the memory cycle as a write. The
FM21LD16 will not drive the data bus regardless of the state of
OE as long as WE is LOW. Input data must be valid when CE is
deasserted HIGH. In a WE-controlled write, the memory cycle
begins on the falling edge of CE. The WE signal falls some time
later. Therefore, the memory cycle begins as a read. The data
bus will be driven if OE is LOW; however, it will be HI-Z when WE
is asserted LOW. The CE- and WE-controlled write timing cases
are shown in the page 14.
Write access to the array begins on the falling edge of WE after
the memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Page Mode Operation
The F-RAM array is organized as eight blocks, each having 4096
rows. Each row has four column-address locations. Address
inputs A1–A0 define the column address to be accessed. An
access can start on any column address, and other column
locations may be accessed without the need to toggle the CE pin.
For fast access reads, after the first data byte is driven to the bus,
the column address inputs A1–A0 may be changed to a new
value. A new data byte is then driven to the DQ pins no later than
tAAP
, which is less than half the initial read access time. For fast
access writes, the first write pulse defines the first write access.
While CE is LOW, a subsequent write pulse along with a new
column address provides a page mode write access.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
Pre-charge is also activated by changing the upper addresses,
A16–A2. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the tAA address
access time; see Figure 8 on page 13. A similar sequence occurs
for write cycles; see Figure 13 on page 14. The rate at which
random addresses can be issued is tRC and tWC, respectively.
Software Write Protect
The 128 K × 16 address space is divided into eight sectors
(blocks) of 16 K × 16 each. Each sector can be individually
software write-protected and the settings are nonvolatile. A
unique address and command sequence invokes the
write-protect mode.
To modify write protection, the system host must issue six read
commands, three write commands, and a final read command.
The specific sequence of read addresses must be provided to
FM21LD16
Document Number: 001-86192 Rev. *C Page 5 of 22
access the write-protect mode. Following the read address
sequence, the host must write a data byte that specifies the
desired protection state of each sector. For confirmation, the
system must then write the complement of the protection byte
immediately after the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a seventh
read address, or failing to complement the protection value will
leave the write protection unchanged.
The write-protect state machine monitors all addresses, taking
no action until this particular read/write sequence occurs. During
the address sequence, each read will occur as a valid operation
and data from the corresponding addresses will be driven to the
data bus. Any address that occurs out of sequence will cause the
software protection state machine to start over. After the address
sequence is completed, the next operation must be a write cycle.
The lower data byte contains the write-protect settings. This
value will not be written to the memory array, so the address is a
don't-care. Rather it will be held pending the next cycle, which
must be a write of the data complement to the protection settings.
If the complement is correct, the write-protect settings will be
adjusted. Otherwise, the process is aborted and the address
sequence starts over. The data value written after the correct six
addresses will not be entered into the memory.
The protection data byte consists of eight bits, each associated
with the write-protect state of a sector. The data byte must be
driven to the lower eight bits of the data bus, DQ7 - DQ0. Setting
a bit to ‘1’ write-protects the corresponding sector; a ‘0’ enables
writes for that sector. The following table shows the write-protect
sectors with the corresponding bit that controls the write-protect
setting.
The write-protect address sequence follows:
1. Read address 12555h
2. Read address 1DAAAh
3. Read address 01333h
4. Read address 0ECCCh
5. Read address 000FFh
6. Read address 1FF00h
7. Write address 1DAAAh
8. Write address 0ECCCh
9. Write address 0FF00h
10.Read address 00000h
Note If CE is LOw entering the sequence, then an address of
00000h must precede 12555h.
The address sequence provides a secure way of modifying the
protection. The write-protect sequence has a one in 3 × 1032
chance of randomly accessing exactly the first six addresses.
The odds are further reduced by requiring three more write
cycles, one that requires an exact inversion of the data byte.
Figure 2 on page 6 shows a flow chart of the entire write-protect
operation. The write-protect settings are nonvolatile. The factory
default: all blocks are unprotected.
For example, the following sequence write-protects addresses
from 0C000h to 13FFFh (sectors 3 and 4):
Table 1. Write Protect Sectors - 16 K × 16 Blocks
Sectors Blocks
Sector 7 1FFFFh–1C000h
Sector 6 1BFFFh–18000h
Sector 5 17FFFh–14000h
Sector 4 13FFFh–10000h
Sector 3 0FFFFh–0C000h
Sector 2 0BFFFh–08000h
Sector 1 07FFFh–04000h
Sector 0 03FFFh–00000h
Address Data
Read 12555h –
Read 1DAAAh –
Read 01333h –
Read 0ECCCh –
Read 000FFh –
Read 1FF00h –
Write 1DAAAh 18h; bits 3 and 4 = 1
Write 0ECCCh E7h; complement of 18h
Write 0FF00h Don’t care
Read 00000h
FM21LD16
Document Number: 001-86192 Rev. *C Page 6 of 22
Figure 2. Write-Protect State Machine
Normal Memory
Operation
Read 12555h?
Read
1DAAAh?
Any other
operation
Read 01333h?
Read
0ECCCh?
Read 000FFh?
Read 1FF00h?
Hold Data Byte
Write
0ECCCh?
Write
0FF00h?
y
n
n
n
n
n
y
y
y
y
n
y
Write
1DAAAh?
y
y
n
Read 00000h
To enter new write
protect settings
n
Read 1AAAAh to
drive write protect
settings
Write
0ECCCh?
y
Read 00000h
n
y
n
Change Write Protect
Settings Read Write Protect
Settings
Sequence Detector
Data
Complement?
y
n
FM21LD16
Document Number: 001-86192 Rev. *C Page 7 of 22
Software Write-Protect Timing
Figure 3. Sequence to Set Write-Protect Blocks [1]
CE
A
WE
DQ
12555
Data Data
OE
01333 0ECCC 000FF 1FF00 1DAAA 0ECCC 0FF00 000001DAAA
16-0
15-0
Figure 4. Sequence to Read Write-Protect Settings [1]
CE
WE
12555
XData
OE
01333 0ECCC 000FF 1FF00 0ECCC 000001DAAA
tCE (read access time)
1AAAA
A16-0
DQ15-0
Note
1. This sequence requires tAS > 10 ns and address must be stable while CE is LOW.
FM21LD16
Document Number: 001-86192 Rev. *C Page 8 of 22
SRAM Drop-In Replacement
The FM21LD16 is designed to be a drop-in replacement for
standard asynchronous SRAMs. The device does not require CE
to toggle for each new address. CE may remain LOW for as long
as 10 µs. While CE is LOW, the device automatically detects
address changes and a new access begins. It also allows page
mode operation at speeds up to 33 MHz.
Figure 5 shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks VDD to a high
enough value, so that the current drawn when CE is LOW is not
an issue. A 10-k resistor draws 330 µA when CE is LOW and
VDD = 3.3 V
Note that if CE is tied to ground, the user must be sure WE is not
LOW at power-up or power-down events. If CE and WE are both
LOW during power cycles, data will be corrupted. Figure 6 shows
a pull-up resistor on WE, which will keep the pin HIGH during
power cycles, assuming the MCU / MPU pin tristates during the
reset condition.The pull-up resistor value should be chosen to
ensure the WE pin tracks VDD to a high enough value, so that
the current drawn when WE is LOW is not an issue. A 10-k
resistor draws 330 µA when WE is LOW and VDD = 3.3 V.
Note If CE is tied to ground, the user gives up the ability to
perform the software write-protect sequence.
For applications that require the lowest power consumption, the
CE signal should be active (LOW) only during memory accesses.
The FM21LD16 draws supply current while CE is LOW, even if
addresses and control signals are static. While CE is HIGH, the
device draws no more than the maximum standby current, ISB.
CE toggling LOW on every address access is perfectly
acceptable in FM21LD16.
The UB and LB byte select pins are active for both read and write
cycles. They may be used to allow the device to be wired as a
256 K × 8 memory. The upper and lower data bytes can be tied
together and controlled with the byte selects. Individual byte
enables or the next higher address line A17 may be available
from the system processor.
Figure 5. Use of Pull-up Resistor on CE
Figure 6. Use of Pull-up Resistor on WE
Figure 7. FM21LD16 Wired as 256 K × 8
DQ
CE
UB
LB
WE
OE 2-Mbit F-RAM
FM21LD16
A
15-8
DQ7-0
D7-0
16-0
A17
A16-0
FM21LD16
Document Number: 001-86192 Rev. *C Page 9 of 22
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum junction temperature ................................... 95 C
Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (JEDEC Std JESD22-A114-D) ........ 2.5 kV
Charged Device Model (JEDEC Std JESD22-C101-C) .... 800 V
Machine Model (JEDEC Std JESD22-A115-A) ................. 200 V
Latch-up current ................................................... > 140 mA
Operating Range
Range Ambient Temper ature (TA) VDD
Industrial –40 C to +85 C 2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [2] Max Unit
VDD Power supply voltage 2.7 3.3 3.6 V
IDD VDD supply current VDD = 3.6 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
–812mA
ISB Standby current VDD = 3.6 V, CE at VDD,
All other pins are static and at
CMOS levels (0.2 V or VDD – 0.2 V)
TA = 25 C– 90 150 µA
TA = 85 C– – 270 µA
ILI Input leakage current VIN between VDD and VSS ––+1µA
ILO Output leakage current VOUT between VDD and VSS ––+1µA
VIH Input HIGH voltage 2.2 – VDD + 0.3 V
VIL Input LOW voltage – 0.3 – 0.6 V
VOH1 Output HIGH voltage IOH = –1.0 mA 2.4 – – V
VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – V
VOL1 Output LOW voltage IOL = 2.1 mA – – 0.4 V
VOL2 Output LOW voltage IOL = 100 µA – – 0.2 V
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Data retention TA = 85 C 10 – Years
TA = 75 C38–
TA = 65 C151–
NVCEndurance Over operating temperature 1014 – Cycles
Note
2. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
FM21LD16
Document Number: 001-86192 Rev. *C Page 10 of 22
AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ....................... 1.5 V
Output load capacitance............................................... 30 pF
Capacitance
Parameter Description Test Conditions Max Unit
CI/O Input/Output capacitance (DQ) TA = 25 C, f = 1 MHz, VDD = VDD(Typ) 8 pF
CIN Input capacitance 6pF
Thermal Resist ance
Parameter Description Test Conditions 48-ball FBGA Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
47 C/W
JC Thermal resistance
(junction to case)
14 C/W
FM21LD16
Document Number: 001-86192 Rev. *C Page 11 of 22
AC Switching Characteristics
Over the Operating Range
Parameters [3]
Description Min Max Unit
Cypress
Parameter Alt Parameter
SRAM Read Cycle
tCE tACE Chip enable access time – 60 ns
tRC –Read cycle time 110 – ns
tAA –Address access time – 110 ns
tOH tOHA Output hold time 20 – ns
tAAP –Page mode address access time – 25 ns
tOHP –Page mode output hold time 5 – ns
tCA –Chip enable active time 60 10,000 ns
tPC –Pre-charge time 50 – ns
tBA tBW UB, LB access time – 20 ns
tAS tSA Address setup time (to CE LOW) 0–ns
tAH tHA Address hold time (CE Controlled) 60 – ns
tOE tDOE Output enable access time – 15 ns
tHZ[4, 5] tHZCE Chip Enable to output HI-Z – 10 ns
tOHZ[4, 5] tHZOE Output enable HIGH to output HI-Z – 10 ns
tBHZ[4, 5] tHZBE UB, LB HIGHHIGH to output HI-Z – 10 ns
Notes
3. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified
IOL/IOH and load capacitance shown in AC Test Conditions on page 10.
4. tHZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
5. This parameter is characterized but not 100% tested.
FM21LD16
Document Number: 001-86192 Rev. *C Page 12 of 22
SRAM Write Cycle
tWC tWC Write cycle time 110 – ns
tCA –Chip enable active time 60 10,000 ns
tCW tSCE Chip enable to write enable HIGH 60 – ns
tPC –Pre-charge time 50 – ns
tPWC –Page mode write enable cycle time 25 – ns
tWP tPWE Write enable pulse width 16 – ns
tAS tSA Address setup time (to CE LOW) 0 – ns
tASP –Page mode address setup time (to WE LOW) 8 – ns
tAHP –Page mode address hold time (to WE LOW) 15 – ns
tWLC tPWE Write enable LOW to chip disabled 25 – ns
tBLC tBW UB, LB LOW to chip disabled 25 – ns
tWLA –Write enable LOW to A16-2 change 25 – ns
tAWH – A16-2 change to write enable HIGH 110 – ns
tDS tSD Data input setup time 14 – ns
tDH tHD Data input hold time 0 – ns
tWZ[6, 7] tHZWE Write enable LOW to output HI-Z – 10 ns
tWX[7] –Write enable HIGH to output driven 10 –ns
tWS[8] –Write enable to CE LOW setup time 0 – ns
tWH[8] –Write enable to CE HIGH hold time 0 – ns
AC Switching Characteristics (continued)
Over the Operating Range
Parameters [3]
Description Min Max Unit
Cypress
Parameter Alt Parameter
Notes
6. tWZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
7. This parameter is characterized but not 100% tested.
8. The relationship between CE and WE determines if a CE- or WE-controlled write occurs. The parameters tWS and tWH are not tested.
FM21LD16
Document Number: 001-86192 Rev. *C Page 13 of 22
Figure 8. Read Cycle Timing 1 (CE LOW, OE LOW)
Figure 9. Read Cycle Timing 2 (CE Controlled)
Figure 10. Page Mode Read Cycle Timing [9]
A
tRC
tAA
Previous Data Valid Data
tOH
Valid Data
tRC
tAA
tOH
DQ
16-0
15-0
tAS
A
DQ
tCE
tHZ
tOE
tOH
tOHZ
UB / LB
OE
CE
tBA tBHZ
tCA tPC
tAH
16-0
15-0
tAS
tHZ
tAAP
tOHP
CE
A
OE
DQ
tCA
A
tOE
tCE
tOHZ
tPC
Data 0 Data 1 Data 2
Col 0 Col 1 Col 2
16-2
1-0
15-0
Note
9. Although sequential column addressing is shown, it is not required
FM21LD16
Document Number: 001-86192 Rev. *C Page 14 of 22
Figure 11. Write Cycle Timing 1 (WE Controlled) [10]
Figure 12. Write Cycle Timing 2 (CE Controlled)
Figure 13. Write Cycle Timing 3 (CE LOW) [10]
tWZ
tHZ
D in
CE
A
WE
tCA tPC
DQ
tWP
tCW
tAS
D out D out
tDS
tDH
tWLC
15-0
16-0
tWX
CE
A
WE
DQ
tAS
tDH
tDS
D in
tCA tPC
UB/LB
tBLC
15-0
16-0
tWS tWH
tDH
tWX
D in
A
WE
DQ
tWC
tWLA
tDS
tAWH
D out D out
tWZ
D in
16-0
15-0
Note
10. OE (not shown) is LOW only to show the effect of WE on DQ pins.
FM21LD16
Document Number: 001-86192 Rev. *C Page 15 of 22
Figure 14. Page Mode Write Cycle Timing
tASP
tDH
CE
A
WE
tCA tPC
tCW
Col 0 Col 1
Data 0
Col 2
tAS
tDS
Data 1
tWP
Data 2
OE
tAHP
tPWC
tWLC
16-2
A1-0
DQ15-0
Note
11. U B and LB to show byte enable and byte masking cases.
FM21LD16
Document Number: 001-86192 Rev. *C Page 16 of 22
Power Cycle and Sleep Mode Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up (after VDD min. is reached) to first access time 450 –µs
tPD Last write (WE HIGH) to power down time 0 – µs
tVR[12, 13] VDD power-up ramp rate 50 –µs/V
tVF[12, 13] VDD power-down ramp rate 100 –µs/V
Figure 15. Power Cycle Timing
VDD tVF
VDD min
min
VDD
tVR
tPU
tPD
Access Allowed
Notes
12. Slope measured at any point on the VDD waveform.
13. Cypress cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict when VDD is below the level of a transistor
threshold voltage. Cypress strongly recommends that VDD power up faster than 100 ms through the range of 0.4 V to 1.0 V.
FM21LD16
Document Number: 001-86192 Rev. *C Page 17 of 22
Functional Truth Table
CE WE A16-2 A1-0 Operation [14, 15]
H X X X Standby/Idle
↓
L
H
H
V
V
V
V
Read
L H No Change Change Page Mode Read
L H Change V Random Read
↓
L
L
L
V
V
V
V
CE-Controlled Write[15]
L↓VVWE-Controlled Write [15, 16]
L↓No Change V Page Mode Write [17]
↑
L
X
X
X
X
X
X
Starts pre-charge
Byte Select Truth Table
WE OE LB UB Operation [18]
H H X X Read; Outputs disabled
XHH
H L H L Read upper byte; HI-Z lower byte
L H Read lower byte; HI-Z upper byte
L L Read both bytes
L X H L Write upper byte; Mask lower byte
L H Write lower byte; Mask upper byte
L L Write both bytes
Notes
14. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH.
15. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first.
16. WE-controlled write cycle begins as a Read cycle and then A16-2 is latched.
17. Addresses A1-0 must remain stable for at least 10 ns during page mode operation.
18. The UB and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256 K x 8.
FM21LD16
Document Number: 001-86192 Rev. *C Page 18 of 22
Ordering Code Definitions
Ordering Information
Access time (ns) Ordering Code Package Diagram Package Type Operating Range
60 FM21LD16-60-BG 001-91158 48-ball FBGA (Not Recom-
mended for New Design)
Industrial
FM21LD16-60-BGTR
All the above parts are Pb-free.
Option:
blank = Standard; TR = Tape and Reel
Package Type:
BG = 48-ball FBGA
Access Time: 60 ns
I/O Width: × 16
Voltage: 2.7 V to 3.6 V
2-Mbit Parallel F-RAM
Cypress
21FM LD 16 - 60 - BG TR
FM21LD16
Document Number: 001-86192 Rev. *C Page 19 of 22
Package Diagram
Figure 16. 48-ball FBGA (6 mm × 8mm × 1.2 mm) Package Outline, 001-91158
001-91158 **
FM21LD16
Document Number: 001-86192 Rev. *C Page 20 of 22
Acronyms Document Conventions
Units of Measure
Acronym Description
CPU Central Processing Unit
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
F-RAM Ferroelectric Random Access Memory
I/O Input/Output
MCU Microcontroller Unit
MPU Microprocesser Unit
RoHS Restriction of Hazardous Substances
R/W Read and Write
SRAM Static Random Access Memory
FBGA Fine-pitch Ball Grid Array
Symbol Unit of Measure
°C degree Celsius
Hz hertz
kHz kilohertz
kkilohm
MHz megahertz
Amicroampere
Fmicrofarad
smicrosecond
mA milliampere
ms millisecond
Mmegaohm
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
FM21LD16
Document Number: 001-86192 Rev. *C Page 21 of 22
Document History Page
Document Title: FM21LD16, 2-Mbit (128 K × 16) F-RAM Memory
Document Number: 001-86192
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 3912933 GVCH 02/25/2013 New spec
*A 4191946 GVCH 11/14/2013 Added watermark as “Not recommended for new designs.”
*B 4274811 GVCH 03/11/2014 Converted to Cypress standard format
Updated Maximum Ratings table
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Updated Data Retention and Endurance table
Added Thermal Resistance table
Removed Package Marking Scheme (top mark)
*C 4569028 GVCH 11/13/2014 Added related documentation hyperlink in page 1.
Document Number: 001-86192 Rev. *C Revised November 13, 2014 Page 22 of 22
All products and company names mentioned in this document may be the trademarks of their respective holders.
FM21LD16
© Cypress Semiconductor Corporation, 2013-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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