Semiconductor Components Industries, LLC, 2003
February, 2003 - Rev. 3 1Publication Order Number:
MMBF5457LT1/D
MMBF5457LT1
Preferred Device
JFET − General Purpose
Transistor
N-Channel
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain-Source Voltage VDS 25 Vdc
Drain-Gate Voltage VDG 25 Vdc
Reverse Gate-Source Voltage VGS(r) -25 Vdc
Gate Current IG10 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR-5 Board(1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction-to-Ambient RJA 556 °C/W
Junction and Storage Temperature TJ, Tstg - 55 to
+150 °C
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Preferred devices are recommended choices for future use
and best overall value.
Device Package Shipping
ORDERING INFORMATION
MMBF5457LT1 SOT-23 3000/
Tape & Reel
SOT-23 (TO-236AB)
CASE 318
Style 10
MARKING
DIAGRAM
6 = Specific Device Code
D = Year
12
3
2 SOURCE
3
GATE
1 DRAIN
6D
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Gate-Source Breakdown Voltage
(IG = 10 Adc, VDS = 0) V(BR)GSS -25 - - Vdc
Gate Reverse Current
(VGS = 15 Vdc, VDS = 0)
(VGS = 15 Vdc, VDS = 0, TA = 100°C)
IGSS -
--
--1.0
-200
nAdc
Gate Source Cutoff Voltage
(VDS = 15 Vdc, ID = 10 nAdc) VGS(off) -0.5 - - 6.0 Vdc
Gate Source Voltage
(VDS = 15 Vdc, ID = 100 Adc) VGS - - 2.5 - Vdc
ON CHARACTERISTICS
Zero-Gate-V oltage Drain Current (Note 2)
(VDS = 15 Vdc, VGS = 0) IDSS 1.0 - 5.0 mAdc
SMALL-SIGNAL CHARACTERISTICS
Forward Transfer Admittance (Note 2)
(VDS = 15 Vdc, VGS = 0, f = 1.0 kHz) |Yfs| 1000 - 5000 mhos
Output Common Source Admittance
(VDS = 15 Vdc, VGS = 0, f = 1.0 kHz) |yos| - 10 50 mhos
Input Capacitance
(VDS = 15 Vdc, VGS = 0, f = 1.0 MHz) Ciss - 4.5 7.0 pF
Reverse Transfer Capacitance
(VDS = 15 Vdc, VGS = 0, f = 1.0 MHz) Crss - 1.5 3.0 pF
1. FR- 5 = 1.0 0.75 0.062 in.
2. Pulse Test: Pulse Width ≤ 630 ms, Duty Cycle ≤ 10%.
MMBF5457LT1
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TYPICAL CHARACTERISTICS
Figure 1. Noise Figure versus Source
Resistance
VDS, DRAIN−SOURCE VOLTAGE (VOLTS)
Figure 2. Typical Drain Characteristics
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Figure 3. Common Source Transfer
Characteristics
1.0
0.4
0.2
0
−1.2
0.8
0.6
0 5 10 15 20 25
0
0.6
0.4
0.2
0.8
1.2
1.0
−0.8 −0.4 0
1.2
, DRAIN CURRENT (mA)
D
I
, DRAIN CURRENT (mA)
D
I
VDS = 15 V
VGS = 0 V
−0.2 V
−0.4 V
−0.6 V
−0.8 V
−1.0 V
VGS(off) −1.2 V
VGS(off) −1.2 V
RS, SOURCE RESISTANCE (Megohms)
14
12
10
8
6
4
2
0
NF, NOISE FIGURE (dB)
0.001 0.01 0.1 1.0 10
VDS = 15 V
VGS = 0
f = 1 kHz
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TYPICAL CHARACTERISTICS
VDS, DRAIN−SOURCE VOLTAGE (VOLTS)
Figure 4. Typical Drain Characteristics
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Figure 5. Common Source Transfer
Characteristics
VDS, DRAIN−SOURCE VOLTAGE (VOLTS)
Figure 6. Typical Drain Characteristics
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Figure 7. Common Source Transfer
Characteristics
0
0
4
3
2
1
0
10
4
2
0
−4
5
510152025
5
4
3
2
1
0
−7
8
6
−6 −5 −4 −3 −2 −1
−5 −3 −2 −1 0
, DRAIN CURRENT (mA)
D
I
VDS = 15 V
VGS(off) −5.8 V
, DRAIN CURRENT (mA)
D
I
, DRAIN CURRENT (mA)
D
I, DRAIN CURRENT (mA)
D
I
VDS = 15 V
10
4
2
0
8
6
0 5 10 15 20 25
VGS(off) −5.8 V
VGS = 0 V
VGS = 0 V
−2 V
−1 V
−3 V
−1 V
−2 V
−3 V
−4 V
−5 V
VGS(off) −3.5 V
VGS(off) −3.5 V
Note: Graphical data is presented for dc conditions. Tabular
data is given for pulsed conditions (Pulse Width = 630
ms, Duty Cycle = 10%). Under dc conditions, self heat-
ing in higher IDSS units reduces IDSS.
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The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT-23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT-23 POWER DISSIPATION
PD = TJ(max) - TA
RJA
PD = 150°C - 25°C
556°C/W = 225 milliwatts
The power dissipation of the SOT-23 is a function of th e
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa-
tion. Power dissipation for a surface mount device is deter-
mined b y T J(max), the maximum rated junction temperature
of the die, RJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the SOT-23
package, PD can be calculated as follows:
The 556°C/W for the SOT-23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT-23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
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PACKAGE DIMENSIONS
CASE 318-08
ISSUE AH
SOT-23 (TO-236AB)
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4. 318−03 AND −07 OBSOLETE, NEW STANDARD
318−08.
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
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changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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MMBF5457LT1/D
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