FI A Tt} u a a XN ABUBEEERA ie ICS82C404 Advance Information Dual Programmable Graphics Frequency Generator Features * Pin for pin and function compatible with [CD's version of the 82C404 Dual programmable graphics clock generator Memory and video clocks are individually programmable on-the-fly * Ideal for designs where multiple or varying frequencies are required * Increased frequency resolution from optional pre-divide by 2 on the M counter Output enable feature available for tri-stating outputs Independent clock outputs range from 390 kHz to 120 MHz Operation up to 140 MHz available Power-down capabilities Low power, high speed 0.8 1. CMOS technology Glitch-free transitions Available in 16 pin PDIP or SOIC package Block Diagram General Description The 1CS82C404 is a fully programmable graphics clock generator. It can generate user specified clock frequen- cies using an externally generated input reference or a single crystal. The output frequency is programmed by entering a 24 bit digital word through the serial port. Two fully user-programmable phase-locked loops are offered ina single package. One PLL is designed to drive the memory clock, while the second drives the video clock. The outputs may be changed on-the-fly to any desired frequency between 390 kHz and 120 MHz. The 1CS82C404 is ideally suited for any design where mul- tiple or varying frequencies are required. This part is ideal for graphics applications. It generates low jitter, high speed pixel clocks. It can be used to replace multiple, expensive high speed crystal oscilla- tors. The flexibility of the device allows it to generate non-standard graphics clocks. The leader in the area of multiple output clocks on a single chip, ICS has been shipping graphics frequency generators since October, 1990, and is constantly im- proving the phase locked loop. The ICS82C404 incorpo- rates a patented fourth generation PLL that offers the best jitter performance available. B-47ICS82C404 Pin Configuration 0 SELO/CLK []1 16 [] /PD SEL1/DATA []2 15 [|] EXTSEL VDD []}3 14 [] INIT1 OE [|4 S 13 [] vppD i GND {[5 @ 12{] INITO x1 rl 11 |] EXTCLK x2 [7 10 [] /FPMODE MCLK []8 9 i VCLK 16-Pin DIP or SOIC K-4, K-6 Pin Description Pin Name Description SELO-CLK Clock input in serial programming mode Clock select pin in mode SEL1-DATA Data input in serial programming mode External clock Power-down active low B-48ICS82C404 Register Definitions - The register file consists of the following six registers: Reglster Addressing Addresq Register Definition 000 REGO Video Clock Register 1 001 REG1 Video Clock Register 2 010 REG2 Video Clock Register 3 011 MREG Memory Register 100 PWRDWN Divisor for Power-down mode 110 CNTLREG | Control Register The ICS82C404 places the three video clock registers and the memory clock register in a known state upon power- up. The registers are initialized based on the state of the INIT1 and INITO pins at application of power to the device. The INIT pins mustramp up with VDDifa logical 1 oneither pinis required. These input pins are internally pulled down and will default to a logical 0 if left unconnected. The registers are initialized as follows: Register Initialization INIT1) _INITO! MREG | REGO | REG} REG2 | 0 0 32.500 | 25.175 | 28.322 | 28322 0 1 40.000 | 25.175 | 28.322 | 28.322 1 0 50.350 | 40.000 | 28.322 | 28.322 1 1 56.644 | 40.000 | 50.350 | 50.350 Register Selection When the ICS82C404 is operating, the video clock output is controlled with a combination of the SELO, SEL1, /PD, and OE pins. The video clock is also multiplexed to an extemal clock (EXTCLK) which can be selected with the EXTSEL pin. The VCLK Selection Table shows how VCLK is selected. VCLK Selection OE | /PDIEXTSEL| /EPMODEISEL1| SELQ . VCLK 0] x x x x x Tri-State 1] 0 x x x x |Forced High 1 1 x 1 0 0 REGO 1 1 x 1 0 1 REG1 1]1 0 1 1 QO | EXTCLK 1 1 1 1 1 x REG2 1 1 x 1 1 1 REG2 1 [1 x 0 x x REG2 As seen in the table above, OE acts to tri-state the output. The /PD pin forces the VCLK signal high while power- ing down the part. The EXTCLK pin will only be multi- plexed in when EXTSEL and SELO are logic 0 and SEL1 is a logic 1. The memory clock outputsare controlled by /PD and OE as follows: MCLK Selection OE fPD MCLK 0 x Tri-State 1 1 MREG 1 0 PWRDWN The Clock Select pins SELO and SEL1 have two purposes. In seria] programming mode, these pins act as the clock and data pins. New data bits come in on SEL1 and these bits are clocked in by a signal on SELO. While these pins are acquiring new information, the VCLK signal remains unchanged. When SELO and SEL] are acting as register selects, a timeout interval is required to determine whether the user is selecting a new register or wants to program the part. During this initial timeout, the VCLK signal remains at its previous frequency. At the end of this timeout interval, a new register is selected. A second timeout interval is required to allow the VCO to settle to its new value. During this period of time, typically 5 msec, the input reference signal is multiplexed to the VCLK signal. When MCLK or the active VCLK register is being repro- grammed, then the reference signal is multiplexed glitch- free to the output during the first timeout interval. A second timeout interval is also required to allow the VCO to settle. During this period, the reference signal is multiplexed to the appropriate output signal. B-49ICS82C404 Control Register Definition The control register allows the user to adjust various internal options. The register is defined as follows: Bit Bit Name Default Value Description 9 C5 C4 C2 Cl co NS2 NS1 NSO 0 This bit determines which power-down mode the /PD pin will implement. Power-down mode 1, C5 = 0, forces the MCLK signal to be a function of the power-down register. Power-down mode 2, C5 = 1, turns off the crystal and disables all outputs. This bit determines which clock is multiplexed to VCLK during frequency changes. C4 = 0 multiplexes the refer- ence frequency to the VCLK output. C4 = 1 multiplexes MCLK to the VCLK output for applications where the graphics controller cannot run as slow as fREr. This bit determines the length of the timeout interval. The timeout interval is derived from the MCLK VCO. If this VCO is programmed to certain extremes, the timeout interval maybe too short. C3 = 0, normal timeout. C3 = 1, doubled timeout interval. Reserved, must be set to 0. This bit adjusts the duty cycle. C1 = 0 causes a Ins de- crease in output high time. C1 = 1 causes no adjustment. If the load capacitance is high, the adjustment can bring the duty cycle closer to 50%. Reserved, must be set to 0. Acts on register 2. NS2 = 0 prescales the N counter by 2. NS2 = 1 prescales the P counter value to 4. Acts on register 1. NS1 = 0 prescales the N counter by 2. NS1 = 1 prescales the P counter value to 4. Acts on register 0. NSO = 0 prescales the P counter by 2. NSO = 1 prescales the P counter value to 4. B-50ICS82C404 Serial Programming Architecture The pins SELO and SEL1 perform the dual functions of selecting registers and serial programming. In serial programming mode, SELO acts as a clock pin while SEL1 acts as the data pin. The ICS82C404-01 may notbe serially programmed when in power-down mode. In order to program a particular register, an unlocking sequence must occur. The unlocking sequence is detailed in the following timing diagram: SEL1-DATA SELO-CLK The unlock sequence consists of at least 5 low-to-high transitions of CLK while data is high, followed immedi- ately by a single low-to-high transition while data is low. Following this unlock sequence, data can be loaded into the serial data register. Following any transition of CLK or DATA, the watchdog timer is reset and begins counting. The watchdog timer ensures that successive rising edges of CLK and DATA do not violate the timeout specification of 2ms. If a timeout occurs, the lock mechanism is reset and the data in the serial data register is ignored. Since the VCLK registers are selected by the SELO and SEL1 pins, and since any change in their state may affect the output frequency, new data input on the selection bits is only permitted to pass through the decode logic after the watchdog timer has timed out. This delay of SELO or SEL1 data permitsa serial program cycle to occur without affecting the current register selection. Serial Data Register The serial data is clocked into the serial data register in the order described in figure 1 below (Serial Data Timing). The serial data is sent as follows: An individual data bit is sampled on the rising edge of CLK. The complement of the data bit must be sampled on the previous falling edge of CLK. The setup and hold time requirements must be met on both CLK edges. For specifics on timing, see the timing diagrams on pages 10, 11, and 12. The bits are shifted in this order: a start bit, 21 data bits, 3 address bits (which designate the desired register), and a stop bit. A total of 24 bits must always be loaded into the serial data register or an error is issued. Following the entry of the last data bit, a stop bit or load command is issued by bringing DATA high and toggling CLK high- to-low and low-to-high. The unlocking mechanism then resets itself following the load. Only after a timeout period are the SELO and SEL1 pins allowed to return toa register selection function. Data Bits Address Bits aw 0 Figure 1 - Serial Data Timing B-51ICS82C404 The serial data register is exactly 24 bits long, enough to accept the data being sent. The stop bit acts as a load command that passes the contents of the Serial Data Register into the register indicated by the three address bits. Ifa stop bit is not received after the serial register is full, and more data is sent, all data in the register is ignored and an error issued. If correct data is received, then the unlocking mechanism rearms, all data in the serial data register is ignored, and an error is issued. Programming the iCS82C404 The ICS82C404 has a wide operating range, but it is recommended that it is operated within the following limits: 1 MHz < Pye < 60 MHz Fyer = Input Reference Frequency 200 KHz < Frpp py <5 MHz M = Reference divide 3 to 129 50 MHz < Fycg < 120 MHz Fyco = VCO output frequency Fox $120 MHz Fox = output frequency The frequency of the programmable oscillator Fyco is determined by the following fields: Field # of Bits Index (1) 4 N counter value (N) 7 Mux (R) 3 M counter value (M) 7 Where the least significant bit is the last bit of M and the most significant bit is the first bit of I. The equations used to determined the oscillator frequency are: N=N+3 M=M+2 Fyco = Prescale -N/M - Foy where 3 < M <129 and 4<N< 130 and prescale = 2 or 4, as set in the control register The value of F,-. must remain between 50 MHz and 120 MHz. As a result, for output frequencies below 50MHz, Fyco must be brought into range. To achieve this, an output divisor is selected by setting the values of the Mux Field (R) as follows: Output Divisor R Divisor 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Unlike the ICD's 82C404, the ICS82C404s VCO does not require tuning to placeitin certain ranges. The ICS82C404s VCO will operate from 50 MHz to 120 MHz without adjusting the VCO gain. However, to maintain compat- ibility, the I bits are programmed as in the ICD2061A. These bits are dummy bits except for the following two cases: Index Field (I) I VCLK Ey co MCLK Fycg 1110 Turn off VCLK 50-120 MHz 1111 Mux MCLK to VLCK 50-120 MHz When theindex field is set to 1111, VCLK is tumed off and both channels run from the same MCLK VCO. This is done in an effort to reduce jitter, which may increase when VCOs runat 2" multiples of one another . If the two outputs must be multiples of one another, itis best to mux MCLK over to the output of the VCLK VCO, and to power-down the VCLK VCO. The multiplexed frequency will be divided down by the correct divisor (M) and output on VCLK. B-52ICS8&2C404 Power Management Issues Power-down mode 1 The ICS82C404 contains a mechanism to reduce the qui- escent power when stand-by operation is desired. Power- down mode 1 is invoked by pulling /PD low and having the proper CNTL register bit set to zero. In this mode, VCOs are shut down, the VCLK output is forced high, and the MCLK output is set to a user-defined low fre- quency value to refresh dynamic RAM. The power-down MCLK value is determined by the following equation: MCLKopp = Ferg / (PWRDWN register divisor value) The power-down register divisor is determined accord- ing to the 4-bit word programmed into the PVRDWN register (see table below). Power Down Register Code Power-down mode 2 When there is no need for any output during power- down, an alternate mode is available which will com- pletely shutdown all outputs and the reference oscillator, but still preserves all register contents. Power-down mode 2 is invoked by first programming the power-down bitin the CNTL register and then pulling the /PD pin low. The /PD pin The /PD pin has a standard internal pull-up resistor during normal operation. When the chip goes into power- down mode 1 or 2, the normal pull-up resistor is dynami- cally switched to a weak pull-up, which reduces power consumption. If the /PD pinis allowed to float after it has been pulled down, the weak pull-up will bring the signal high and allow the device to resume operation. PWRDWN bits PWRDWN Power-down MCLK,, P3 P2 Pl Po Register Value Divisor (fgpp =14.31818) 0 0 0 0 0 n/a n/a 0 0 0 1 1 32 447.4 KHz 0 0 1 0 2 30 477.3 KHz 0 0 1 1 3 28 511.4 KHz 0 1 0 0 4 26 550.7 KHz 0 1 0 1 5 24 596.6 KHz 0 1 1 0 6 22 650.8 KHz 0 1 1 1 7 20 715.9 KHz 1 0 0 0 8 (default) 18 795.5 KHz 1 0 0 1 9 16 894.9 KHz 1 0 1 0 A 14 1.02 MHz 1 0 1 1 B 12 1.19 MHz 1 1 0 0 Cc 10 1.43 MHz 1 1 0 1 D 8 1.79 MHz 1 1 1 0 E 6 2.39 MHz 1 1 1 1 F 4 3.58 MHz B-53ICS82C404 Absolute Maximum Ratings Storage temperature... cccecesscccerceenassees -40C to +150C VDD referenced to GND.............- Voltage on Ho pins referenced to GND...... GND -0.5V Operating temperature under b C to +70C to VDD +05V Power dissipation.....cssscssssssresesescserssneseenssees 05 Watts Note: Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for extended periads may affect device reliability. Electrical Characteristics (VDD= +5V 5%, OC S$ TayeprenrS +70C unless otherwise stated) Device Specifications Maximum Ratings Name Description Max ture Junction Package dissipation DC Characteristics Name Description Min Typ | Max | Units | Conditions Vig High level input voltage 2.0 Vv Vir Low level input voltage 0.8 v Vou High level CMOS ouput voltage 3.84 Vv Toy = 4: ma Vor Low level output voltage 0.4 Vv Ig, = 4. ma Thy Input high current 100 pa Vy = 5.25 V I Input low current -250 pa Vy = OV loz Output leakage current 10 pa (tri-state) Ipp Power supply current 15 65 ma lpn Power supply current (typical) 35 ma @60 MHz Tapp Analog power supply current 10 ma Ipp) Power-down current (Mode 1) 6 7.5 ma Top Power-down current (Mode 2) 25 50 pia Cw Input capacitance 10 pf B-54ICS82C404 AC Characteristics ymbol Name Description Min | Typ Max Units freer Reference Reference oscillator value 1 14.31818 60 Mhz fx | (note 1} tec Reference period] 1/fprr 16.6 1000 ns t; Input duty cycle} Duty cycle for the input oscillator defined as t,/t, 25% 75% t Output clock Output oscillator values 8.33 2564 ns periods (120 MHz) 390 MHz) ts Output duty Duty cycle for the output cycle oscillators (note 2) 45% 55% & Rise times Rise time for the output oscillators into a 25 pf load 3 ns ts Fall times Fall time for the output oscillator into a 25 pf load 3 ns teeat freq] output Old frequency output beeaa? freq2 output New frequency output ta fgep Mux time Time clock output remains high while output muxes to reference frequency | tarp eter ns timeout |! imeout internal] Interval for serial program- ming and for VCO changes to settle (note 3) 2 5 10 ns te trreqz Huxtime Time clock ouput remains high while output muxes to new 05 + 15 _frequency value REF REF ns ts Tri-state Time for the ouput oscillators to go into tri-state mode after OUTDIS - signal assertion 0 12 ns ty CLK valid Time for the output oscillators to recover from tri-state mode after OUTDIS -signal goes high 0 12 ns__| ty Power-Down Time for power-down mode of operation to take effect 12 ns ty Power-Up Time for recovery from power-down mode of operation 12 ns__| tig MCLKOUT Time for MCLK to go high high after PWRDWN is asserted high 0 tpwRDWN ns ty MCLKOUT Delay of MCLK prior to fucix delay signal at output St ore Stock ns took Clock period of serial clock 2 - toon 2 msec | tere Setup time 20 ns tup Hold time 10 ns tdcmd Load command 0 t,+30 ns NOTES 1. For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally. 2. Duty cycle is measured at CMOS threshold levels. At5 volts, Vz, = 2.5 volts). 3. If the interval is too short, see the timeout interval section in the control register definition. B-55ICS82C404 REF p XTAL IN fREF VCLK MCLK Rise and Fall Times OUTDIS* | VCLK MCLK Tri-Stated Timing B-56ICS82C404 1 ! I I Selection Recognition Time ' VCO Settle time | New Frequency State SELO ! A SEL1 KY . ; { timeout ; timeout ' I ' Internal 1 ! Timeout ; ! I 1 i I I VCLK TU Yireq! tREF a 4req2 Selection Timing t t 1 I ' VCO Settle time | New Frequency State Stop L i Bit I I ! | bimeout \ t | . t (Internal 1 I Timeout) T ! t ! I \ I I VCLK 1 1 MCLK 1 1 treq1 ta tREF ta rege Or tMCLK if bit set in Controt Register MCLK & Active VCLK Register Programming Timing B-57iICS82C404 This is when VCLK directly muxes to VCLK PLL I 1 I 1 ! 1 i I (may glitch) i t T t I i 1 forced high U UML LPP ( 1 {Mick pwROWN faci! > (value from PWRDOWN register) 1)It takes 2-10 msec after soft power-down to guarantee lock of VCLK & MCLK PLLs Soft Power-Down Timing (Mode 2) Unlock Sequence Start Bit 1 I tsarcik 2 ! 3 al s| CLK Valid Data Sequence (24 bits) Stop Bit ; 1 ' 1 CLK > Lt Lo f tgy HD tsu \ /'HD l i? DATA rm [ WY 0 0 1 1 0 ! 1 demd [ (intemal Load Register Command) Serial Programming Timing B-58ICS82C404 ORDERING INFORMATION Part Number Temperature Range Package Type |B ICS82C404-xxCW16 0C to +70C 16 lead Plastic SOIC ICS82C404-xxCN16 OC to +70C 16 lead Plastic DIP B-59