ssaene8 Corporation ispLSI 2096E in-System Programmable SuperFAST High Density PLD Features SUPERFAST HIGH DENSITY iN-SYSTEM PROGRAMMABLE LOGIC ~ 4000 PLD Gates ~ 96 I/O Pins, Six Dedicated inputs 96 Registers ~ High Speed Global Interconnect Wide input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic - 100% Functional/JEDEC Upward Compatible with ispLSI 2096 Devices + HIGH PERFORMANCE E*CMOS* TECHNOLOGY fmax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay ~ TTL Compatible Inputs and Outputs 5V Programmable Logic Core ~ ispJTAG In-System Programmabie via IEEE 1149.1 (JTAG) Test Access Port ~~ User-Selectable 3.3V or 5V /O Supports Mixed- Voltage Systems -~- PCI Compatible Outputs ~~ Open-Drain Output Option - Electrically Erasable and Reprogrammable ~ Non-Volatile -~ Unused Product Term Shutdown Saves Power * ispLSI OFFERS THE FOLLOWING ADDED FEATURES ~ increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soidered Devices for Faster Prototyping + OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Giue Logic and Structured Designs ~ Enhanced Pin Locking Capability - Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Siew Rate Controi to Minimize Switching Noise - Flexible Pin Placement Optimized Globai Routing Pool Provides Globai Interconnectivity * ispEXPERT - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Toots, Timing Simulator and ispANALYZER PC and UNIX Platforms Functional Block Diagram Go en Ge zi = cn Gee | Gutput Routing Pool (ORP) | [_ Gatput Routing Pool (OAP) | ic? : [oe] fos] [es pe} [ea] [or] oc] - Joos hoo t apo Img 187 TT wt Els - wleld 2 ' Py S| 2 fos || 31 fel | . ic 14 . l lia ey e| . Ary 4 Global Routing Poo! | 2 fa} 3 GLB 4 (GRP) fas || 2) nye FF pe i Blimn| a He fe i Balliol bad J iL. 4 roy ret Pel hol fart fuel Teel Bois fe] | te) ed ey fe] be! S [Gutput Routing Poot (ORF) ] [ Ouaput Routing Pool AP) |, a EES EEE GEE oar at20R6E The ispLS! 2096E is a High Density Programmabie Logic Device. The device contains 96 Registers, 96 Universal 1/O pins, six Dedicated Input pins, three Dedicated Clock Inpul pins, two dedicated Global OE input pins and a Glabal Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLS! 2096E features SV in-system programmability and in-system diagnostic capabilities. The ispL.S! 2096E offers non-volatile reprogrammability of ali logic, as well as the interconnect to provide truly reconfigurable sys- tems. The basic unit of logic on the ispLS! 2096E device is the Generic Logic Block (GLB). The GLBs are labeled AO, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSi 2096E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 96 1/O cells, each of which is directly connected to an I/O pin. Each 1/O cell can be individually programmed to be a combinatorial input, output or bi- directional 1/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be pro- grammed independently for fast or slow output slew rate ta minimize overall output switching noise. By connecting Copyright 1998 Lattice Semiconductor Carp. Ait brand or product names are trademarks or reg:stered trademarks of thaw respective halders. The specifications and intorsration. herein are supject io change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124. U.S.A. Tel. (503) 681-0118; 1-800-LATTICE: FAX (503) 681-3037; http:/AwwwJatticesemi.com 52 November 1998= Lattice agent Semiconductor aneana Corporation Specifications ispLSI 2096E Functional Block Diagram Figure 1. ispLSI 2096E Functional Block Diagram o woe G o oO oO GO Te E Input Bus : i oo I Megablock + | L__Qutnut Routing Pool one) | a i [~~ ony | os eneric Logic 4 fo cs (OT c2 i ci x Blocks (GLBs} wwe i ~ mo J =" i i Yeo rod | Ey [oes . 2) | Als Ah 05 103 mE min, TT | || [EE [xoso Global wo4 . mols vo as WO8 | as [|S a 108 Routing | 88 ig W038 0 1 ty Fos WO 57 or Pool TH S [Jal [roe OR Lint = BIE) vos vO (GRP) i 5 |S) ES) | vo se W010 fe] | vose 1041 Layee B Pe] | #Gs2 WO 12 16 Ca] piest W013 : Esp | bose "Or Fey pO as yO15 Ee 1048, aN aes .. wane ih oA Bo Bt 1 e2 CT aa | TMSIN | | ct | 4 | BS i a el Lenn ial TL 100 pi Output Routing Poo! (OAP) RESET . | SCAN the VCCIO pins to a common 5V or 3.3V power supply, /O output levels can be matched to 5V or 3.3V compat- ible voltages. When connected to a 5V supply, the I/O pins provide PCI-compatible output drive. Eight GLBs, 32 1/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSi 2096E device contains three Megablocks. The GRP has as its inputs, the outputs from ail of the GLBs and all of the inputs from the bi-directional I/O cells. Allofthese signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2096E device are selected using the dedicated clock pins. Three dedicated clock pins (YO, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. 991772006 Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLS! 2096E are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a pro- grammable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispEXPERT software tools. 53Lattice Specifications ispLSI 2096E saneee Corporation External Timing Parameters Over Recommended Operating Conditions PARAMETER coup! # DESCRIPTION vain TAA aa Tne vain aioe UNITS tod1 A 1 | Data Prop Deiay, 4PT Bypass, ORP Bypass ~ | 5.0 - 75 ~ 110.0 ns tod2 A 2 | Data Prop Delay -~ |76 3 ~ |100) |13.0] ns | fmax A 3 | Clk Freq with Internal Feedback? 180} ~ | 136] - | 100) | MHz fmax (Ext) 4 | Clk Freq with External Feedback (gavin) 125 | - | 100} ~ | 77 | ~ | MHz fmax (Tog.) | - 5 | Clk Frequency, Max. Toggle 200} - |143/ - | 100, | MHz. tsut - 6 | GLB Reg Setup Time before Cik, 4 PT Bypass | 4.0 | 60) - 165 | - ns | tco1 7 OA 7 | GLB Reg Clk to Output Deiay, ORP Bypass -~ |30) - | 40 | 50 ns tn a 8 | GLB Reg Hold Time after Clk, 4 PT Bypass 00} ~- |} 00] - | a0) - ns tsu2 fo 9 | GLB Reg Setup Time before Clk 50| - .60| ~ |B8o0| - ns tco2 |. | 10 | GLB Reg Clk to Output Delay ~ |35: - /451 60] ns the | 44 [GLB Reg Hold Time after Cik Fool - o0/- |o0| = | ns tri A 12 | External Reset Pin to Output Delay ~ | 7.0) ~- [100] - 1135] ns trv - 13 | External Reset Pulse Duration ao; - |50|- 165.) | ns tptoeen B | 14] Input to Output Enable ~ E'Ta001 [120) 115.0] ns tptoedis C | 15 | Input to Output Disable _ ~ f100) ~ 120) ~ 150 ns tgoeen B | 16/GiobalOE OutputEnable ~t. fs50f- Tro, - }90/ ns tgoedis C | 417|GlobalOE Output Disable - |50] - 170) - | 901 ns twh - 18 | External Synch Clk Pulse Duration, High 25 ~ 3.5 ~ 5.0 Lu ns twi - 19 | External Synch Cik Pulse Duration, Low 25] -~- 135] - 504 - ns 1. Unless noted otherwise, all parameters use a GRP load of four GLBs. 20 PTXOR path. ORP and YO clock Table 2-00802/20966 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section.