General Description
The MAX5948A/MAX5948B are hot-swap controllers
that allow a circuit card to be safely hot plugged into a
live backplane. The MAX5948A/MAX5948B operate
from -20V to -80V and are well-suited for -48V power
systems. The MAX5948A is pin- and function-compati-
ble with both the LT1640AL and LT1640L. The
MAX5948B is pin- and function-compatible with both
the LT1640AH and LT1640H.
The MAX5948A/MAX5948B provide a controlled turn-on
to circuit cards preventing glitches on the power-supply
rail and damage to board connectors and components.
The MAX5948A/MAX5948B provide undervoltage, over-
voltage, and overcurrent protection. These devices
ensure the input voltage is stable and within tolerance
before applying power to the load.
Both the MAX5948A and MAX5948B protect a system
against overcurrent and short-circuit conditions by turning
off the external MOSFET in the event of a fault condition.
Both devices feature an open-drain power-good status
output, PWRGD for MAX5948A or PWRGD for
MAX5948B, that can be used to enable downstream
converters.
The MAX5948A/MAX5948B are available in an 8-pin SO
package. Both devices are specified for the extended
-40°C to +85°C temperature range.
Applications
Central-Office Switching
Network Switches/Routers
Server Line Cards
Base-Station Line Cards
Features
oAllow Safe Board Insertion and Removal from a
Live -48V Backplane
oPin- and Function-Compatible with
LT1640AL/LT1640L (MAX5948A)
oPin- and Function-Compatible with
LT1640AH/LT1640H (MAX5948B)
oWithstand -100V Input Transients with No
External Components
oOperate from -20V to -80V
oProgrammable Inrush and Short-Circuit Current
Limits
oProgrammable Overvoltage Protection
oProgrammable Undervoltage Lockout
oPower Up into a Shorted Load
oPower-Good Control Output
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
________________________________________________________________
Maxim Integrated Products
1
GATE
SENSEVEE
1
2
8
7
VDD
DRAINOV
UV
PWRGD
(PWRGD)
SO
TOP VIEW
3
4
6
5
MAX5948A
MAX5948B
( ) FOR MAX5948B.
Pin Configuration
19-3473; Rev 1; 8/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Typical Operating Circuit appears at end of data sheet.
Selector Guide
PART PWRGD POLARITY
MAX5948AESA Active Low (PWRGD)
MAX5948BESA Active High (PWRGD)
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX5948AESA+ -40°C to +85°C 8 SO
MAX5948BESA+ -40°C to +85°C 8 SO
+
Denotes a lead(Pb)-free/RoHS-compliant package.
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages are referenced to VEE, unless otherwise noted.)
Supply Voltage (VDD - VEE ) .................................-0.3V to +100V
PWRGD, PWRGD .................................................-0.3V to +100V
DRAIN (Note 1)........................................................-2V to +100V
SENSE ....................................................................-0.3V to +20V
GATE (internally clamped) .....................................-0.3V to +18V
UV and OV..............................................................-0.3V to +60V
Current through SENSE ....................................................±20mA
Current into GATE...........................................................±300mA
Current into Any Other Pin................................................±20mA
Current into Drain............................................-100mA to +20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)...................471mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
ELECTRICAL CHARACTERISTICS
(VEE = 0V, VDD = 48V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Operating Input Voltage Range VDD 20 80 V
Supply Current IDD VUV = 3V, OV = VEE, SENSE = VEE 0.7 2 mA
GATE DRIVER AND CLAMPING CIRCUITS
Gate Pin Pullup Current IPU GATE drive on, VGATE = VEE -30 -45 -60 µA
Gate Pin Pulldown Current IPD Any fault condition, VGATE = 2V 24 50 70 mA
External Gate Drive ∆VGATE VGATE - VEE, 20V ≤ VDD ≤ 80V 10 13.5 18 V
GATE to VEE Clamp Voltage VGSCLMP VGATE - VEE, current into GATE = 30mA 15 16.4 18 V
CIRCUIT BREAKER
Current-Limit Trip Voltage VCB VCB = VSENSE - VEE 40 50 60 mV
SENSE Input Bias Current ISENSE VSENSE = 50mV 0 -0.03 -1 µA
UV PIN
UV High Threshold VUVH UV low to high transition 1.213 1.243 1.272 V
UV Low Threshold VUVL UV high to low transition 1.198 1.223 1.247 V
UV Hysteresis VUVHY 20 mV
UV Input Bias Current IINUV VUV = VEE 0-0.5µA
OV PIN
OV High Threshold VOVH OV low to high transition 1.198 1.223 1.247 V
OV Low Threshold VOVL OV high to low transition 1.165 1.203 1.232 V
OV Hysteresis VOVHY 20 mV
OV Input Bias Current IINOV VOV = VEE 0-0.5µA
PWRGD OUTPUT SIGNAL REFERENCED TO DRAIN
DRAIN Input Bias Current IDRAIN VDRAIN = 48V 10 80 250 µA
P ow er - G ood Thr eshol d VPG VDRAIN - VEE, high to low transition 1.1 1.4 2.0 V
P ow er - G ood Thr eshol d H yster esi sV
PGHY 0.4 V
Note 1: Test condition per Figure 1. DRAIN current must be limited to the specified 100mA maximum.
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VEE = 0V, VDD = 48V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWRGD, PWRGD Output
Leakage IOH VPWRGD (MAX5948A) = 80V, VDRAIN = 48V,
VPWRGD (MAX5948B) = 80V, VDRAIN = 0V 10 µA
Power-Good Output Impedance
(PWRGD to DRAIN) ROUT VPWRGD (MAX5948B) (VDRAIN - VEE) < VPG 500 x
103MΩ
PWRGD Output Low Voltage VOL VPWRGD - VEE; VDRAIN - VEE < VPG,
IOUT = 1mA (MAX5948A) 0.11 0.4 V
PWRGD Output Low Voltage VOL VPWRGD - VDRAIN; VDRAIN = 5V,
IOUT = 1mA (MAX5948B) 0.11 0.4 V
AC PARAMETERS
OV High to GATE Low tPHLOV Figures 2, 3 0.5 µs
UV Low to GATE Low tPHLUV Figures 2, 4 0.4 µs
OV Low to GATE High tPLHOV Figures 2, 3 3.3 µs
UV High to GATE High tPLHVL Figures 2, 4 3.4 µs
SENSE High to GATE Low tPHLSENSE Figures 2, 5 2 3 4 µs
MAX5948A, Figures 2, 6 0.5DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD - DRAIN)
High
tPHLPG
MAX5948B, Figures 2, 6 0.5
µs
MAX5948A, Figures 2, 6 0.5DRAIN High to PWRGD High
DRAIN High to (PWRGD -
DRAIN) Low
tPLHPG
MAX5948B, Figures 2, 6 0.5
µs
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE,
unless otherwise specified.
Note 3: Limits are 100% tested at TA= +25°C and +85°C. Limits at -40°C are guaranteed by design.
2V
100mA MAX
MAX5948
PWRGD/PWRGD
OV
UV
VEE
VDD
DRAIN
GATE
TEST VOLTAGE
SENSE
Figure 1. -2V DRAIN Voltage Test Circuit
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 48V, VEE = 0V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5948 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
80 90604020 70503010
100
200
300
400
500
600
700
800
900
0
0 100
SUPPLY CURRENT vs. TEMPERATURE
MAX5948 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
7550250-25
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
-50 100
GATE VOLTAGE vs. SUPPLY VOLTAGE
MAX5948 toc03
SUPPLY VOLTAGE (V)
GATE VOLTAGE (V)
908010 20 30 50 6040 70
2
4
6
8
10
12
14
16
0
0100
GATE VOLTAGE vs. TEMPERATURE
MAX5948 toc04
TEMPERATURE (°C)
GATE VOLTAGE (V)
7550250-25
12.5
13.0
13.5
14.0
14.5
15.0
12.0
-50 100
CIRCUIT-BREAKER TRIP VOLTAGE
vs. TEMPERATURE
MAX5948 toc05
TEMPERATURE (°C)
TRIP VOLTAGE (mV)
7550250-25
49
50
51
52
53
54
55
48
-50 100
GATE PULLUP CURRENT vs. TEMPERATURE
MAX5948 toc06
TEMPERATURE (°C)
GATE PULLUP CURRENT (µA)
7550-25 025
41
42
43
44
45
46
47
48
40
-50 100
VGATE = 0V
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 5
VS
R
5kΩ
VOV
VUV
V+
5V
VSENSE
VDRAIN
48V
MAX5948A
MAX5948B
PWRGD/PWRGD
OV
UV
VEE
VDD
DRAIN
GATE
SENSE
Figure 2. Test Circuit 1
Typical Operating Characteristics (continued)
(VDD = 48V, VEE = 0V, TA= +25°C, unless otherwise noted.)
GATE PULLDOWN CURRENT
vs. TEMPERATURE
MAX5948 toc07
TEMPERATURE (°C)
GATE PULLDOWN CURRENT (mA)
7550250-25
35
40
45
50
55
60
30
-50 100
VGATE = 2V
PWRGD OUTPUT LOW VOLTAGE
vs. TEMPERATURE (MAX5948A)
MAX5948 toc08
TEMPERATURE (°C)
PWRGD OUTPUT LOW VOLTAGE (mV)
7550-25 0 25
5
10
15
20
25
30
35
40
0
-50 100
IOUT = 1mA
10,000
1000
100
10
1
-50 25-25 0 50 75 100
PWRGD OUTPUT IMPEDANCE
vs. TEMPERATURE (MAX5948B)
MAX5948 toc09
TEMPERATURE (°C)
OUTPUT IMPEDANCE (GΩ)
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
6 _______________________________________________________________________________________
Timing Diagrams
1.223V
OV
tPHLOV
0V
2V
1V
1.203V
1V
tPLHOV
GATE
Figure 3. OV to GATE Timing
tPHLUV
1.223V
1V 1V
1.243V
tPLHUV
UV
0V
2V
GATE
Figure 4. UV to GATE Timing
50mV
1V
100mV
GATE
SENSE
VEE
tPHLSENSE
Figure 5. SENSE to GATE Timing
DRAIN
PWRGD
VPWRGD - VDRAIN = 0V
1.8V
VEE
DRAIN
1V
VEE
1.8V
0V
tPLHPG
1V
1.4V
tPHLPG
1V
1.4V
tPHLPG
1V
PWRGD
DRAIN
Figure 6. DRAIN to PWRGD/PWRGD Timing
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 7
Detailed Description
The MAX5948A/MAX5948B are integrated hot-swap
controllers for -48V power systems. They allow circuit
boards to be safely hot plugged into a live backplane
without causing a glitch on the power-supply rail. When
circuit boards are inserted into a live backplane, the
bypass capacitors at the input of the board’s power
module or switching power supply can draw large
inrush currents as they charge. The inrush currents can
cause glitches on the system power-supply rail and
damage components on the board.
The MAX5948A/MAX5948B provide a controlled turn-on
to circuit cards preventing glitches on the power-sup-
ply rail and damage to board connectors and compo-
nents. Both the MAX5948A and MAX5948B provide
undervoltage, overvoltage, and overcurrent protection.
The MAX5948A/MAX5948B ensure the input voltage is
stable and within tolerance before applying power to
the load.
Board Insertion
Figure 6a shows a typical hot-swap circuit for -48V sys-
tems. When the circuit board first makes contact with the
backplane, the DRAIN to GATE capacitance (Cgd) of Q1
pulls up the GATE voltage to roughly I(VEE x Cgd) /
(Cgd + Cgs)I. The MAX5948_ features an internal
dynamic clamp between GATE and VEE to keep the
gate-to-source voltage of Q1 low during hot insertion,
preventing Q1 from passing an uncontrolled current to
the load. For most applications, the internal clamp
between GATE and VEE of the MAX5948A/MAX5948B
eliminates the need for an external gate-to-source
capacitor. Resistor R3 limits the current into the clamp
circuitry during card insertion.
Pin Description
PIN
MAX5948A MAX5948B NAME FUNCTION
1—PWRGD
Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced
to VEE. PWRGD is low when VDRAIN - VEE ≤ VPG, indicating a power-good condition.
PWRGD is open drain otherwise.
— 1 PWRGD
Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced
to DRAIN. PWRGD is in a high-impedance state when VDRAIN - VEE ≤ VPG, indicating a
power-good condition. PWRGD is pulled low to DRAIN otherwise.
22OV
Input Pin for Overvoltage Detection. OV is referenced to VEE. When OV is pulled above
VOVH voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the
OV pin voltage reduces to VOVL.
33UV
Input Pin for Undervoltage Detection. UV is referenced to VEE. When UV is pulled above
VUVH voltage, the GATE is enabled. When UV is pulled below VUVL, GATE is pulled low.
UV is also used to reset the circuit breaker after a fault condition. To reset the circuit
breaker, pull UV below VUVL.
44V
EE Device Negative Power-Supply Input. Connect to the negative power-supply rail.
5 5 SENSE
Current-Sense Voltage Input. Connect to an external sense resistor and the external
MOSFET source. The voltage drop across the external sense resistor is monitored to detect
overcurrent or short-circuit fault conditions. Connect SENSE to VEE to disable the circuit-
breaker feature.
6 6 GATE Gate-Drive Output. Connect to gate of the external n-channel MOSFET.
7 7 DRAIN Output-Voltage Sense Input. Connect to the output-voltage node (drain of external
n-channel MOSFET).
88V
DD Positive Power-Supply Rail Input. This is the power ground in the negative-supply voltage
system. Connect to the most positive potential of the power-supply inputs.
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
8 _______________________________________________________________________________________
Power-Supply Ramping
The MAX5948A/MAX5948B can reside either on the
backplane or the removable circuit board (Figure 6a).
Power is delivered to the load by placing an external
n-channel MOSFET pass transistor in the power-
supply path.
After the circuit board is inserted into the backplane and
the supply voltage at VEE is stable and within the under-
voltage and overvoltage tolerance, the MAX5948A/
MAX5948B turn on Q1. The MAX5948A/MAX5948B grad-
ually turn on the external MOSFET by charging the gate
of Q1 with a 45µA current source. Capacitor C2 provides
a feedback signal to accurately limit the inrush current.
The inrush current can be calculated:
IINRUSH = (IPU x CL)/C2
where CLis the total load capacitance, C3 + C4, and
IPU is the MAX5948_ gate pullup current.
Figure 6b shows the inrush current waveform. The cur-
rent through C2 controls the GATE voltage. At the end
of the DRAIN ramp, the GATE voltage is charged to its
final value. The GATE-to-SENSE clamp limits the maxi-
mum VGS to about 18V under any condition.
Board Removal
If the card is removed from a live backplane, the output
capacitor on the card may not be immediately discharged.
While the output capacitor is discharging, the MAX5948_
continues to operate as if the input supply were still con-
nected because the output capacitor temporarily supplies
operating current to the IC. If the circuit is connected as in
Figure 7a, the voltage at the UV pin falls below the UVLO
detect threshold, and the MAX5948_ turns off the external
MOSFET. If R4 in the circuit is connected directly to the -
48V return, the external MOSFET remains on until the
capacitor is discharged sufficiently to drop the UV pin volt-
age to the UVLO detect threshold.
In either case, when the MOSFET is turned off, the output
capacitor continues to discharge by the IC supply current
IDD. The IDD flows into the IC at the VDD terminal, out at the
VEE terminal, and back to the capacitor through the sub-
strate diode of the external MOSFET. There is also a paral-
lel current path between the VEE and DRAIN terminals
through multiple internal ESD-protection diodes. The pro-
tection circuit built into the IC allows the DRAIN terminal
voltage to drop below that of the VEE terminal so long as
the absolute maximum allowed DRAIN terminal current
(-100mA) is not exceeded. As IDD is only 2mA maximum,
this limiting current will not even be approached.
LOGIC
AND
GATE DRIVE
VCC AND
REFERENCE
GENERATOR
REF
VCC
REF
VPG
VEE
50mV
VDD
UV
OV
VEE SENSE GATE DRAIN
PWRGD
PWRGD
MAX5948A
MAX5948B
OUTPUT
DRIVE
Block Diagram
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
_______________________________________________________________________________________ 9
Electronic Circuit Breaker
The MAX5948 provides a circuit-breaker feature that
protects against excessive load current and short-cir-
cuit conditions. The load current is monitored by sens-
ing the voltage across an external sense resistor
connected between VEE and SENSE.
If the voltage between VEE and SENSE exceeds the
current-limit trip voltage (VCB) for a period of
tPHLSENSE, the electronic circuit breaker will trip, caus-
ing the MAX5948A/MAX5948B to turn off the external
MOSFET as shown in Figure 8.
After an overcurrent fault condition, the circuit breaker
can be reset by pulling the UV pin low and then pulling
UV high or by cycling power to the MAX5948A/
MAX5948B.
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5948B
-48V RTN
-48V
R4
562kΩ
1%
R5
9.09kΩ
1%
R6
10kΩ
1%
R1
0.02Ω
5%
R3
18kΩ
5%
R2
10Ω
5%
C1
150nF
25V
Q1
IRF530
C2
3.3nF
100V
GATE IN
VICOR
VI-J3D-CY
VIN+
VIN-
C4
100µF
100V
C3
0.1µF
100V
*
-48V RTN
(SHORT PIN)
*DIODES INC. SMAT70A.
Figure 7a. Inrush Control Circuitry
GATE - VEE
10V/div
VEE
50V/div
DRAIN
50V/div
INRUSH
CURRENT
1A/div
4ms/div
CONTACT
BOUNCE
Figure 7b. Input Inrush Current
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
10 ______________________________________________________________________________________
If more than 3µs (typ) deglitch time (tPHLSENSE) is
needed to prevent spurious shutdown due to load cur-
rent spikes or noise, a simple lowpass filter can be
used between the SENSE and VEE pins as shown in
Figure 9. Resistor R7 and capacitor C3 slow down the
response of the circuit breaker to filter momentary
glitches in the SENSE voltage. The additional delay
time can be estimated with the following equation:
where Ifis the current in fault condition, IIis the initial
current before the fault, and ICB is the circuit-breaker
trip current (ICB = VCB/R1). Alternatively, the corre-
sponding voltages across the sense resistor (Vf, VI, and
VCB) may be used in the equation as shown. The
SENSE pin of the MAX5948A/MAX5948B sources very
little current (0.02µA typ), so the addition of resistor R7
will introduce very little error in the circuit-breaker trip
voltage. For example, a 10kΩresistor for R7 will only
cause a 200µV offset.
Example: A system has a 1A nominal load current and
a 20mΩsense resistor. The circuit-breaker delay needs
to be increased to 50µs in response to a load current
step to 5A. The circuit-breaker trip current is
50mV/20mΩ= 2.5A. Solving for R7 x C3 in the equation
above yields a desired time constant of 100µs. This can
be achieved with R7 = 100Ωand C3 = 1µF.
tRCIn
VV
VV
RCInII
II
cbdly fI
fCB
fI
fCB
=×× −
−
⎛
⎝
⎜⎞
⎠
⎟
=×× −
−
⎛
⎝
⎜⎞
⎠
⎟
73
73
GATE - VEE
5V/div
VEE
50V/div
INRUSH
CURRENT
2A/div
4ms/div
CONTACT
BOUNCE
Figure 8. Startup Into a Short Circuit
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5948A
-48V RTN
-48V
R4
562kΩ
1%
R5
9.09kΩ
1%
R6
10kΩ
1%
R1
0.02Ω
5%
R3
18kΩ
5%
R2
10Ω
5%
C1
150nF
25V
Q1
IRF530
C2
3.3nF
100V
C4
100µF
100V
*
-48V RTN
(SHORT PIN)
*DIODES INC. SMAT70A.
C3
R7
Figure 9. Extending the Short-Circuit Protection Delay
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 11
In the event of a short circuit at the output, the input
supply may dip below the UV threshold, resetting the
circuit breaker. The MAX5948 cycles ON and OFF until
the short is removed, which can be minimized by creat-
ing a deglitching delay at the UV pin with a capacitor
from UV to VEE. This allows the input supply to recover
before the UV pin resets the circuit breaker.
Figure 10 shows a circuit that automatically resets the
circuit breaker after a current fault. Transistors Q2 and
Q3 along with C4, D1, R7, and R8 form a programma-
ble one-shot circuit. In normal operation, the GATE pin
is pulled high and Q3 is turned on, pulling node 2 to
VEE. Resistor R8 turns off Q2. When a short occurs, the
GATE pin is pulled low and Q3 turns off. Node 2 starts
to charge C4 and Q2 turns on, pulling the UV pin low
and resetting the circuit breaker. The instant C4 is fully
charged, R8 turns off Q2, UV goes high and the GATE
starts to ramp up. Q3 turns back on and pulls node 2
back to VEE. Diode D1 clamps node 3 at one diode
drop below VEE. The duty cycle is set to 10% to prevent
Q1 from overheating.
Undervoltage and Overvoltage Protection
The UV and OV pins can be used to detect undervolt-
age and overvoltage conditions. The UV and OV pins
are internally connected to analog comparators with
20mV of hysteresis. When the UV voltage falls below its
threshold or the OV voltage rises above its threshold,
the GATE pin is immediately pulled low. The GATE pin
is held low until UV goes high and OV is low indicating
that the input supply voltage is within specification.
The UV pin is also used to reset the circuit breaker after
a fault condition has occurred. The UV pin can be
pulled below VUVL to reset the circuit breaker.
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5948A
-48V RTN
-48V RTN
(SHORT PIN)
*
-48V
*DIODES INC. SMAT70A.
R4
562kΩ
1%
R8
510kΩ
5%
R5
19.1kΩ
1%
R6
562kΩ
1%
R7
1MΩ
5%
R9
10kΩ
1%
R1
0.02Ω
5%
R3
18kΩ
5%
R2
10Ω
5%
C1
150nF
25V
C4
1µF
100V
Q1
IRF530
D1
1N4148
Q2
2N2222
Q3
ZVN3310
C2
3.3nF
100V
C3
100µF
100V GATE
2V/div
NODE2
50V/div
1s/div
NODE 2
Figure 10. Automatic Restart After Current Fault
MAX5948A/MAX5948B
Figure 11a shows how to program the undervoltage
and overvoltage trip thresholds using three resistors.
With R4 = 562kΩ, R5 = 9.09kΩ, and R6 = 10kΩ, the
undervoltage threshold is set to 37.2V (with a 37.8V
release from undervoltage) and the overvoltage is set
to 71.1V (with a 69.9V release from overvoltage).
More hysteresis can be added to the undervoltage
lockout with the circuit shown in Figure 11b. Resistor
R3 connected between GATE and UV lowers the sup-
ply undervoltage lockout threshold (supply voltage
decreasing) to:
where VUVL is typically 1.223V. The supply voltage to
release from undervoltage lockout (supply voltage
increasing) is:
where VUVH is typically 1.243V. The supply undervolt-
age lockout hysteresis is the difference, or: where VUVHY is typically 20mV.
VV
R R RR RR
RR VR
R
UV HYS UVHY GATE, =×+×+×
×
⎛
⎝
⎜⎞
⎠
⎟+×
⎛
⎝
⎜
⎞
⎠
⎟
231312
23
1
3
∆
VV
RRRRRR
RR
UV LH UVH,=×+×+×
×
⎛
⎝
⎜⎞
⎠
⎟
231312
23
VV
R R RR RR
RR VR
R
UV HL UVL GATE,=×+×+×
×
⎛
⎝
⎜⎞
⎠
⎟−×
⎛
⎝
⎜⎞
⎠
⎟
231312
23
1
3
∆
-48V Hot-Swap Controllers
with External RSENSE
12 ______________________________________________________________________________________
VEE
VDD
OV
UV
MAX5948A
MAX5948B
-48V RTN
-48V
VUV = 1.223 R4 + R5 + R6
R5 + R6
R4
R5
R6
-48V RTN
(SHORT PIN)
VOV = 1.223 R4 + R5 + R6
R6
Figure 11a. Undervoltage and Overvoltage Sensing
VEE SENSE GATE
VDD
UV
OV
MAX5948
-48V RTN
= 37.6VUV
-48V RTN
(SHORT PIN)
*
-48V
*DIODES INC. SMAT70A.
R1
562kΩ
1%
R4
506kΩ
1%
R2
16.9kΩ
1%
R5
8.87kΩ
1%
R7
0.02Ω
5%
R6
10Ω
5%
C1
150nF
25V
Q1
IRF530
R3
1.62MΩ
1%
= 43VUV
= 71VOV
Figure 11b. Programmable Hysteresis For Undervoltage
A separate resistor-divider must be used for the over-
voltage lockout setting. The supply overvoltage lockout
threshold is:
where VOVH is typically 1.223V.
Using R1 = 562kΩ, R2 = 16.9kΩ, R3 = 1.62MΩ, R4 =
506kΩ, R5 = 8.87kΩ, and the typical value of VGATE =
13.5V results in the following thresholds:
VUV,HL = 37.6V
VUV,LH = 43V
(with hysteresis now increased to 5.4V), and VOV = 71V
(with 1.2V hysteresis).
PWRGD
/PWRGD Output
The PWRGD (PWRGD) output can be used directly to
enable a power module after hot insertion. The
MAX5948A (PWRGD) can be used to enable modules
with an active-low enable input (Figure 13), while the
MAX5948B (PWRGD) is used to enable modules with
an active-high enable input (Figure 12).
The PWRGD signal is referenced to the DRAIN termi-
nal, which is the negative supply of the power module.
The PWRGD signal is referenced to VEE.
When the DRAIN voltage of the MAX5948A is high with
respect to VEE, the internal pulldown MOSFET Q2 is off
and the PWRGD pin is in a high-impedance state
(Figure 13). PWRGD is pulled high by the module’s
internal pullup current source, turning the module off.
When the DRAIN voltage drops below VPG, Q2 turns on
and PWRGD pulls low, enabling the module.
The PWRGD signal can also be used to turn on an LED
or optoisolator to indicate that the power is good
(Figure 13) (see the
Component Selection Procedure
section).
VV RR
R
OV OVH
=+
⎛
⎝
⎜⎞
⎠
⎟
45
5
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 13
PWRGD
I1
VEE
VPG
-48V
R1
R2
C1
Q1
R3 C2
MAX5948B
VIN+
VIN-
C4
Q2
Q3
VOUT+
VOUT-
ON/OFF
VICOR
VI-J3D-CY
DRAIN
GATESENSEVEE
VDD
R4
R5
R6
*
*DIODES INC. SMAT70A.
-48V RTN
-48V RTN
(SHORT PIN)
UV
OV
Figure 12. Active-High Enable Module
MAX5948A/MAX5948B
When the DRAIN voltage of the MAX5948B is high with
respect to VEE (Figure 12), the internal MOSFET Q3 is
turned off so that I1 and the internal MOSFET Q2 clamp
the PWRGD pin to the DRAIN pin. MOSFET Q2 sinks
the module’s pullup current, and the module turns off.
When the DRAIN voltage drops below VPG, MOSFET Q3
turns on, shorting I1 to VEE and turning Q2 off. The
pullup current in the module pulls PWRGD high,
enabling the module.
GATE Voltage Regulation
GATE goes high when the following startup conditions
are met: UV is high, OV is low, the supply voltage is
above VUV,LH, and (VSENSE - VEE) is less than 50mV.
GATE is pulled up with a 45µA current source and is
regulated at 13.5V above VEE. The MAX5948A/
MAX5948B include an internal clamp that ensures the
GATE voltage of the external MOSFET never exceeds
18V. During a fast-rising VDD, the clamp also keeps the
GATE and SENSE potentials as close as possible to
prevent the FET from accidentally turning on. When a
fault condition is detected, GATE is pulled low with a
50mA current.
DRAIN Pin Protection
The MAX5948’s DRAIN pin withstands negative volt-
ages (referenced to VEE); no external diode is required.
When the -48V backplane shorts to ground and VEE
becomes 0V, the DRAIN pin is held at less than 1.5V
(sum of Q1’s body diode and voltage drop across R1)
below VEE due to the storage capacitor C3 (Figure 13).
The -1.5V results in a 50mA reverse DRAIN current,
which is within the capability of the MAX5948. A design
with R1 larger than 0.1Ωmay require a resistor in series
with the DRAIN pin to avoid exceeding the 50mA drain
current maximum.
-48V Hot-Swap Controllers
with External RSENSE
14 ______________________________________________________________________________________
PWRGD
VEE
VPG
-48V
R1
R2
C1
Q1
R3 C2
MAX5948A
VIN+
VIN-
C4
VOUT+
VOUT-
ON/OFF
ACTIVE-HIGH
ENABLE MODULE
DRAIN
GATESENSEVEE
VDD
R4
R5
R6
*
*DIODES INC. SMAT70A.
-48V RTN
-48V RTN
(SHORT PIN)
UV
OV
Q2
Figure 13. Active-Low Enable Module
Applications Information
(Refer to the
Typical Operating Circuit.
)
Sense Resistor
The circuit-breaker threshold is set to 50mV (typically).
Select a sense resistor that causes a drop equal to or
above the current-limit threshold at a current level above
the maximum normal operating current. Typically, set the
overload current to 1.5 to 2.0 times the nominal load cur-
rent plus the load-capacitance charging current during
startup. Choose the sense resistor power rating to be
greater than (VCB)2/ RSENSE.
Component Selection Procedure
• Determine load capacitance:
CL= C3 + C4 + module input capacitance
• Determine load current, ILOAD.
• Select circuit-breaker current, for example:
ICB = 2 x ILOAD
• Calculate RSENSE:
Realize that ICB varies ±20% due to trip-voltage
tolerance.
• Set allowable inrush current:
• Determine value of C2:
• Calculate value of C1:
CCCx
VV
V
gd IN MAX GS TH
GS TH
12
=+ −
⎛
⎝
⎜⎞
⎠
⎟
()
() ()
()
CAxC
I
L
INRUSH
2
45
=µ
Ix
mV
RIor
II xI
INRUSH SENSE LOAD
INRUSH LOAD CB MIN
≤−
+≤
08 40
08
.
.()
RmV
I
SENSE CB
=50
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 15
VEE SENSE GATE DRAIN
VDD
OV
UV
PWRGD
MAX5948A
GND
(SHORT PIN)
-48V
R4
562kΩ
1%
R5
9.09kΩ
1%
R6
10kΩ
1%
R1
0.02Ω
5%
R3
18kΩ
5%
R2
10Ω
5%
C1
150nF
25V
Q1
IRF530
C2
3.3nF
100V
C3
100µF
100V
*
GND
*DIODES INC. SMAT70A.
MOC207
R7
51kΩ
5%
PWRGD
Figure 14. Using PWRGD to Drive an Optoisolator
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
16 ______________________________________________________________________________________
VEE SENSE GATE DRAIN
VDD
OV
5V
UV
PWRGD
MAX5948A
GND
(SHORT PIN)
-48V
R4
562kΩ
1%
R5
9.09kΩ
1%
R6
10kΩ
1%
R1
0.02Ω
5%
R3
18kΩ
5%
R2
10Ω
5%
C1
150nF
25V
Q1
IRF530
C2
3.3nF
100V
SENSE-
SENSE+
TRIM
ON/OFF
LUCENT
JW050A1-E
VIN+
VIN-
VOUT+
VOUT-
C4
100µF
100V
C5
100µF
16V
C3
0.1µF
100V
*
GND
*DIODES INC. SMAT70A.
Typical Operating Circuit
• Determine value of R3:
• Set R2 = 10Ω.
• If an optocoupler is utilized as in Figure 14, deter-
mine the LED series resistor:
Although the suggested optocoupler is not specified for
operation below 5mA, its performance is adequate for
36V temporary low-line voltage where LED current
would then be ≈2.2mA to 3.7mA. If R7 is set as high as
51kΩ, optocoupler operation should be verified over
the expected temperature and input voltage range to
ensure suitable operation when LED current ≈0.9mA for
48V input and ≈0.7mA for 36V input.
If input transients are expected to momentarily raise the
input voltage to >100V, select an input transient-volt-
age-suppression diode (TVS) to limit maximum voltage
on the MAX5948 to less than 100V. A suitable device is
the Diodes Inc. SMAT70A telecom-specific TVS.
Select Q1 to meet supply voltage, load current, efficien-
cy, and Q1 package power-dissipation requirements:
BVDSS ≥100V
ID(ON) ≥3x I
LOAD
DPAK, D2PAK, or TO-220AB
Choose the lowest practical RDS(ON) within budget
constraints. MOSFETs with values from 14mΩto
540mΩare available at 100V breakdown.
Ensure that the temperature rise of Q1 junction is not
excessive at normal load current for the package select-
ed. Ensure that ICB current during voltage transients
does not exceed allowable transient-safe operating-area
limitations. This is determined from the SOA and tran-
sient-thermal-resistance curves in the Q1 manufacturer’s
data sheet.
Example 1:
ILOAD = 2.5A, efficiency = 98%, then VDS = 0.96V is
acceptable, or RDS(ON) ≤384mΩat operating temper-
ature is acceptable. An IRL520NS 100V nMOS with
RDS(ON) ≤180mΩand ID(ON) = 10A is available in
D2PAK. (A Vishay Siliconix SUD40N10-25 100V nMOS
with RDS(ON) ≤25mΩand ID(ON) = 40A is available in
DPAK, but may be more costly because of a larger
die size).
RVV
mA I mA
IN NOMINAL
LED
72
35
()
=−
≤≤
Rs
C
32
150
≤µ
Using the IRL520NS, VDS ≤0.625V even at +80°C so
efficiency ≥98.6% at 80°C. PD≤1.56W and junction
temperature rise above case temperature would be 5°C
due to the package θJC = 3.1°C/W thermal resistance.
Of course, using the SUD40N10-25 would yield an effi-
ciency greater than 99.8% to compensate for the
increased cost.
If ICB is set to twice ILOAD, or 5A, VDS momentarily dou-
bles to ≤1.25V. If COUT = 4000µF, transient-line input
voltage is ∆36V, the 5A charging-current pulse is:
Entering the data sheet transient-thermal-resistance
curves at 1ms provides a θJC = 0.9°C/W. PD= 6.25W,
so ∆tJC = 5.6°C. Clearly, this is not a problem.
Example 2:
ILOAD = 10A, efficiency = 98%, allowing VDS = 0.96V
but RDS(ON) ≤96mΩ. An IRF530 in a D2PAK exhibits
RDS(ON) ≤90mΩat +25°C and ≤135mΩat +80°C.
Power dissipation is 9.6W at +25°C or 14.4W at +80°C.
Junction-to-case thermal resistance is 1.9W/°C, so the
junction temperature rise would be approximately 5°C
above the +25°C case temperature. For higher efficien-
cy, consider IRL540NS with RDS(ON) ≤44mΩ. This
allows η= 99%, PD≤4.4W, and TJC = +4°C (θJC =
1.1°C/W) at +25°C.
Thermal calculations for the transient condition yield
ICB = 20A, VDS = 1.8V, t = 0.5ms, transient θJC =
0.12°C/W, PD= 36W and ∆tJC = 4.3°C.
tFx V
Ams==
4000 1 25
51
µ.
MAX5948A/MAX5948B
-48V Hot-Swap Controllers
with External RSENSE
______________________________________________________________________________________ 17
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
8 SO S8+5 21-0041 90-0096
MAX5948A/MAX5984B
-48V Hot-Swap Controllers
with External RSENSE
MAX5948A/MAX5948B
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/04 Initial release —
1 8/11 Updated Ordering Information, Absolute Maximum Ratings, Electrical
Characteristics, and Package Information.1, 2, 3, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
18
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