eroflex Circuit Technology - Advanced Multichip Modules © SCD1662 REV B 9/5/01
General Description
The ACT–E128K32 is a high
speed, 4 megabit, CMOS
EEPROM multichip module
(MCM) designed for full
temperature range military,
space, or high reliability
applications. The MCM can be
organized as a 256K x 16 bits
or 512K x 8 bits device and is
input and output CMOS and
TTL compatible. Writing is
executed when the write enable
(WE) and chip enable (CE)
inputs are low and output
enable (OE) is high. Reading is
accomplished when WE is high
and CE and OE are both low.
Access times grades of
120, 140, 150, 200, 250 & 300ns
are standard.
The ACT–E128K32 is
packaged in a choice of
hermetically sealed co-fired
ceramic packages, a 66 pin,
1.08" sq PGA or a 68 lead, .88"
sq gullwing CQFP. The device
operates over the temperature
range of -55°C to +125°C and
military environment.
■ 4 Low Power 128K x 8 EEPROM Die in One MCM
Package
■ Organized as 128K x 32
● User Configurable to 256K x 16 or 512K x 8
■ CMOS and TTL Compatible Inputs and Outputs
■ Access Times of 120,140,150, 200, 250& 300ns
■ +5V ±10% Supply
■ Automatic Page Write Operation
■ Page Write Cycle Time: 10ms Max
■ Data Retention Ten Years Minimum
■ Low Power CMOS
■ Data Polling for End of Write Detection
■ Industry Standard Pinouts
■ Packaging – Hermetic Ceramic
● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,
Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
● 68 Lead, .88" x .88" x .200" Dual-Cavity Small
Outline Gull Wing, Aeroflex code# "F2"
(Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
■ MIL-PRF-38534 Compliant MCMs Available
■ Hardware and Software Data Protection
■ Internal Decoupling Capacitors for Low Noise
Operation
■ Commercial, Industrial and Military Temperature
Ranges
■ SMD# 5962–94585 Released (P7 & F2)
Features
128Kx8 128Kx8 128Kx8
CE4
OE
A0 – A16
I/O0-7 I/O8-15 I/O16-23 I/O24-31
8888
CE3WE4
WE3
WE2
WE1CE1CE2
128Kx8
Pin Description
I/O0-31 Data I/O
A0–16 Address Inputs
WE1-4 Write Enables
OE Output Enable
CE1-4 Chip Enables
VCC Power Supply
GND Ground
Block Diagram – PGA Type Package (P3,P7) & CQFP (F2)
ACT–E128K32 High Speed
4 Megabit EEPROM Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
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Aeroflex Circuit Technology SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
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Absolute Maximum Ratings
Parameter Symbol Range Units
Operating Temperature TC-55 to +125 °C
Storage Temperature Range TSTG -65 to +150 °C
All Input Voltages with respect to Ground VG-0.6 to +6.25 V
All Output Voltages with respect to Ground - -0.6 to VCC+0.6 V
Voltage on OE and A9 with respect to Ground - -0.6 to +13.5 V
NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol Parameter Minimum Maximum Units
VCC Power Supply Voltage +4.5 +5.5 V
VIH Input High Voltage +2.0 VCC + 0.3 V
VIL Input Low Voltage -0.5 +0.8 V
TCCase Operating Temperature (Military) -55 +125 °C
Capacitance
(VIN = 0V, f = 1MHz, TC = 25°C)
Symbol Parameter Maximum Units
CAD A0 – A16 Capacitance 50 pF
COE Output Enable Capacitance 50 pF
CWE(1-4) Write Enable Capacitance 20 pF
CCE(1-4) Chip Enable Capacitance 20 pF
CI/OI/O0 – I/O31 Capacitance 20 pF
DC Characteristics
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C, unless otherwise specified)
Parameter Sym Conditions Minimum Maximum Units
Input Leakage Current ILI VCC = 5.5V, VIN = GND to VCC 10 µA
Output Leakage Current ILOX32 CE = OE = VIH, V
OUT = GND to VCC 10 µA
Operating Supply Current x 32 Mode ICCX32 CE = VIL, OE = VIH, f = 5Mhz 250 mA
Operating Supply Current ISB CE = VIH, OE = VIH, f = 5Mhz 5mA
Output Low Voltage VOL IOL = +2.1mA, VCC = 4.5V 0.45 V
Output High Voltage VOH IOH = –400µA, VCC = 4.5V 2.4 V
Truth Table
CE OE WE Mode Data I/O
H X X Standby High Z
L L H Read Data Out
L H L Write Data In
X H X Out Disable High Z
XXH Write
Inhibit
-
XLX -
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AC Write Characteristics
(VCC = 5V, VSS = 0V, TC = -55°C to +125°C)
Parameter Symbol Min Max Units
Write Cycle Time tWC 10 ms
Address Set-up Time tAS 10 ns
Write Pulse Width (WE or CE)tWP 150 ns
Chip Enable Set-up Time tCE 0ns
Address Hold Time tAH 100 ns
Data Hold Time tDH 10 ns
Chip Enable Hold Time tCEH 0ns
Data Set-up Time tDS 100 ns
Output Enable Set-up Time tOES 10 ns
Output Enable Hold Time tOEH 10 ns
AC Read Characteristics
(VCC = 5V, VSS = 0V, TC = -55°C to +125°C)
Read Cycle Parameter Symbol –120
Min Max
–140
Min Max
–150
Min Max
–200
Min Max
–250
Min Max
–300
Min Max Units
Read Cycle Time tRC 120 140 150 200 250 300 ns
Address Access Time tACC 120 140 150 200 250 300 ns
Chip Enable Access Time tACE 120 140 150 200 250 300 ns
Output Hold From Address Change,
OE or CE tOH 000000 ns
Output Enable to Output Valid tOE 055055055055085085 ns
Chip Enable or OE to High Z Output tDF 70 70 70 70 70 70 ns
Page Write Characteristics
(VCC = 5V, VSS = 0V, TC = -55°C to +125°C)
Parameter Symbol Minimum Maximum Units
Write Cycle Time tWC 10 ms
Address Set-up Time tAS 10 ns
Address Hold Time , See Note 1 tAH 100 ns
Data Set-up Time tDS 100 ns
Data Hold Time tDH 10 ns
Write Pulse Width tWP 150 ns
Byte Load Cycle Time tBLC 150 µs
Write Pulse Width High tWPH 50 ns
Note 1 – Page Address must remain valid for duration of write cycle.
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Device Operation
The ACT-E128K32 is a high-performance
Electrically Erasable and Programmable
Read Only Memory. It is composed of four 1
megabit memory chips and is organized as
131,072 by 32 bits. The device offers access
times of 120 to 300ns with power dissipation
of 1.375W. When the device is deselected,
the CMOS standby current is less than 5 mA.
The ACT-E128K32 is accessed like a Static
RAM for the read or write cycle without the
need for external components. The device
contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously.
During a write cycle, the address and 1 to
128 bytes of data are internally latched,
freeing the address and data bus for other
operations. Following the initiation of a write
cycle, the device will automatically write the
latched data using an internal control timer.
The end of a write cycle can be detected by
DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a
read or write can begin.
Aeroflex’s ACT-E128K32 has additional
features to ensure high quality and
manufacturability. The device utilizes internal
error correction for extended endurance and
improved data retention characteristics. An
optional software data protection mechanism
is available to guard against inadvertent
writes.
WRITE
A write cycle is initiated when OE is high and
a low pulse is on WE or CE with CE or WE
low. The address is latched on the falling
edge of CE or WE whichever occurs last.
The data is latched by the rising edge of CE
or WE, whichever occurs first. A byte write
operation will automatically continue to
completion.
WRITE CYCLE TIMING
Figures 2 and 3 show the write cycle timing
relationships. A write cycle begins with
address application, write enable and chip
enable. Chip enable is accomplished by
placing the CE line low. Write enable
consists of setting the WE line low. The write
cycle begins when the last of either CE or
WE goes low.
The WE line transition from high to low also
initiates an internal delay timer to permit
page mode operation. Each subsequent WE
transition from high to low that occurs before
the completion of the tBLC time out will restart
the timer from zero. The operation of the
timer is the same as a retriggable one-shot.
READ
The ACT-E128K32 stores data at the
memory location determined by the address
pins. When CE and OE are low and WE is
high, this data is present on the outputs.
When CE and OE are high, the outputs are in
a high impedance state. This two line control
prevents bus contention.
DATA POLLING
The ACT-E128K32 offers a data polling
feature which allows a faster method of
writing to the device. Figure 5 shows the
timing diagram for this function. During a
byte or page write cycle, an attempted read
of the last byte written will result in the
complement of the written data on I/O7 (For
each Chip). Once the write cycle has been
completed, true data is valid on all outputs
and the next cycle may begin. Data polling
may begin at any time during the write cycle.
PAGE WRITE OPERATION
The ACT-E128K32 has a page write
operation that allows one to 128 bytes of data
to be written into the device and
consecutively loads during the internal
programming period. Successive bytes may
be loaded in the same manner after the first
data byte has been loaded. An internal timer
begins a time out operation at each write
cycle. If another write cycle is completed
within tBLC or less, a new time out period
begins. Each write cycle restarts the delay
period. The write cycles can be continued as
long as the interval is less than the time out
period.
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The usual procedure is to increment the least
significant address lines from A0 through A6
at each write cycle. In this manner a page of
up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning
the relatively long interval programming
cycle.
After the tBLC time out is completed, the
EEPROM begins an internal write cycle.
During this cycle the entire page will be
written at the same time. The internal
programming cycle is the same regardless of
the number of bytes accessed.
SOFTWARE DATA PROTECTION
A software write protection feature may be
enabled or disabled by the user. When
shipped by Aeroflex Microelectronics, the
ACT-E128K32 has the feature disabled.
Write access to the device is unrestricted.
To enable software write protection, the user
writes three access code bytes to three
special internal locations. Once write
protection has been enabled, each write to
the EEPROM must use the same three byte
write sequence to permit writing. The write
protection feature can be disabled by a six
byte write sequence of specific data to
specific locations. Power transitions will not
reset the software write protection.
Each 128K byte block of the EEPROM has
independent write protection. One or more
blocks may be enabled and the rest disabled
in any combination. The software write
protection guards against inadvertent writes
during power transitions, or unauthorized
modification using a PROM programmer.
HARDWARE DATA PROTECTION
These features protect against inadvertent
writes to the ACT-E128K32. These are
included to improve reliability during normal
operation:
A) Vcc Sense
While below 3.8V typical write cycles
are inhibited.
B) Write inhibiting
Holding OE low and either CE or WE
high inhibits write cycles.
C) Noise filter
Pulses of <10ns (TYP) on WE or CE
will not initiate a write cycle.
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Data Polling Characteristics
(VCC = 5V, VSS = 0V, TC = -55°C to +125°C)
Parameter Symbol Min Max Units
Data Hold Time tDH 10 ns
OE Hold Time tOEH 10 ns
OE to Output Valid tOE 55 ns
Write Recovery Time tWR 0ns
Guaranteed. But not tested.
IOL Parameter Typical Units
Input Pulse Level 0 – 3.0 V
Input Rise and Fall 5 ns
Input and Output Timing Reference Level 1.5 V
Output Lead Capacitance 50 pF
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO=75Ω. 4) VZ is typically the
midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.
IOH
To Device Under Test VZ ~ 1.5 V
Current Source
Current Source
CL =
50 pF
Figure 1
AC Test Circuit
Write Waveforms – WE Controlled
Figure 2
DATA IN
ADDRESS
CE
WE
OE
tAS
tOES
tWP
tCE
tOEH
tCEH
tWPH
tDH
tDS
tAH
tWC
(Bipolar Supply)
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Write Waveforms – CE Controlled
Figure 3
DATA IN
ADDRESS
WE
CE
OE
tAS
tOES
tWP
tCE
tOEH
tCEH
tWPH
tDH
tDS
tAH
tWC
Notes:
1. OE may be delayed up to tACS – tOE after the falling edge of CE without impact on tOE or by tACC – tOE
after an address change without impact on tACC.
Read Waveforms
Figure 4
OE
CE
ADDRESS
OUTPUT
tACE
tOE
tACC
tDF
tOH
Output
High Z
Address Valid
Valid
tRC
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Figure 5
Data Polling Waveform
tOEH
tOE
tDH tWR
CE1-4
WE1-4
I/O7
OE
ADDRESS
High Z
ANANANANAN
CEX
tWP tWPH tBLC
tAS
tAH tDH
tDS tWC
OE
WEX
DATA
ADDRESS
Notes:
1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE) after the software codes have been entered.
2. OE must be high when WE and CE are both low.
Valid DATA Byte 127
Figure 6
Page Mode Write Waveforms
Byte 0 Byte 1 Byte 2 Byte 3
Valid ADD
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Figure 7
Software Data
To
Load Data AA
Address 5555
To
Load Data 55
Address 2AAA
To
Load Data A0
Address 5555
To
Load Data XX
Any Address (4)
Writes Enabled (2)
NOTES:
1. Data Format: I/O0 - I/O7 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end ot write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
To
Load Data AA
Address 5555
To
Load Data 55
Address 2AAA
To
Load Data 80
Address 5555
To
Load Data AA
Address 5555 (4)
Exit Data
Protect State (3 )
To
Load Data 55
Address 2AAA
To
Load Data 20
Address 5555
To
Load Data XX
Any Address (4)
Figure 8
Protection Enable Algorithm (1)
To
Load Last Byte
Last Address Enter Data
Protect State
Software Data
Protection Disable Algorithm (1)
To
Load Last Byte
Last Address
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Pin Numbers & Functions
66 Pins — PGA Type Package
Pin # Function Pin # Function Pin # Function Pin # Function
1I/O
818 A12 35 I/O25 52 WE3
2I/O
919 Vcc 36 I/O26 53 CE3
3I/O
10 20 CE137 A654 GND
4A
13 21 NC 38 A755 I/O19
5A
14 22 I/O339 NC 56 I/O31
6A
15 23 I/O15 40 A857 I/O30
7A
16 24 I/O14 41 A958 I/O29
8 NC 25 I/O13 42 I/O16 59 I/O28
9I/O
026 I/O12 43 I/O17 60 A0
10 I/O127 OE 44 I/O18 61 A1
11 I/O228 NC 45 VCC 62 A2
12 WE229 WE146 CE463 I/O23
13 CE230 I/O747 WE464 I/O22
14 GND 31 I/O648 I/O27 65 I/O21
15 I/O11 32 I/O549 A366 I/O20
16 A10 33 I/O450 A4
17 A11 34 I/O24 51 A5
Note: Pins 8, 21, 28 & 39 can be connected to ground by specifing Option "C".
1.085 SQ
1.000
.600
1.000
.100
.020
.016
.100
.180
TYP
1.030
1.040
.160
Pin 56
Pin 66
Pin 11
Pin 1
Bottom View (P7 & P3)
MAX
MAX
"P3" — 1.08" SQ PGA Type (without shoulder) Package
"P7" — 1.08" SQ PGA Type (with shoulder) Package
1.030
1.040
.020
.016
.100
.025
.185
MAX
Side View
(P7)
Side View
(P3)
.050
.180
TYP
.035
All dimensions in inches
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Pin Numbers & Functions
68 Pins — Dual-Cavity CQFP
Pin # Function Pin # Function Pin # Function Pin # Function
1GND18GND35OE52 GND
2CE
319 I/O836 CE253 I/O23
3A
520 I/O937 NC 54 I/O22
4A
421 I/O10 38 WE255 I/O21
5A
322 I/O11 39 WE356 I/O20
6A
223 I/O12 40 WE457 I/O19
7A
124 I/O13 41 NC 58 I/O18
8A
025 I/O14 42 NC 59 I/O17
9 NC 26 I/O15 43 NC 60 I/O16
10 I/O027 Vcc 44 I/O31 61 VCC
11 I/O128 A11 45 I/O30 62 A10
12 I/O229 A12 46 I/O29 63 A9
13 I/O330 A13 47 I/O28 64 A8
14 I/O431 A14 48 I/O27 65 A7
15 I/O532 A15 49 I/O26 66 A6
16 I/O633 A16 50 I/O25 67 WE1
17 I/O734 CE151 I/O24 68 CE4
Top View
All dimensions in inches
Package Outline — Dual-Cavity CQFP "F2"
.015
.990 SQ
±.010
.880 SQ
±.010
.800 REF
.050
.946
±.010
See Detail “A”
Detail “A”
*.200 MAX .010 REF
0°- 7°
.040
0.010 R
.010 ±.005
TYP
±.010
Pin 60
Pin 44
Pin 43Pin 27
Pin 26
Pin 10
Pin 9 Pin 61
*.180 MAX available, call factory for details
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Ordering Information
Model Number DESC Drawing Number Speed Package
ACT-E128K32N-120P7Q 5962-9458506H4X 120ns PGA Type
ACT-E128K32C-120P7Q 5962-9458506H5X 120ns PGA Type
ACT-E128K32N-140P7Q 5962-9458505H4X 140ns PGA Type
ACT-E128K32C-140P7Q 5962-9458505H5X 140ns PGA Type
ACT-E128K32N-150P7Q 5962-9458504H4X 150ns PGA Type
ACT-E128K32C-150P7Q 5962-9458504H5X 150ns PGA Type
ACT-E128K32N-200P7Q 5962-9458503H4X 200ns PGA Type
ACT-E128K32C-200P7Q 5962-9458503H5X 200ns PGA Type
ACT-E128K32N-250P7Q 5962-9458502H4X 250ns PGA Type
ACT-E128K32C-250P7Q 5962-9458502H5X 250ns PGA Type
ACT-E128K32N-300P7Q 5962-9458501H4X 300ns PGA Type
ACT-E128K32C-300P7Q 5962-9458501H5X 300ns PGA Type
ACT-E128K32N-120F2Q 5962-9458506HMX 120ns CQFP
ACT-E128K32N-140F2Q 5962-9458505HMX 140ns CQFP
ACT-E128K32N-150F2Q 5962-9458504HMX 150ns CQFP
ACT-E128K32N-200F2Q 5962-9458503HMX 200ns CQFP
ACT-E128K32N-250F2Q 5962-9458502HMX 250ns CQFP
ACT-E128K32N-300F2Q 5962-9458501HMX 300ns CQFP
P
art
N
um
b
er
B
rea
kd
own
ACT– E 128K 32 N– 200 P7 M
Aeroflex Circuit
Technolo gy
Memory Type
E = EEPROM
Memory Depth
Options
Memory Width, Bits
N = None
C = Connect to GND – Pins 8,21,28,39 (P3 & P7 Pkg only)
Memory Speed, ns
Package Type & Size
Surface Mount Packages Thru-Hole Packages
F2 = .88"SQ 68 Lead Dual-Cavity
CQFP
P3 = 1.085"SQ PGA 66 Pins
without shoulder
P7 = 1.085"SQ PGA 66 Pins
with shoulder
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screening *
Q = MIL-PRF-38534 Compliant / SMD
Screening
* Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
CIRCUIT TECHNOLOGY
