SM5813AP/APT/AF [- EIGHT-TIMES OVERSAMPLING DIGITAL NIPPON PRECISION CIRCUITS INC. FILTER FOR DIGITAL AUDIO mM OVERVIEW The SM5813AP/APT is a high-fidelity eight-times oversampling digital filter LSI for digital audio system, using the molibdenum gate C-MOS process developed solely by NPC. This LSI has a two-channel FIR filter and three types of output modes (16bit/18bit/20bit). Since it has four kinds of system clocks --- 512fs/256fs/384fs/192fs, it can be used for not only CD players but also other audio systems. m FEATURES * FILTER CHARACTERISTICS ITEMS CHARACTERISTICS Pass band. ....., _..., 0 to 0.4535fs Stop band |. .0.5465fs to 7.45358 Pass band ripple Within 0.00005dB Stop band attenuation | Morethan 110dB Linear phase (There is no group delay distortion.) * FILTER STRUCTURE * Free running mode (Jitter-free) Eight-times oversampling * INPUT/OUTPUT Two-channel filters 16 bit serial data input ~ Cascaded three-stage linear phase (2's complement code, MSB first) FIR filters (153+29+17 order) 16/18/20bit serial data output 20 x 22 bit multiplier (2's complement/Complemented offset binary, 25bit accumulator MSB first) Overflow limiter SYSTEM CLOCK Crystal oscillation circuit (512fs/256fs/384fs/192fs) * Power supply voltage: 5V 0.5V * PACKAGE * Molybdenam gate C-MOS process 28-pin DIP, 44-pin QFP m PIN OUT (TOP VIEW) - 28-pin DIP DIN [1 \7 > 287) tRcI BCKI [| l] FSCO CKSL [ 1] BCKO CKDV [ 1] WCKO (NC) ff 2 2 {| DOL xTI [ ol VU [] DOR XTO [ 1] Vpp vs CES Nn HV: ssl Gb ~.W Ss2 SM5813AF CKO | oJ > 1] DG __ Uv ~ SYN [ o\ ] (NC) (Nc) [ > ] (NC) (NC) [ U ] OW18 (NC) [ 4 } OW20 RST f}14 15{] COB NIPPON PRECISION CIRCUITS 441SM5813AP/APT/AF M PACKAGE DIMENSION (UNIT: mm) -28-pin DIP +013 0.05 0.25 * 44-pin QEP O~15 142 NIPPON PRECISION CIRCUITSM BLOCK DIAGRAM Vop Vssi Vesa SM5813AP/APT/AF DIN BCKI moeteestcnteeccceeenee Onna 16 FILTER CALCULATION 20 C) OWi8 OUTPUT INTERFACE ow20 COB Onno OynnrrnnnOpnnnnnneOenneee eee! DG BCKO wcKo DOL DOR M@ FILTER CHARACTERISTICS (THEORITICAL VALUE) Attenuation [dB] CHARACTERISTICS STOP BAND ATTENUATION 20 40 60 80 100 120 0.4535 0.5465 5 6 7 \ 8 [x fs] 7.4535 NIPPON PRECISION CIRCUITS 143SM5813AP/APT/AF PASS BAND RIPPLE 0.00005 } --- na wove eceneceeeneeeeeeeneeneneeee Oly + 0.00005 + Attenuation [dB] [x fs] 0.4535 THE DOMAIN BETWEEN PASS BAND AND STOP BAND 20} 40} 60} 80 100 120 Attenuation [dB} 0.45 0.5 0.5465 0.6 [x fs] 144 NIPPON PRECISION CIRCUITSSM5813 AP/APT/AF mM PIN DESCRIPTION NAME} /O*) DESCRIPTION 1 | 42 |DIN 1 | Serial data input .6)....3. [TE |... | Input for oscillator or external clock input (System clock) 7} 4/XTO 0 | Output for oscillator, No connect when using external clock 816 [Vest fe [Ground 9] 10 |CKO | 0 | Clock output (Same frequency as XTI input clock) 10} 11 |SY 1 | H: Free running mode L: Forced synchronizing mode 294.25 [DG |. Q | Deglitch control clock 21, 1..27.|Vss2 0d. = Ground le eee cee cee tceeey vee cov ventuasitavinnstnaven ., 22.4..28 | VDD... Supply voltage (+5V) *1) =k: Input terminal Ip: Input terminal with pull-up resistance O: Output terminal *2) CKSL | CKDV System clock (Input to XTI) a Fcc d ABS coe sss H L 384fs pope i Regi coor propre pr oes Sige * OWT8 | OW20 The number of output data bit ce Fc cee EO DH veel snafeneee Fo cee cee verte 18 it een : sou NIPPON PRECISION CIRCUITS 145SM5813AP/APT/AF m ABSOLUTE MAXIMUM RATINGS (Vss=OV) ITEM SYMBOL LIMITS UNIT SUPPLY VOLTAGE ppb. 0.3to7.0 |) 0 Vo. INPUT VOLTAGE | Vin. -0.3t0Vo0+03 | vo. STORAGE TEMPERATURE | Toro | 40to 125 | co POWER DISSIPATION. |. Pwo | 250 mW SOLDERING TEMPERATURE | Tun | 5 dn. C. SOLDERING TIME Tstp 10 Sec M RECOMMENDATORY OPERATING CONDITIONS (Vss=OV) ITEM SYMBOL LIMITS UNIT SUPPLY VOLTAGE | Wop) 47510 5.2500 |W. OPERATING TEMPERATURE Torro -20 to 70 C mM ELECTRIG CHARACTERISTICS * DC CHARACTERISTICS (Ta = -20 to 70C, Vpp = 4.75 to 5.25V, Vss = OV) ITEM TER- |SYMBOL| CONDITION | MIN | TYP | MAX | UNIT MINAL CURRENT CONSUMPTION | Voo | Ipp Vop=5V, fsys*3}o0 dL A mA INPUT VOLTAGE (1) XTI Vini 0.7Vpp cen be. Viu1 0.3Vpp Vv INPUT VOLTAGE (2) AI] Veeco 2 ein vo. Vit2 0.5 Vv OUTPUT VOLTAGE (2) ye Vou | Jou =-0.4mA | 25 Fo. LY tte tif dec Vou | Jor=lomA fof Oe LV INPUT LEAK CURRENT (1) | XTI Ty | MinsVDD fd 100) 200 HA co creetettttite titties vt vedic) ce Ie. Vin=OV Td, 10 [200 WA INPUT LEAK CURRENT (2) | (*1) Ty Vin =Vpp 1.0 LA INPUT CURRENT (2) In] Vin-0ovV | 10 20 LA < TERMINAL> *1__| LRCI, DIN, BCKI, CKSL, CKDV, SYN, RST, COB, OW20, OW18 #2 | CKO, DG, DOL, DOR, WCKO, BCKO, FSCO (*3) fsys; Frequency of internal system clock (AP ... 9.5SMHz/APT ...13MHz) When CKDV=L fXTV/2 When CKDV=H_ fXTI (fXTI: Frequency of XTI input clock) 146 NIPPON PRECISION CIRCUITSM AC CHARACTERISTICS SM5813AP SM5813AP/APT/AE (Ta = -20 to 70C, Von = 4.75 to 5.25V, Vs = OV) 1. XTI TERMINAL a. In case of crystal oscillation SYM- ; CONDITION IT MIN : TYP (MAX |UNIT |. oe as NOTE EM [Bou CKSL | CKD NOP A A | 192 fs, Oscillating] 5 muz | HL | 384fs frequency L : HH | 256fs | DL LPS 128s b. In case of terminal clock input SYM- ; CONDITION MIN :TYP:MAX J UNIT | loses ee ITEM |BoL ts UNIT! CxsE : CKD] NOTE Width of | A | 192fs clock tew | nSec we, Loy. 384 fs pulse ELH [256fs | L 512fs Cycle QA A 192fs time of | tey nsec | H DL | 384fs, clock wd. A | 256fs pulse L L | 512fs 2. INPUT TIMING BCKI, DIN, LRCI terminal ITEM SYMBOL] MIN :} TYP MAX] UNIT BCKI, Pulse width | tpew......).100.2 nSec BCKI, Cycle time tacy 200 nSec Rising edge of last BCKI {BL Edge of LRCI Bdge cerReD a ~ Rising edge of first BCKI Falling edge of XTI txL. Rising edge of LRCI Rising edge of LRCI tLx Falling edge of XTI 3. OUPUT TIMING ITEM SYMBOL BCKO delay time from XTI Output delay (1) XTI input clock p~~ MIN. 0.7Vpp 0.5Vpp i MAX. 0.3Vpp hm_t cw tow tey: tECy: be-LBCW-~is-tBCW-+4 (2) an - BCKI 1L5V ptps+-toH DIN } L5V heT BL i= tL B+ LRCI 15V i tXL- tix (CKDV=-L) XTI [. Vop/2 = tx tLx (3) (CKDV=H) XTI \ Vpp/2 XTI f \ } \ ' Voo/2 (CKDV=L) Tsys: XTI } Von/2 i ,_ tsbH i tsbL (CKDV=H) SeitxbH a! txbL BCKO j } L5V +iike thdL DOL 15V DOR DGL ik tbdH DGR WCKO 15V NIPPON PRECISION CIRCUITS 147SMS5813APT/AF SM5813AP/APT/AF (Ta = -20 to 70C, Vop = 4.75 to 5.25V, Vss = OV) 1, XTI TERMINAL a. Incase of crystal oscillation SYM- ITEM BOL MIN | TYP [MAX UNIT CONDITION Oscillating fmax frequency : 13.0 MHz b. In case of external clock input SYM- ITEM BOL MIN /TYP?MAX UNIT Width of clock pulse teow nSec Cycle time of clock pulse tey nSec cm m 2. INPUT TIMING BCKI, DIN, LRCI terminal ITEM SYMBOL BCKI, Pulse width Rising edge of last BCKI Edge of LRCI Edge of LRCI Rising edge of first BCKI Falling edge of XTL Rising edge of LRCI Rising edge of LRCI Falling edge of XTI 3. OUTPUT TIMING (1) XTI input clock r~ MIN. 0.7Vpp h-icw 0.5Vpp fferwennmes MAX, 0,3Vpp tBCY: bt BCW-+e-TBCW$ LSV {DH y L5V \ +tBL~i-tLp-j LRCI (3) XTI (CRDV=L) XTI Tsys- } Vop/2 ITEM SYMBOL BCKO delay time from XTI Output delay (CKDV=H) + BCKO tsbH Vop/2 ri be tsbL ie-ei txbDL + txbH A 1L5V - thdL 1L5V ~ thdH 148 NIPPON PRECISION CIRCUITSSM5813AP/APT/AF FUNCTION EIGHT-TIMES OVERSAMPLING In put of fs sampling rate to the SM5813 is output with 8fs sampling rate after calculating in the digital filter. * This LSI has cascaded three-stage FIR filter as follows: SYSTEM CLOCK SELECTION OF SYSTEM CLOCK The SM5813AP/APT/AF has an internal clock generator that may be used by connecting a crystal of the appropriate frequency between pins XTi and XTO. Alternatively, an externally generated clock can be input on XTI. The clock frequency Fxi is selected by the CKDV and CKSL inputs from one of the four multiples of the sample frequency shown in the right table, where the clock period txi=1/Fxi. For the 384fs and 512fs clock frequencies, the clock is divided by two for internal use. The system clock signal, of the same frequency as the signal on pin XTI, is available on the CKO output pin. AUDIO DATA INPUT Input data is processed MSB first and 2's comple- ment. Each bit of serial data input on the DIN pin is read into the SIPO register (serial to parallel conversion register) at the rising-edge of BCKI bit clock and converted to parallel data. The SIPO output is transferred to the Lch/Rch input register, respectively, at the rising-edge/ falling-edge of the LRCI clock. (See Figure A and B) The timing of the operation part and output part are independent from the timing of the input part, so that it is not affected by jitter of the input part. JITTER-FREE MODE AND FORCED SYN- CHRONIZATION MODE SELECTION (SYN, FSCO) The timing of the internal operation and output (internal timing) are determined by the system clock (the XTI input), which is independent of the input clock timing (BCKI, LRCI). The internal timing is provided with 2 kinds of "yitter-free mode," and "forced synchronization mode" to cope with jitter on the LRCI clock input. The setting of SYN enables selection. CONDITION | XTI Cycle time of inter- CKDV: CKSL | clock (Fx) | nal system clock Hob 1 286fs Be, Lo. A | 384fs L L 512fs 21F a iu f Input register 1 Input register 1 | Leh CI Rch ws Uj Input register 2 Input register 2 { i Leh rn Rch U 1 1 1 Latching timing of input SIPO ura fo Input register (R.,) aL) (R) FSCK LT (Intemal clock) i) @y) a) Input register NIPPON PRECISION CIRCUITS 149SM5813AP/APT/AF @ Jitter-free mode (SYN=H) When the phase difference between the LRCI clock and the internal timing is within +3/8 to -3/8 of the input sampling frequency (1/fs), the internal timing is not adjusted. Thus jitter on the LRCI clock does not affect the internal timing to prevent malfunctions and jitter transmission. If the phase difference exceeds the said range, the phase of internal timing is adjusted synchronously with the starting-side edge f the LRCI clock. When a reset is input, the phase is also adjusted. @ Forced synchronization mode (SYN=L) In this mode, the internal timing is always reset at the starting-edge of the LRCI input. In this case, malfunction occurs if a cycle which does not statisfy the required system clock cycle due to jitter onthe LRCI input exists. To the contrary, if a cycle which is longer than the specified clock cycle exists, the intervals of the output timing are not the same though operation is performed corrtectly. @ FSCO clock (output) The fs frequency clock obtained by dividing the XTI clock. DATA AND DAC CONTROL SIGNAL OUTPUT (DOL, DOR, BCKO, WCKO, DG, COB, OWI8, OW20) Table B. Output timing @ Output data format Item Sym- CKSL (1) MSB first (2) 2's complement and COB (complemented offset hee system clock 192fs | 256fs binary) switch COB format (COB=H) Bit clock cycle 7 Tas | Tas COB foramt (COB=L) Data word length Tw | 24xTsys| 32xTsvs @ Bit number selection of output data (OW18, OW20) Bit number of output data can be selected from among 16, | 7 0, _ 1 (n-18 or 18 or 20) | 18 and 2 DOL an _ Tsys is internal system clock cycle. 16-bit output wis =H, OW20=H) 18-bit output (OW18=L, OW20=H) eb Ty 74 ci a7aTw 5 20-bit output (OWT8=H, OW20=L) WCKO a @ Output tining DG Te The timing of audio output part is determined correspond- ing to the system clock frequency of each part. (See Table C. Output timing Table B, Figure C) SYSTEM RESET (RST) When a reset is input in the jitter-free mode, the internal operation timing is reset synchronously with the rising- SM5813 edge of the following LRCI clock input. Taking advan- tage of this, the output timing in the jitter-free mode can match to LRCI. Vop | Vpp The reset pulse (L level) should be longer than 5Ons after a power-on. A reset is also unnecessary in the jitter-free - Vss2 mode if the output timing is not required to match with 100pF I RST the LRCI input. In the case of performing the system reset at power-on, connect a 100pF or so capacitor to the RST pin. (See Fig D Table D. System reset circuit sample igure ) at power-on 150 NIPPON PRECISION CIRCUITSSM5813AP/APT/AE BH TIMING CHART L. LRCI MSB Lch data LSB MSB Rch data LSB on LIL LEELA TET SERIAL INPUT TIMING fs cycle LTTE 2. DOL DOR WCKO BCKO DG _ more than | 16 cycle _. More than |; Ocycle | O cycle SERIAL OUTPUT TIMING 16 cycle NIPPON PRECISION CIRCUITS 151mM TYPICAL APPLICATION SM5813AP/APT/AF 1. INPUT U x tal | ( 16.9344MHz ) ( SONY ) XTAI OSSMME? cK = XT]. XTO CXD1125 LRCK 44.1kHz ERCI CXD1130 CXD1135 DATA DN SM5813 2.1168MHz PSSL___SLOB C210 BCKI 16.9344MH: (MATSUSHITA) *CK 2} yt} MN6617 RAL po Hed SRDATA DIN SM5813 SEL IPSEL SRCK BCKI RD (YAMAHA) OA 16.9344MHz XTI YM3623 LR 44,1kH2 _ DO DIN SM5813 Ber! CKDV 152 NIPPON PRECISION CIRCUITSSM5813AP/APT/AF 2. OUTPUT 0 X tal oa ( 8.4672MHz ) 8.48672MH (MITSUBISHI) x1 =) cKo XT XTO M50421P LRCK 44-1KHz LRCI DO DIN SM5813 2.1168MHz DASEL DFPAS DSCK BCKI iS NIPPON PRECISION CIRCUITS 153