EMIF061005N12 - STMICROELECTRONICS

July 2011 Doc ID 16959 Rev 2 1/12

EMIF06-1005N12

6-line IPAD™, low capacitance

EMI filter and ESD protection in narrow micro QFN package

Features

■EMI symmetrical (I/O) low-pass filter

■High efficiency in EMI filtering at frequencies

from 900 MHz to 1.8 GHz

■Very low PCB space consumption:

2.5 mm x 1.2 mm

■Very thin package: 0.55 mm max

■High efficiency in ESD suppression on inputs

pins (IEC 61000-4-2 level 4)

■High reliability offered by monolithic integration

■High reduction of parasitic elements through

integration and wafer level packaging

■Lead-free package

Complies with the following standards

■IEC 61000-4-2 level 4 input and output pins

–+ 15 kV (air discharge)

–+ 8 kV (contact discharge)

■MIL STD 883G - Method 3015-7 Class 3B

(all pins)

Applications

Where EMI filtering in ESD sensitive equipment is

required:

■LCD and camera for mobile phones

■Computers and printers

■Communication systems

■MCU boards

■Keypad for portable equipment

TM: IPAD is a trademark of STMicroelectronics.

Figure 1. Pin configuration (top view)

Figure 2. Basic cell configuration

Description

EMIF06-1005N12 is a 6-line, highly integrated

device designed to suppress EMI/RFI noise in all

systems exposed to electromagnetic

interference.This filter includes ESD protection

circuitry, which prevents damage to the

application when subjected to ESD surges up to

15 kV on the input pins.

µQFN-12L

1 Input Output 12

Output 11

Output 10

Output 9

2 Input

3 Input

4 Input

Output 8

Output 7

5 Input

6 Input

Typical line capacitance = 45 pF @ 0 V

100 Ω

Input Output

www.st.com

Characteristics EMIF06-1005N12

2/12 Doc ID 16959 Rev 2

1 Characteristics

Figure 3. Electrical characteristics (definitions)

Table 1. Absolute ratings (limiting values)

Symbol Parameter and test conditions Value Unit

VPP

ESD discharge IEC 61000-4-2, level 4

air discharge

contact discharge

ESD-Machine Model :

(MM: C = 200 pF, R = 25 Ω L = 500 nH)

ESD-Charged Device Model:

(JESD22-C101D)

TjJunction temperature at Tamb = 25 °C 125 °C

Top Operating temperature range - 40 to + 85 °C

Tstg Storage temperature range - 55 to + 150 °C

Table 2. Electrical characteristics (Tamb = 25 °C)

Symbol Test conditions Min. Typ. Max. Unit

VBR IR = 1 mA 6 8 10 V

VFIF = 10 mA 0.5 1 1.5 V

IRM VRM = 3 V per line 200 nA

RI/O Tolerance ± 15% 85 100 115 Ω

Cline Vline = 0 V, Vosc = 30 mV, F = 1 MHz 38 45 52 pF

IRM

IPP

VRM VF

VBR

VCL

Symbol Parameter

V = Breakdown voltage

I = Leakage current @ V

V = Stand-off voltage

I = Forward current

I = Peak pulse current

I = Breakdown current

V = Forward voltage drop

RM RM

V = Clamping voltage

d= Dynamic impedance

I = Forward current

R = Series resistanc between input and output

C = Input capacitance per line

I/O

line

EMIF06-1005N12 Characteristics

Doc ID 16959 Rev 2 3/12

Figure 8. ESD test conditions for figure 6 and figure 7

Figure 4. S21 attenuation measurement Figure 5. Analog cross talk measurements

300k 1M 3M 10M 30M 100M 300M 1G 3G

- 60

- 50

- 40

- 30

- 20

- 10

0.0 S21 (dB)

I2-O2

I3-O3

I4-O4

I5-O5

I1-O1

I6-O6

I2-O2

I3-O3

I4-O4

I5-O5

I1-O1

I6-O6

F = 110 MHz

-31

-35

S21(dB)

F = 900 MHz

S21(dB)

F = 1.8 GHz

F(Hz)

V = 0V

BIAS

300k 1M 3M 10M 30M 100M 300M 1G 3G

- 130

- 120

- 110

- 100

- 90

- 80

- 70

- 60

- 50

- 40

- 30

- 20

- 10

0.0

I2-O5

I2-O3

XTalk (dB)

V = 0V

BIAS

F(Hz)

Figure 6. ESD response to IEC 61000-4-2

(+8 kV contact discharge).

Remaining voltage on filter output

Figure 7. ESD response to IEC 61000-4-2

(-8 kV contact discharge).

Remaining voltage on filter output

V max

27.2 V 3.3 V

4.6 V

t = 30 ns

t = 100 ns

OUTPUT

5 V/Div

20 ns/Div

V max

-20.7 V -787 mV

-3.2 V

t = 30 ns

t = 100 ns

OUTPUT

5 V/Div

20 ns/Div

D.U.T Attenuator 20…60dB

50 Ohm

>500MHz Oscilloscope with

50 Ohm input mode

Characteristics EMIF06-1005N12

4/12 Doc ID 16959 Rev 2

Figure 11. Line capacitance versus applied voltage

Figure 9. ESD response to IEC 61000-4-2

(+15 kV air discharge) on one line

Figure 10. ESD response to IEC 61000-4-2

(-15 kV air discharge) on one line

INPUT

5 V/Div

2 V/Div

100 ns/Div

OUTPUT

INPUT

C3 OUTPUT

5 V/Div

100 ns/Div

2 V/Div

100 ns/Div

0123456

C(pF)

V (V)

EMIF06-1005N12 Ordering information scheme

Doc ID 16959 Rev 2 5/12

2 Ordering information scheme

Figure 12. Ordering information scheme

EMIF yy - xxx z Nx

EMI filter

Number of lines

Information

x = resistance value (Ohms)

z = capacitance value / 10(pF)

Package

Nx = narrow micro QFN x leads

Package information EMIF06-1005N12

6/12 Doc ID 16959 Rev 2

3 Package information

●Epoxy meets UL94, V0

●Lead-free package

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Table 3. µQFN-12L dimensions

Ref.

Dimensions

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.45 0.5 0.55 0.018 0.020 0.022

A1 0.02 0.05 0.0008 0.002

b 0.15 0.2 0.25 0.006 0.008 0.010

D 2.45 2.5 2.55 0.096 0.098 0.10

D2 1.75 1.8 1.85 0.069 0.071 0.73

E 1.15 1.2 1.25 0.045 0.047 0.050

E2 0.25 0.3 0.35 0.010 0.012 0.014

e 0.4 0.016

L 0.15 0.25 0.35 0.006 0.010 0.014

Figure 13. Footprint recommendations Figure 14. Marking

TOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN#1 ID

1.8

0.4

0.3

0.45

2.2

1.6

0.2

EMIF06-1005N12 Package information

Doc ID 16959 Rev 2 7/12

Figure 15. Flip-Chip tape and reel specification

Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should

this product marking be used to orient the component for its placement on a PCB. Only pin

1 mark is to be used for this purpose.

User direction of unreeling

All dimensions in mm

4.0 ± 0.1

8.0 ± 0.20

1.75 ± 0.1 3.5 ±- 0.05

Ø 1.55 ± 0.05

1.20 ± 0.10

1.40 ±0.10

2.70 ±0.10

4.0 ± 0.1

Dot identifying Pin A1 location 2.0 ± 0.05

0.25 ± 0.02

Recommendation on PCB assembly EMIF06-1005N12

8/12 Doc ID 16959 Rev 2

4 Recommendation on PCB assembly

4.1 Stencil opening design

1. General recommendation on stencil opening design

a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).

Figure 16. Stencil opening dimensions

b) General design rule

Stencil thickness (T) = 75 ~ 125 µm

2. Reference design

a) Stencil opening thickness: 100 µm

b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%.

c) Stencil opening for leads: Opening to footprint ratio is 90%.

Figure 17. Recommended stencil window position

Aspect Ratio W

----- 1.5≥=

Aspect Area LW×

2T L W+()

----------------------------0.66≥=

Stencil Window

Footprint

200 µm

450 µm

420 µm

190 µm

15 µm

0.2

2.2

0.4

µm

5µm

300 µm

1800 µm

170 µm

1600 µm

100 µm 100 µm

65 µm

5µm

1.8

0.45

1.6

0.3

EMIF06-1005N12 Recommendation on PCB assembly

Doc ID 16959 Rev 2 9/12

4.2 Solder paste

1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.

2. “No clean” solder paste is recommended.

3. Offers a high tack force to resist component movement during high speed.

4. Solder paste with fine particles: powder particle size is 20-45 µm.

4.3 Placement

1. Manual positioning is not recommended.

2. It is recommended to use the lead recognition capabilities of the placement system, not

the outline centering.

3. Standard tolerance of ± 0.05 mm is recommended.

4. 3.5 N placement force is recommended. Too much placement force can lead to

squeezed out solder paste and cause solder joints to short. Too low placement force

can lead to insufficient contact between package and solder paste that could cause

open solder joints or badly centered packages.

5. To improve the package placement accuracy, a bottom side optical control should be

performed with a high resolution tool.

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is

recommended during solder paste printing, pick and place and reflow soldering by

using optimized tools.

4.4 PCB design preference

1. To control the solder paste amount, the closed via is recommended instead of open

vias.

2. The position of tracks and open vias in the solder area should be well balanced. The

symmetrical layout is recommended, in case any tilt phenomena caused by

asymmetrical solder paste amount due to the solder flow away.

Recommendation on PCB assembly EMIF06-1005N12

10/12 Doc ID 16959 Rev 2

4.5 Reflow profile

Figure 18. ST ECOPACK® recommended soldering reflow profile for PCB mounting

Note: Minimize air convection currents in the reflow oven to avoid component movement.

01234567

Time (min)

Temperature (°C)

2°C/s recommended

6°C/s max

220°C

125 °C

260°C max

255°C

180°C

90 sec max

10-30 sec

90 to 150 sec

3°C/s max

01234567

Time (min)

Temperature (°C)

2°C/s recommended

6°C/s max

220°C

125 °C

260°C max

255°C

180°C

90 sec max

10-30 sec

90 to 150 sec

3°C/s max

EMIF06-1005N12 Ordering information

Doc ID 16959 Rev 2 11/12

5 Ordering information

6 Revision history

Table 4. Ordering information

Order code Marking Package Weight Base qty Delivery mode

EMIF06-1005N12 KB µQFN-12L 4.48 mg 3000 Tape and reel 7”

Table 5. Document revision history

Date Revision Changes

12-Jan-2010 1Initial release.

03-Jul-2011 2Updated package name throughout the document.

EMIF06-1005N12

12/12 Doc ID 16959 Rev 2

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