CY62136FV30 MoBL®
2-Mbit (128 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-08402 Rev. *M Revised November 27, 2014
2-Mbit (128 K × 16) Static RAM
Features
■Very high speed: 45 ns
■Temperature ranges
❐Industrial: –40 °C to +85 °C
❐Automotive-A: –40 °C to +85 °C
❐Automotive-E: –40 °C to +125 °C
■Wide voltage range: 2.20 V to 3.60 V
■Pin compatible with CY62136V, CY62136CV30/CV33, and
CY62136EV30
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 5 A (Industrial)
■Ultra low active power
❐Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP) II
packages
Functional Description
The CY62136FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90 percent when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or
during a write operation (CE LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
For a complete list of related resources, click here.
128 K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
Logic Block Diagram
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 2 of 18
Contents
Product Portfolio ..............................................................3
Pin Configuration .............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ...................................................................... 5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure .......................................................15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support ..................................................... 18
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 3 of 18
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2
(A)
f = 1 MHz f = fmax
Min Typ [1] Max Typ [1] Max Typ [1] Max Typ [1] Max
CY62136FV30LL Industrial/Auto-A 2.2 3.0 3.6 45 1.6 2.5 13 18 1 5
Auto-E 2.2 3.0 3.6 55 2 3 15 25 1 20
Pin Configuration
Figure 1. 48-ball VFBGA pinout [2, 3] Figure 2. 44-pin TSOP II pinout [2]
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
A7
I/O0
BHE
NC
NC
A2
A1
BLE
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
16
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 4 of 18
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential [4, 5] ... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
DC voltage applied to outputs
in High Z State [4, 5] .......... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current .....................................................> 200 mA
Operating Range
Device Range Ambient
Temperature VCC[6]
CY62136FV30LL Industrial/
Auto-A
–40 °C to +85 °C 2.2 V to 3.6 V
Auto-E –40 °C to +125 °C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -45 (Industrial/Auto-A) -55 (Auto-E) Unit
Min Typ [7] Max Min Typ [7] Max
VOH Output high voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 – – 2.0 – – V
2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 – – 2.4 – – V
VOL Output low voltage 2.2 < VCC < 2.7 IOL = 0.1 mA – – 0.4 – – 0.4 V
2.7 < VCC < 3.6 IOL = 2.1 mA – – 0.4 – – 0.4 V
VIH Input high voltage 2.2 < VCC < 2.7 1.8 – VCC + 0.3 1.8 – VCC + 0.3 V
2.7 < VCC < 3.6 2.2 – VCC + 0.3 2.2 – VCC + 0.3 V
VIL Input low voltage 2.2 < VCC < 2.7 –0.3 – 0.6 –0.3 – 0.6 V
2.7 < VCC < 3.6 –0.3 – 0.8 –0.3 – 0.8 V
IIX Input leakage current GND < VI < VCC –1 – +1 –4 – +4 A
IOZ Output leakage current GND < VO < VCC, Output disabled –1 – +1 –4 – +4 A
ICC VCC operating supply
current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
– 13 18 – 15 25 mA
f = 1 MHz – 1.6 2.5 – 2 3
ISB1[8] Automatic CE power
down current — CMOS
inputs
CE > VCC –0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and data only),
f = 0 (OE, WE, BHE, and BLE),
VCC = 3.60 V
–15–120A
ISB2 [8] Automatic CE power
down current — CMOS
inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–15–120A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max)=VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 5 of 18
Capacitance
Parameter [9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter [9] Description Test Conditions 48-ball VFBGA 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, two
layer printed circuit board
75 77 C/W
JC Thermal resistance
(junction to case) 10 13 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC
VCC
OUTPUT
R2
30 pF GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
V
INCLUDING
JIG AND
SCOPE
Parameters 2.5 V (2.2 V to 2.7 V) 3.0 V (2.7 V to 3.6 V) Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 6 of 18
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [10] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR [11] Data retention current VCC = 1.5 V,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
Industrial/
Automotive-A
––4A
Automotive-E – – 12
tCDR [12] Chip deselect to data retention
time 0––ns
tR [13] Operation recovery time CY62136FV30LL-45 45 – – ns
CY62136FV30LL-55 55 – –
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
VCC
CE or
BHE.BLE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR specification. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 7 of 18
Switching Characteristics
Over the Operating Range
Parameter [15, 16] Description -45 (Industrial/Automotive-A) -55 (Automotive-E) Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45 –55 –ns
tAA Address to data valid –45 –55 ns
tOHA Data hold from address change 10 –10 –ns
tACE CE LOW to data valid –45 –55 ns
tDOE OE LOW to data valid –22 –25 ns
tLZOE OE LOW to low Z [17] 5 – 5 – ns
tHZOE OE HIGH to high Z [17, 18] –18 –20 ns
tLZCE CE LOW to low Z [17] 10 –10 –ns
tHZCE CE HIGH to high Z [17, 18] –18 –20 ns
tPU CE LOW to power up 0 – 0 – ns
tPD CE HIGH to power down –45 –55 ns
tDBE BLE/BHE LOW to data valid –22 –25 ns
tLZBE BLE/BHE LOW to low Z [17] 5 – 5 – ns
tHZBE BLE/BHE HIGH to high Z [17, 18] –18 –20 ns
Write Cycle [19]
tWC Write cycle time 45 –55 –ns
tSCE CE LOW to write end 35 –40 –ns
tAW Address setup to write end 35 –40 –ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 –40 –ns
tBW BLE/BHE LOW to write end 35 –40 –ns
tSD Data setup to write end 25 –25 –ns
tHD Data Hold From Write End 0 – 0 – ns
tHZWE WE LOW to high Z [17, 18] –18 –20 ns
tLZWE WE HIGH to low Z [17] 10 –10 –ns
Notes
15. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
16. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production. .
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 8 of 18
Switching Waveforms
Figure 5. Read Cycle No.1: Address Transition Controlled [20, 21]
Figure 6. Read Cycle No. 2: OE Controlled [21, 22]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
20. The device is continuously selected. OE, CE = VIL, BHE and BLE = VIL.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE and BHE, BLE transition LOW.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 9 of 18
Figure 7. Write Cycle No 1: WE Controlled [23, 24, 25]
Figure 8. Write Cycle 2: CE Controlled [23, 24, 25]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 26
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 26
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
24. Data I/O is high impedance if OE = VIH.
25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 10 of 18
Figure 9. Write Cycle 3: WE controlled, OE LOW [27]
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [27]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 28
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 28
DATA I/O
ADDRESS
CE
WE
BHE/BLE
Notes
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 11 of 18
Truth Table
CE WE OE BHE BLE Inputs or Outputs Mode Power
HXXX
[29] X[29] High Z Deselect or power-down Standby (ISB)
L X X H H High Z Output disabled Active (ICC)
L H L L L Data out (I/O0–I/O15)Read Active (I
CC)
LHLHLData out (I/O
0–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read Active (ICC)
L H H L L High Z Output disabled Active (ICC)
L H H H L High Z Output disabled Active (ICC)
L H H L H High Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write Active (ICC)
Note
29. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate
voltage levels on these pins is not permitted.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 12 of 18
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62136FV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial
CY62136FV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
CY62136FV30LL-45ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A
55 CY62136FV30LL-55ZSXE 51-85087 44-pin TSOP II (Pb-free) Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Temperature Grade: X = I or A or E
I = Industrial; A = Automotive-A or E = Automotive-E
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: XX = 45 ns or 55 ns
Low Power
Voltage Range: 3 V typical
Process Technology: 90 nm
Bus width = × 16
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY -XX
621 36FLL X
XX X
V30
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 13 of 18
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 14 of 18
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
Package Diagrams (continued)
51-85087 *E
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 15 of 18
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
ns nanosecond
%percent
pF picofarad
ohm
Vvolt
Wwatt
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 16 of 18
Document History Page
Document Title: CY62136FV30 MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-08402
Revision ECN Submission
Date
Orig. of
Change Description of Change
** 467351 See ECN NXR New data sheet.
*A 797956 See ECN VKN Changed status from Preliminary to Final.
Changed ISB1(typ) and ISB1(max) specification from 0.5 A to 1.0 A and 2.5 A
to 5.0 A, respectively
Changed ISB2(typ) and ISB2(max) specification from 0.5 A to 1.0 A and 2.5 A
to 5.0 A, respectively
Changed ICCDR(typ) and ICCDR(max) specification from 0.5 A to 1.0 A and
2.5 A to 4.0 A, respectively
Changed ICC(max) specification from 2.25 A to 2.5 A
*B 869500 See ECN VKN Added Automotive information
Updated Ordering information table
Added footnote 12 related to tACE
*C 901800 See ECN VKN Added footnote 9 related to ISB2 and ICCDR
Made footnote 13 applicable to AC parameters from tACE
*D 1371124 See ECN VKN /
AESA
Converted Automotive information from preliminary to final
Changed IIX min spec from –1 A to –4 A and IIX max spec from +1 A to +4 A
Changed IOZ min spec from –1 A to –4 A and IOZ max spec from +1 A to +4 A
Changed tDBE spec from 55 ns to 25 ns for automotive part
*E 2594937 10/22/08 NXR /
PYRS Added Automotive-A information
Changed tLZBE from 10 ns to 5 ns for -55.
*F 2675375 03/17/2009 VKN /
PYRS Corrected typo on page 2 (Corrected ISB2 unit to A from mA)
*G 2882113 02/19/2010 VKN /
AESA Corrected typo in the Truth Table
Added Table of Contents
Updated package diagrams
*H 2943752 06/03/2010 VKN Added footnote related to Chip enable and Byte enables in Truth Table
Updated Package Diagrams
*I 3055169 10/12/2010 RAME Updated all foot notes from table notes.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated Package Diagrams.
*J 3263825 06/17/2011 RAME Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated Data Retention Characteristics (Minimum value of tR parameter).
Updated to new template.
*K 3376161 09/19/2011 RAME No technical updates. Completing sunset review.
*L 4102266 08/22/2013 VINI Updated Switching Characteristics:
Updated Note 16.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
CY62136FV30 MoBL®
Document Number: 001-08402 Rev. *M Page 17 of 18
*M 4581648 11/27/2014 VINI Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
Document History Page (continued)
Document Title: CY62136FV30 MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-08402
Revision ECN Submission
Date
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Document Number: 001-08402 Rev. *M Revised November 27, 2014 Page 18 of 18
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
CY62136FV30 MoBL®
© Cypress Semiconductor Corporation, 2006-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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