, am PRELIMINARY M_=Iic MxX29L 8O0O0OT/B 8NM-BIT [1M x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH EEPROM FEATURES - Erase suspend capability - Fast erase time: 50ms typical for chip erase * Extended single-supply voltage range 2.7V to 3.6V * Auto Page Program operation for read and write - Automatically programs and verifies data at JEDEC-standard EEPROM commands specified addresses * Endurance : 100,000 cycles - Internal address and data latches for 128 bytes per * Fast access time: 120ns page * Optimized block architecture on power dissipation - One 16 Kbyte protected block(16K-block) Sona ace current ' - Two 8 Kbyte parameter blocks Ur standby curren - One 96 Kbyte main block - 1uA deep power-down current - Seven 128 Kbyte main blocks * Hardware Reset pin (RP) * Hardware and software data protection - Reset internal state machine, and put the device - Hardware Write Protection pin (WP) ; . into deep power-down mode - Hardware Lockout bit for 16K-block Built-in 128 Bytes Page Buffer - Software command data protection - Work as SRAM for temporary data storage * Software EEPROM emulation with parameter blocks ~ Fast access to temporary data * Status register * Low Vcc write inhibit < 1.8V - For detection of program or erase cycle completion * Industry standard surface mount packaging * Auto Erase operation - 40-Lead TSOP Type | - Automatically erases any one of the sectors or the whole chip 1.0 GENERAL DESCRIPTION The MX29L8000T/B is a 8 Mbit, 3 V-only Flash memory Programming the MX29L8000T/B is performed on a page organized as a 1 Mbytes of 8 bits each. For flexible erase basis; 128 bytes of data are loaded into the device and then and program capability, the 8 Mbits of data is divided into programmed simultaneously. The typical Page Program 11 sectors of one 16 Kbyte protected block, two 8 Kbyte time is 5ms.The device can also be reprogrammed in parameter blocks, one 96 Kbyte main block, and seven 128 standard EPROM programmers. Reading data out of the Kbyte main blocks. To allow for simple in-system device is similar to reading from an EPROM or other flash. operation, the device can be operated with a single 2.7 V to 3.6 V supply voltage. Since many designs read from the Erase is accomplished by executing the Erase command flash memory a large percentage of the time, significant sequence. This willinvoke the Auto Erase algorithm which power saving is achieved with the 2.7 V VCC operation. is an internal algorithm that automatically times the erase Manufactured with MXIC's advanced nonvolatile memory pulse widths and verifies proper cell margin. This device technology, the device offers access times of 120 ns, and features both chip erase and block erase. Each block can a low 1uA typical deep power-down current. be erased and programmed without affecting other blocks. Using MXICs advanced design technology, no The MX29L8000T/B command set is compatible with the preprogram is required (internally or externally). As a result, JEDEC single-power-supply flash standard. Commands the whole chip can be typically erased and verified in as fast are written to the command register using standard as 50 ms. microprocessor write timings. MXICs flash memory __ augments EPROM functionality with an internal state Acombined feature of Write Protection pin (WP), Reset pin machine which controls the erase and program circuitry. (RP), 16K-block lockout bit, and software command The device Status Register provides a convenient way to sequences provides complete data protection. First, monitor when a program or erase cycle is complete, andthe software data protection protects the device from success or failure of that cycle. P/N: PM0446 REV.1.4, Jan 12, 1998 29-1M=Iic % inadvertent program or erase. Two "unlock" write cycles must be presented to the device before the program or erase command can be accepted by the device. For hardware data protection, the WP pin and FP pin provide MxX29L 8000T/B PIN CONFIGURATIONS SYMBOL PIN NAME , ce nn AQ-A19 Address Input protection against unwanted commandwrites due to invalid ress np system bus condition that may occur during system reset Q0-Q7 Data Input/Output and power-up/down sequence. Finatly, with 16K-block lockout bit feature, the device provides complete core CE Chip Enable Input security for the kernel code required for system = initialization. OE Output Enable Input The device has 128 Bytes built-in page buffer, which.can WE Write Enable serve as SRAM. This feature provides a convenient way AP Reset/Deep Power-down to store temporary data for fast read and write. ___ _ WP Write Protect MXICs Flash technology reliably stores memory contents after 100,000 erase and program cycles. The MXICs cell vcc Power Supply Pin (2.7V - 3.6V) is designed to optimize the erase and program mechanism. _ In addition, the combination of advanced tunnel oxide GND Ground Pin processing and low internal electric fields for erase and program operations produce reliable cycling. The highest degree of latch-up protection is achieved with MXICs proprietary non-epi process. Latch-up protectionis proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V. 1 2 PINOUTS 40TSOP (TPYE 1) 10 x 20mm AIG 1 40 AI? AIS 2 39 GND Ald | 3 O 38 > NC A13. 4 37 AID Al2 5 36 AIO Att 6 35 *. DQ? AQ 7 34 * -DOQ6 AB 8 33 pas WE " 9 ' pas ae MX29L8000T/B a | vee NC . 1 30 VCC we | 412 29 NC Ata 13 28 | DQ3 AT 44 27 paz AG 15 26 Dat AS 16 25 pao AS | 17 24 OE AS 18 23 GND a2 _| 19 22 cE Al 20 21 - AG P/N: PM0446 REV.1.4, Jan 12, 1998 29-2M=Iic MxX29L8000T/B 1.1 MX29L8000T/B SECTOR ARCHITECTURE FFEFEFH 16-Kbyte BLOCK FCOOOH byte BLOC EBFFFH oot -Kbyte PARAMETER BLOCK FOFFFH -Kbyte PARAMETER BL aed -Kbyte PARAMET OCK F7FFEH 96-Kbyte MAIN BLOCK E0000H DFFFFEH 128-Kbyte MAIN BLOCK CO000H BFFFFH 128-Kbyte MAIN BLOCK AQOOGH QFEFFH 128-Kbyte MAIN BLOCK 80000H 7FFFEH 128-Kbyte MAIN BLOCK 60000H 5FFFEFH 128-Kbyte MAIN BLOCK 40000H 3FFFFH 128-Kbyte MAIN BLOCK 20000H 1FPRFFFH 128-Kbyte MAIN BLOCK 00000H MX29L8000T Memory Map FFFFFH Om No No no ns3 xr BOQ No no no no xrIz op Ne no no 1) xrIt ao To TO nod nO} rz Ag Te TOS no nO rx Op Nos WhO no nS rit +p TO 1S no nNOS} xrIt oO SOSRSPO Oo CaMNana oO TONONYS Oo TNOTNONS o TOTOTNS mZrTrIrTrie 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 96-Kbyte MAIN BLOCK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 16-Kbyte BLOCK MX29L8000 B Memory Map P/N: PM0446 REV.1.4, Jan 12, 1998MEIC MxX29L 8000T/B BLOCK DIAGRAM AP. WP 4 Vb | WRITE Ls CE CONTROL PROGRAM/ERASE ae ae STATE a Oe => INPUT HIGH VOLTAGE ae WE occ _! _ MACHINE (WSM) COMMAND INTERFACE x | REGISTER MX29L8000T/B ciR) ADDRESS s FLASH oO LATCH nm ARRAY ARRAY A0-A19 SOURCE AND z HV COMMAND BUFFER 3 DATA 6 | Y-PASS GATE =| 8 DECODER a SENSE rom DATA AMPLIFIER | | HV COMMAND {J P DATA LATCH PAGE PROGRAM | DATA LATCH | { 0 BUFFER P/N: PM0Q446 REV.1.4, Jan 12, 1998 29-4Ml MX29L8000T/B Tabie 1 .PIN DESCRIPTIONS SYMBOL AQ-A19 TYPE INPUT NAME AND FUNCTION ADDRESS INPUTS: for memory addresses. Addresses are internally latched uring a write cycle. Q0-Q7 INPUT/OUTPUT INPUTS/OUTPUTS DATA BUS: Input data and commands during Command Interface Register(CIR) write cycles. Outputs array,status ,identifier data, and page buffer in the appropriate read mode. Floatto tri-state when the chip is de- selected or the outputs are disabled. INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With CE high, the device is deselected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low to select the device. INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during aread cycle. OE is active low. INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE is active low. INPUT RESET/DEEP POWER-DOWN: When RP is low, the device is in reset/deep power-down mode. When RP is high, the device is in standard operation. INPUT WRITE PROTECTION: Provides a method for locking the 16K-block, using three voltage levels (VIL, VIH, and VHH). When WP is low, the 16K-block is locked. When WP is high the 16K-block is unlocked, if the 16K-block lockout bit is disabled. When WP is at VHH, the 16K-block is unlocked. This overrides the status of the lockout bit. See Section3 for details of data-protection vcc DEVICE POWER SUPPLY(2.7V - 3.6V} GND GROUND 1.3 BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU. Allbus cycles to or fromthe flash memory conform to standard microprocessor bus cycles. These bus operations are summarized below. Table2 MX29L8000T/B Bus Operations Mode Notes | CE OE WE | RP AQ Al AQ Q0-Q7 Read VIL VIL VIH_ | VIH X Xx x DOUT Output Disable VIL VIH VIH_ | VIH Xx Xx Xx HighZ Standby VIH x X VIH X X x HighZ Deep powerdown Xx Xx Xx VIL x Xx Xx HighZ Manufacturer ID VIL VIL VIH VIH VIL VIL VHH C2H Device ID VIL VIL VIH_ | VIH VIH VIL VHH 83H(Top Boot) 82H(Bottom Boot) Write VIL VIH VIL | VIH X x X DIN NOTES :1.X can be VIH or VIL for address or control pins. 2. VHH = 11.5V- 12.5V. P/N: PM0446 REV.1.4, Jan 12, 1998 29-5M=Ic 1.4 WRITE OPERATIONS The Command Interface Register (CIR) is the interface between the microprocessor and the internal chip controller. Device operations are selected by writing specific address and data sequence into the CIR, using standard microprocessor write timings. Writing incorrect data value or writing them in improper sequence will reset the device to the read mode.(read array or read buffer) Table 3 defines the valid command sequences. Note that the Erase Suspend (BOH) and Erase Resume (30H) are valid only while an erase operation is in progress and will be ignored in other circumstance. There are four read TABLE 3. COMMAND DEFINITIONS MxX29L 8000T/B modes: Read Array, Read Silicon ID, Read Status Register, and Read Page Buffer. For Program and Erase commands, the CIR will inform the interna inform the internal state machine that a program or erase sequence has been requested. During the execution of program or erase operation, the state machine will control the program /erase sequence. After the state machine has completed its task, it will set bit 7 of the Status Register (SR. 7) toa "{", which indicates that the CIR can respond to the full command set. Command Read/ | Silicon | Page/Byte Chip Block Erase Erase Sleep Sequence Reset | !D Read | Program Erase Erase | Suspend | Resume Mode Bus Write 4 4 4 6 6 1 1 3 Cycles Required First Bus Addr XXXXH | 5555H 5555H 5555H 5555H | XXXXH_ XXXXH_ J 5555H Write Cycle Data FOH AAH AAH AAH AAH BOH 30H AAH Second Bus Addr RA 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data RD 55H 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H Write Cycle Data 90H AOQH 80H 80H COH Fourth Bus Adar QOH/01H PA 5555H 5555H Read/Write Cycie Data C2H/83H PD AAH AAH Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr 5555H SA Write Cycle Data 10H 30H P/N: PM0446 REV.1.4, Jan 12, 1998 29-6Mic MX29L8000T/B COMMAND DEFINITIONS(continue Table 3.) Command Lock Lock Status Read Write Read Clear Clear Sequence 16K-block Read Page Buffer | Page Buffer | Status Register {Status Register | Buffer Bus Write 6 4 4 4 3 3 3 Cycles Required First Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH RAAAH Write Cycle Data 55H 55H 55H 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data 60H 90H 75H EOH 70H 50H 04H Fourth Bus Adar 5555H 02H RA RA Read/Write Cycle | Data AAH C2H/00H RD RD Fifth Bus Addr 2AAAH Write Cycle Data 55H Sixth Bus Addr SA Write Cycle Data 20H Notes: 1.Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from AO to A14. 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. __ PA = Address of the memory location to ba programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the block to be erased. The combination of A13 -- A19 will uniquely select any block. 4. RD = Data read from location RA during a read operation. __ PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. . Erase can be suspended during sector erase with Addr = don't care, Data = BOH . Erase can be resumed after suspend with Addr = don't care, Data = 30H. . Clear Buffer set all buffer data to 1. . In lack status Read, SAO2H = 00002H for Bottom Boot SA02H = FFFO2H for Top Boot OND : PM0446 REV.1.4, Jan 12, 1998 PIN: PM 29-7MI a a 2.0 DEVICE OPERATION 2.1 SILICON ID READ The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VHH (1 1.5V~12.5V) on address pin A9. Twoidentifier bytes may then be sequenced from the device outputs by toggling address AO from VIL to VIH. All addresses are don't cares except AO and Al. The manufacturer and device codes may also be read via the command register, for instances when the MX29L8000T/B is erased or programmed in a system MX29L8000T/B without access to high voltage on the AQ pin. The command sequence is illustrated in Tabie 3. Following the command write, a read cycle with AO = VIL retrieves the manufacturer code of C2H. Aread cycle with AO = VIH returns. the device code . MX29L8000T Device Code =83H, MX29L8000B Device Code = 82H To terminate the operation, it is necessary to write the Read/Reset command sequence inta the CIR. Table 4. MX29L8000T/B Silion ID Codes and Verify Sector Protect Code Type A,,~A, A, A, | Code(HEX) | DQ, | DQ, |DQ, /DQ, |DQ, DQ, /DQ,| DA, Manufacturer Code X Vit VIL. C2H 1 1 0 0 0 0 1 0 MX29L8000T Device Code X VIL VIH 83H 1 0 0 0 o}|o!1 1 MX29L8000B Device Code X VIL VIH 82H 1 0 0 0 o | 0 1 0 Verify 16K-Block Protect** SA VIH VIL C2H* 1 1 0 0 0 | 0 1 0 * Outputs C2H if 16K-block is protected (lockout bit is enabled), OOH otherwise. ** Only the 16K-Block has protect-bit feature. P/N: PM0446 REV.1.4, Jan 12, 1998 29-82.2 READ/RESET COMMAND The read or reset operation is initiated by writing the Read/ Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains ready for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29L8000T/B is accessed like an EPROM. When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. Note that the Read/Reset command is not valid when program or erase is in progress. 2.3 PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock write cycles. These are followed by writing the page program command AOH. Any attempt to write to the device without the three- cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device. After three-cycle command sequence is given, a byte load is performed by applying a iow pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page. MX29L8000T/B 2.3.1 PROGRAM Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. The device is programmed on a page basis. If a byte of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE (or CE) within 30us of the low to high transition of WE (or CE) ofthe preceding byte. A7 to A19 specify the page address, i.e., the device is page-aligned on 128 bytes boundary. The page address must be valid during each high to low transition of WE or CE. AO to A6 specify the byte address within the page The byte may be loaded in any order; sequential loading is not required. If a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The load period will also end if the same address is consecutively loaded twice. The first data and address will be treated as normal data to be programmed. The second data needs to be '00 to terminate the load cycle. Other numbers besides '00 are reserved for future use. The status of program can be determined by checking the Status Register. While the program operation is in progress, bit 7 of the Status Register (SR. 7) is "0". When the Status Register indicates that program is complete (when SR. 7 = 1), the Program Status bit should be checked to verify that the program operation was successful. If the program operation was unsuccessful, SR. 4 of the Status Register will be set to "1" to indicate a program failure. The Status Register should be cleared before attempting the next operation. P/N: PM0446 REV.1.4, Jan 12, 19982.4 CHIP ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more unlock write cycles are then followed by the Chip Erase command 10H. Chip erase does not require the user to program the device prior to erase. The 16K-Biock will not be erased if itis protected (16K-Block Lockout bit enabled). The Auto Chip Erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on SR.7 is "1". While the erase sequence is in progress, SR.7 of the Status Register is "0". When erase is complete, the Erase Status bit should be checked. If the erase operation was unsuccessful, SR.5 of the Status Register is set to a "1" to indicate an erase failure. Clear the Status Register before attempting the next operation. 2.5 BLOCK ERASE Sector erase is a six-bus cycle operation. There are two unlock write cycles. These are followed by writing the set- upcommand 80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. Only one sector can be erased at a time. Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The AutomaticBlock Erase begins on the rising edge ofthe last WE pulse in the command sequence and terminates when the data on SR.7 is "1". When erasing a block, the remaining unselected blocks are unaffected.During the execution of the Block Erase command, only the Erase Suspend and Erase Resume commands are allowed. The Erase Suspend/Resume command may be issued as many time as required. Similar to the Chip Erase mode, the Status Register should be checked when erase is complete. MxX291L 8000T/S 2.6 ERASE SUSPEND AND RESUME The Erase Suspend command is provided to allow the user to interrupt an erase sequence and then read data from a block other than that which is being erased. This command is applicable only during the erase operation. During the erase operation, writing the Erase Suspend command to the CIR will cause the internal state machine to pause the erase sequence at a predetermined point. The Status Register will indicate when the erase operation has been suspended. Once in erase suspend, a Read Array command can be written to the CIR in order to read data from blocks not being erase suspended. The only other valid commands during erase suspend are Erase Resume and Read Status Register commands. Read Page Buffer command, however, is not applicable during erase suspend. To resume the erase operation, the Erase Resume command 30H should be written tothe CIR. Another Erase Suspend command can be written after the chip has resumed erasing. P/N: PM0446 29-10 REV.1.4, Jan 12, 1998Tabie5. Status Register Bit Definition MxX29L 8000T/B WSMS | ESS ES PS SLP SLK 7 6 5 4 2 1 SR.7 = WRITE STATE MACHINE STATUS(WSMS) NOTE : 1 = Ready State machine bit must first be checked to determine 0 = Busy Program or Erase completion, before the Program or SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5= ERASE STATUS 1 = Error in Erase 0 = Successful Erasure SR.4= PROGRAM STATUS 1 = Error in Page/Byte Program 0 = Successful Page/Byte Program SR.2= SLEEP STATUS 1 = Device in sleep mode 0 = Device not in sleep mode SR.3=0 SR.1 = Boot sector Jock status 1: Jock, 0: unlock Others = Reserved for future enhancements Erase Status bits are checked for success. When Erase Suspend is issued, state machine halts execution and sets both WSMS and ESS bits to "1," ESS bit remains set to "1" until an Erase Resume command is issued. When this bit set to "1," state machine has applied the maximum number of erase pulses to the device andis still unable to successfully verify erasure. When this bit is set to 1, state machine has attempted but failed to program page data. When this bit is set to "1", the device is in sleep mode(deep power-down). Writing the Read Array command will wake up the device, and the device will return to standby. 2.7 STATUS REGISTER The device contains a Status Register which may be read to determine when a Program or Erase operation is complete, and whether that operation completed success- fully. The Status Register may be read at any time by writing the Read Status command to the command interface. After writing this command, all subsequent Read operations output data from the Status Register until another command is written to the command interface. A Read Array command must be written to the command interface to return to the read array mode. The Status Register bits are output on DO/0:7]. The contents of the Status Register are latched on the falling edge of OE or CE, whichever occurs last in the read cycle: This prevents possible bus errors which might occur ifthe contents of the Status Register change while reading the Status Register. CE or OE must be toggled with each subsequent status read, or the completion of a Program or Erase operation will not be evident from the Status Register. When the state machine is active, this register will indicate the status of the state machine, and will also hold the bits indicating whether or not the state machine was successful in performing the desired operation. 2.7.1 CLEARING THE STATUS REGISTER The state machine sets status bits 4 through 7 to "1", and clears bits 6 and 7 to "0", but cannot clear status bits 4 and 5to"0". Bits 4 and 5 can only be cleared by the controlling CPU through the use of the Clear Status Register command. These bits can indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The Status P/N: PM0446 REV.1.4, Jan 12, 1998 29-11MX29L8000T/B Register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Once an error occurred, the command Interface only responds to clear Status Register, Read Status Register and Read Array. To clear the Status Register, the Clear Status Register command is written to the command interface. Then, any other command may be issued to the command interface. Note, again, that before read cycle can be initiated, a Read Array command must be written to the command interface to specify whether the read data is to come from the Memory Array, Status Register, Page Buffer, or silicon ID. 2.8 SLEEP MODE The MX29L8000T/B features a sofware controlled low power modes: Sleep modes. Sleep modeis allowed during any current operations except that once Suspend command is issued, Sleep command is ignored. To activate Sleep mode, a three-bus cycle operation is required. The COH command (Refer to Table 3) puts the device in the Sleep mode. Once in the Sleep mode and with CMOS input level applied, the power of the device is reduced to deep power-down current levels. The only power consumed is diffusion leakage, transistor subthreshold conduction, input leakage, and output leakage. The Sleep command allows the device to complete its current operations before going into Sleep mode. During Sleep mode, Silicon ID codes remain valid and can still be read. The Device Sleep Status bit SR.2 will indicate that the device in the sleep mode. The device is in read SR. mode during sleep mode. Writing the Read Array command wakes up the device out of sleep mode. SR.2 is reset to "0" and device returns to standby current level. 2.9 PAGE BUFFER READ AND WRITE The MX29L8000T/B has 128 Bytes of page buffers, which can work as SRAM to store temporary data for fast access purpose. To write data into page buffers, the Write Page Buffer command is written to the CIR. There are two "untock"write cycles, followed by the command EOH. Loading data to page buffer is similar to that in Page Program. Sequential loading is not required. AO to A6 must be valid to specify byte address within the page buffers during each high-to-low transition of WE or CE. Eachnew byte to be stored must have its high-to-low transition of WE or CE within 30 us of the low-to-high transition of WE or CE of the preceding byte. Otherwise, the Write Page Buffer mode is terminated automatically. To read data from the page buffer, the Read Page Buffer command is written to the CIR. There are two "unlock" write cycles, which are followed by the command 75H. Each subsequent toggle of address (or OE, CE) will read data from the specified byte address of the page buffer (AO to A6). To terminate the operation, it is necessary to write the Read/Reset command sequence into the CIR. 3.0 DATA PROTECTION The MX29L8000T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the intemal state machine in the Read Array mode. Aiso, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. 3.1 16K-BLOCK LOCKING The MX29L8000T/B features hardware 16K-Block protection. This feature will disable both program and erase operations in the 16K-Block. The biock protection feature is enabled using system software by the user(Refer to Table 3). The device is shipped with 16K-Block unprotected. Alternatively, MXIC may protect 16K-Block in the factory prior to shipping the device. Execute lock bit protection operation three additional times after protect bit is verified successfully to guarantee lock bit status under all conditions. 3.1.1 LOCK BLOCK To activate this mode, a six-bus cycle operation is required. There are two unlock write cycles. These are followed by writing the set-up command. Two more P/N: PM0446 REV.1.4, Jan 12, 1998 29-12M=Ic unlock write cycles are then followed by the Lock Sector command 20H. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on SR.7 is 1 at which time the device stays at the read mode. 3.1.2 LOCK STATUS READ To verify the Protect status of the 16K-Block, operation is initiated by writing Silicon ID read command into the command register. Following the command write, a read cycle from address SAO2H(see Table 3) retrieves the Manufacturer code of C2H if the 16K-Block is protected. If the 16K-Block is unprotected, 00H will be read instead. To terminate the operation, it is necessary to write the Read/ Reset command sequence into the CIR. The lock status information can also be retrieved by reading SR... The SR.1 ="1" if 16K-Block is locked. The SR.1 ="0" if 16K-Block is unlocked. A few retries are required if Protect status can not be verified successfully after each operation. 3.2 HARDWARE PROTECTION Protection for parameter blocks and main blocks can be achieved using combinations of RP and WP pins. 3.2.1 RP = VIL FOR COMPLETE PROTECTION For complete data protection of all blocks, the RP can be held low. 3.2.2 WP = VIL FOR 16K-BLOCK LOCKING When WP = VIL, the 16K-block is locked, while all other blocks remain unlocked in this condition and can be programmed or erased normally. 3.2.3 WP=VHH FOR 16K-BLOCK UNLOCKING If WP = VHH, the 16K-Block is unlocked and can be programmed or erased. Note that this feature will override the 16K-Block Lock bit protection. 3.2.4 WP = VIH FOR REGULAR BLOCK UNLOCKING MxX29L 8000T/B if WP = VIH and RP = VIH, all the regular blocks (parameter blocks and main blocks) are unlocked and can be programmed or erased. In this condition, whether the 16K- Block is locked is dependent on the 16K-Block Lock bit. If the 16K-Block Lock bit is enabled, then the 16K-Block is still protected; otherwise, itis unlocked. The following truth table clearly defines the write protection methods. Table 5. WRITE PROTECTION TRUTH TABLE FOR MX29L8000T/B RP | WP | 16K-Biock |Write Protection Provided Lockout bit! 16K-Block/ Regular Block VIH | VHH Xx unlocked unlocked VIL} X x locked locked VIH| VIL X locked unlocked VIH | VIH 1 locked unlocked VIH| VIH 0 unlocked unlocked 3.3 LOW VCC WRITE INHIBIT To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO( typically 1.8V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. 3.4 WRITE PULSE PROTECTION Noise pulses of less than 5ns (typical) on CE or WE will not initiate a write cycle. "GLITCH" 3.5 LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. P/N: PM0446 REV.1.4, Jan 12, 1998 29-13M=IiIg MxX29L 8000T/B Figure 1. AUTO PAGE PROGRAM FLOW CHART START y Write Program Cmd Sequence y q Write Program Data/Address Loading End? YES 1 Read Status Register jo YES (t) YES Program Fail NG Page Program Completed | . REV.1.4, Jan 42, 1998 P/N: PM0446 29-14M=Ic Figure 2. AUTO ERASE FLOW CHART Mx29L8000T/B Write Erase Cmd Sequence Read Status Register NO NO Y Erase Completed NO To Execute YES Suspend Made ? Erase Suspend Flow (Figure 3.) P/N: PM0446 REV.1.4,Jan 12, 1998 29-15M_Ic MxX29L 8000T/B Figure 3. ERASE SUSPEND/ERASE RESUME FLOW CHART START Y Write BOH y Read Status Register YES NO Erase Completed Erase Suspended Y Write FOH ! Read Array ' Done Reading YES Y Write 30H Erase Resumed . REV.1.4, Jan 12, 1998 P/N: PM0446 29-16M=Ii MX29L8000T/B Figure 4. 16K-BLOCK PROTECTION FLOW CHART START ! Write 16K-Biock Protect Cmd Sequence ! Read Status Register YES Sector Protect Completed Figure 5. VERIFY 16K-BLOCK PROTECT FLOW CHART START ' Write Verify-Protection and Sequence y Read Protect Status Note: 1. Protect Status: Data Outputs (C2H in byte mode, 0OC2H in word mode) if block is protected(lockout bit is enabled). Data Outputs (OOH in byte mode, OOGO0H in word mode) otherwise. 2. Silicon ID can be read via this Flow Chart. Refer to Table 4. 3. SR1 also contains the lock bit information Refer to Table 5. 4.Execute lock bit protection operation three additional times after protect bit is verified successfully to guarantee lock bit status under all conditions. : REV.1.4, Jan 12, 1998 P/N: PM0446 29-17M=Ic MxX29L8000T/B 5.0 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS OPERATING RANGES RATING VALUE Ambient Temperature 0 Cto 70 C(Comm.} RATING VALUE -40 C to 85 C(ind.) Ambient Temperature -40 Cto85 C Vee Supply Voltage 2.7V to 3.6V NOTICE: T - __ Storage emperature . 65 C to 125 C _ 1.This document contains information on product in the dsign Applied Input Voltage -0.5V to VCC + 4.5 phase of development. Revised information will be published oo _ when the product is available. Applied Output Voltage -0.5V to VCC +06 2.Specifications contained within the following tables are subject to change. : WARNING: P -0.5V to 5. VCC to Ground Potential 0.5V to 5.5V Stresses greater than those listed under ABSOLUTE AS, WP -0.5V to 13.0V MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational CAPACITANCE TA= 25 C, f= 1.0 MHz sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 14 pF VIN = OV COUT Output Capacitance 16 pF VOUT = 0V SWITCHING TEST CIRCUITS DEVICE 2.7K ohm UNDER < +e wv oo 3.3 TEST CL = 50 pF for 120ns CL = 100 pF Including jig capacitance for 150/200ns 1 i i L DIODES = IN3064 6.2K ohm OR EQUIVALENT SWITCHING TEST WAVEFORMS 2.4V So ~2.0V P 0.8V 0.45V TEST POINTS ye 1.5V INPUT Input pulse rise and fall times are 5ns. AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". OUTPUT P/N: PM0446 REV.1.4, 12,1 29-18 EV.1.4, Jan 12, 1998M=Ic MX291L 8000T/B 5.1 DC CHARACTERISTICS Vcc = 2.7V to 3.6V SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS IL Input Load 1 1 uA VCC = VCC Max Current VIN = VCC or GND ILO Output Leakage 1 10 uA VCC = VCC Max Current VIN = VCC or GND ISB1 VCC Standby 1 20 30 uA VCC = VCC Max Current(CMOS) CE = VIH ISB2 VCC Standby 1 2 mA NCC = VCC Max Current(TTL) CE =VIH ICcC1 VCC Read 1 20 35 mA VCC = VCC Max Current f = 10MHz, IOUT =0 mA Icc2 VCC Erase 1,2 5 mA CE =VIH Suspend Current Block Erase Suspended ICC3 VCC Program 1 15 30 mA Program in Progress Current Icc4 VCC Erase Current 1 15 30 mA Erase in Progress {PPD VCC Deep Power-down 1 8 uA VCC = VCC Max Current RP = VIL VIL Input Low Voltage 3 -0.3 0.6 Vv VIH Input High Voltage 4 2.0 VCC+0.3 OV VOL Output Low Voltage 0.45 Vv IOL = 2.1mA, Vec = Vec Min VOH Output High Voltage 2.4 v IOH = -100uUA, Vcc = Vec Min NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.0V, T= 25 C. These currents are valid for all product versions (package and speeds). 2. |CC2 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC2 and ICC1. 3. VIL min. = -1.0V for pulse width < 50ns. VIL min. = -2.0V for pulse width < 20ns. 4. VIH max. = VCC + 1.5V for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. P/N: PM0446 REV.1.4, Jan 12, 1998 29-19M=_ Ic MxX29L8000T/B 5.2 AC CHARACTERISTICS READ OPERATIONS 291.8000T/B-12 29L8000T/B-15 291 8000T/B-20 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 420(1) 150 200 ns CE=OE=VIL tCE CE to Output Delay 120(1) 150 200 ns O=VIL tOE OE to Output Delay 60 75 100 ns CE=Vit tDF(2) OE High to Output Delay 0 55 0 55 9) 55 ns CE=VIL tOH Address to Output hold =O 0 0 ns CE=OE=VIL TEST CONDITIONS: NOTE: * Input pulse levels: 0.45V/2.4V 1. 120ns is the data while Vec = 3.3V 0.3V. When Vcc goes * Input rise and fall times: 5ns down to 2.7V, the value will be 150ns. 2. tDF is defined as the time at which the output achieves the "Output load: 1TTL gate+ 100pF (Including scope and open circuit condition and data is no longer driven. jig) (100pF loading for 150ns, 200ns read speed.) ( 50pF loading for 120ns read speed.) * Reference levels for measuring timing: 1.5V - REV.1.4, Jan 12, 1998 P/N: PM0446 29-20M=]Iic ee Mx291 8000T/B Figure 6. READ TIMING WAVEFORMS Device and Standby ; Outputs Enabled Standby address selection Data valid Vi ADDRESSES ADDRESSES STABLE Vik ; I | . VIH CE VIL | VIH OE vit VI f \ WE VIL : tOE >| | - tcE | ! . tO a DATA OUT on Men? { Data out valid Sp vou i i tacc ~ . REV.1.4, Jan 12, 1998 P/N: PM0448 29-21M=I. oa MxX291L8006T/B 5.3 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS. 29L8000T/B-12 29L8000-T/B15 29L8000-T/B20 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT tWC Write Cycle Time 120 150 200 ns tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 60 60 60 ns tDS Data Setup Time 50 50 50 ns tDH Data Hold Time 10 10 10 ns tOES Output Enable Setup Time 0 0 0 ns tCES CE Setup Time 0 0 0 ns tGHWL Read Recover Time Before Write 0 0 0 ns ics CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tWwP Write Pulse Width 60 60 60 ns tWPH Write Pulse Width High 40 40 40 ns tBALC Byte Address Load Cycle 0.2 30 0.2 30 0.2 30 us tBAL Byte Address Load Time 100 100 100 us tSRA Status Register Access Time 120 150 200 ns tCESR CE Setup before S.R. Read 100 100 100 ns tPHWL RP High Recovery to WE Going Low 1 1 1 us tVCS VCC Setup Time 2 2 2 us P/N: PM0448 REV.1.4, Jan 12, 1998 29-22=I . MxX291L 8000T/B Figure 7. COMMAND WRITE TIMING WAVEFORMS CE \ < tCH SN OE ~~ ~~ iwe ~~ . ~ WE MN !WPH \ ADDRESSES voc ~ wes ~~? - - REV.1.4, Jan 12, 1998 P/N: PM0446 29-23= MxX29L 8000T/B Figure 8. AUTOMATIC PAGE PROGRAM/WRITE PAGE BUFFER TIMING WAVEFORMS Address tiset Addres: AT-A14 55H 2AH 55H x Page Address 2"* Zit twe aad sal tBALC: {BAL __ H a _ ~- NI NS NS NSP NS NS VS twP tWPH | ; ee ate NPN SN SN SNS (CES A ce SJ VS SH - ~<a 1SRA i ? - DATA "AH 55H AOH/EO were . Data tPHWL : ad a NOTE: 1.Please refer to SECTION 2.3 for detail page program operation. **2.Page address is not required for Write Page Buffer P/N: PMO446 REV.1.4, Jan 12, 1998 29-24MI MxX29L8000T/B ana aan Figure 9. AUTOMATIC BLOCK/CHIP ERASE TIMING WAVEFORMS A0~A14 x 5555H K 2AAAH 5555H 4 5555H x 2AAAH Xo sssst ) (nn tS. tAH <_< - tCESR : anal twP _ AWPH : a -_ > <P i | | aM hy CES | OE fo Of 0S = 'DH ~~ iSRA <= &! DATA { an \{ 55H - so} AAH af 55H )aon/t0%) ("sp )}- tPHWL -=_ RP _ NOTES: *1.X" means don't care in this diagram **2."SA" means "Block Address"(required for Block Erase only) P/N: PM0446 29-25 REV.1.4, Jan 12, 1998M=Iic | MxX29L8000T/B 5.4 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS (Alternate CE Controlled) 29L8000T/B-12 29L8000T/B-15 29L8000T/B-20 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT twC Write Cycle Time 120 150 200 ns tAS Address Setup Time 10 10 10 ns tAH Address Hold Time 60 60 60 ns tDS Data Setup Time 50 50 50 ns tDH Data Hold Time 10 10 10 ns tOES Output Enable Setup Time 0 0 0 ns tCES CE Setup Time 0 0 0 ns tGHWL Read Recover TimeBefore Write 0 0 0 ns twS WE Setup Time 0 0 0 ns tWH WE Hold Time 0 0 0 ns tCP CE Pulse Width 60 60 60 ns tCPH CE Pulse Width High 40 40 40 ns tVCS VCC Setup Time 2 2 2 us . REV.1.4, Jan 12, 1998 P/N: PMO0446 29-26WE \ tWH ~~ ~ OE : ~ two ~ - CE \ ~ 1GHWL ~ ICPH \ ~ - ADDRESSES 1DS 1DH paTA DIN _ { vec _S wes - ~~ P/N: PM0446 REV.1.4, Jan 12, 1998 29-27M=I MxX<29L8000T/B ee Figure 11. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled) Byte offset ast Byte tAS tAH ae =a oad - tBALC cP tCPH! tBAL __ <> | ae SN IN IN SN SII NSS tCES o \/ iDS et tSRA _ ~ _ tOH . REV.1.4, Jan 12, 1998 PIN: PMO446 29-28M_Ic MxX29L 8000T/B 5.5 ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP. MAX. UNITS Chip/Sector Erase Time 50 ms Page Programming Time 5 ms Chip Programming Time 40 sec Byte Program Time(average) 40 us Erase/Program Cycles 100,000 Cycles 5.6 LATCHUP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. P/N: PM0446 29-29 REV.1.4, Jan 12, 1998MEIC a MxX291 8000T/B Revision History Revision # Description Date 1.1 Change from "Advance Information" to "Pretiminary. 4/14/1997 1.2 Changes Program/Erase cycles from 1,000 ta 1,000/10,000. 8/22/1997 Page 8: Table 4 "Verify 16K-block protect : A18~A2 X--->SA. 1.3 Write-Erase cycles change from 1,000/10,000 to 100,000. 10/29/1997 1.4 Adding Notes Item 8 on Page 7 to make the table more clear 01/12/1998 PIN: PMO446 REV.1.4, Jan 12, 1998 29-30