W742S819
4-BIT TELEPHONE CONTROLLER
Publication Release Date: Aug. 23, 2005
- 1 - Revision A1
Table of content-
1. GENERAL DESCRIPTION ......................................................................................................... 2
2. FEATURES................................................................................................................................. 2
3. PIN CONFIGURATION............................................................................................................... 3
4. PIN DESCRIPTION..................................................................................................................... 4
5. BLOCK DIAGRAM...................................................................................................................... 5
6. ABSOLUTE MAXIMUM RATINGS ............................................................................................. 6
7. DC CHARACTERISTICS............................................................................................................ 6
7.1 DC CHARACTERISTICS: VDD-VSS=3.0V.................................................................... 6
7.2 DC CHARACTERISTICS: VDD-VSS=3.6V.................................................................... 9
8. AC CHARACTERISTICS............................................................................................................ 9
9. APPLICATIONS INFORMATION.............................................................................................. 10
9.1 Operating Voltage......................................................................................................... 10
9.2 Drive Abilities of OP-AMPs........................................................................................... 10
9.3 FSK Signal Detection and FSK Demodulation............................................................. 10
9.3.1 FSK Signal Detection ...................................................................................................10
9.3.2 FSK demodulation........................................................................................................10
10. REVISION HISTORY................................................................................................................ 11
W742S819
- 2 -
1. GENERAL DESCRIPTION
The W742S819 is a high-performance 4-bit micro-controller (μC) that provides an LCD driver and
three OpAmps. The device contains a 4-bit ALU, two 8-bit timers, two dividers (for two oscillators) in
dual-clock operation, a 24 × 8 LCD driver, six 4-bit I/O ports (including 1 output port for LED driving),
three OpAmps(Operational Amplifiers), and one channel DTMF generator. There are also five interrupt
sources and 16-levels subroutine nesting for call subroutine or interrupt applications. The W742S819
operates on very low current and has two power reduction modes, that is the dual-clock slow
operation and STOP mode, which help to minimize po wer di ssipation.
2. FEATURES
y Operating voltage: 2.4V - 5.5V
y Dual-clock operation mode (Connect to 32768 Hz crystal only)
− Fslow oscillator : 32768Hz OSC
− Ffast oscillator : PLL ( Phase Lock Loop ) output enable
y Memory
− 12288 x 16 bits program ROM (includi ng 48K x 4 bit look-up table)
− 1536 x 4 bits data RAM (including 16 nibble s x 16 pa ges working registers)
− 24 x 8 LCD data RAM
y 24 input/output pins
− Port for input only: 1 ports/4 pins(RC)
− Input/output ports: 3 ports/12 pins(RA, RB & RD)
− High sink current output port for LED driv ing: 1 port /4 pins(RE)
− Port for output only: 1 ports/4 pins(RF)
y Power-down mode
− Hold function: no operation (excluding Fslow and Fosc oscillator)
− Stop function: no operation (Fslow a nd Fosc oscillator are stopped)
− Dual-clock slow operation mode: system is operated by 32768Hz (FOSC=Fslow and Ffast
stopped)
y Five types of interrupts
− Four internal interrupts (Div ider0, Divider1, Timer 0, Timer 1)
− One external interrupts (RC Port)
y LCD driver output
− 24 segments x 8 commons
− 1/8 duty, 1/3 bias driving mode by option code
− 16 level software LCD contrast adjusting
y MFP output pin
− Output is software selectable as modulating or non-modulating freque ncy
− Works as frequency outpu t specified by Timer 1
y DTMF output pin (PLL should be enable in this function)
− Output is one channel Dual Tone Multi-Frequency signal for dialing
y Three OpAmps(Operational Amplifiers)
− Three general purpose O pAmps with positive inputs, negative inputs and outp uts.
W742S819
Publication Release Date: Aug. 23, 2005
- 3 - Revision A1
y Two built-in 14-bit frequen cy dividers
− Divider0: the clock source is the output of the Fosc-oscillator
− Divider1: the clock source is the output of the Fslow-oscillator
y Two built-in 8-bit progra mmable countdown timers
− Timer 0: one of two internal clock freque ncies (FOSC/4 or FOSC/1024) can be selected
− Timer 1: with auto-reload function and one of three internal clock frequencies (FOSC,
FOSC/64 or Fslow) can be selected by MR1 register; and the specified frequency can be
delivered to MFP pin
y Built-in 18/15-bit watchdog timer selectable for system reset; enable the watch dog timer or not is
determined by code option
y Build-in Power-on re set detested circuit
y Powerful instr u ct ion set: 1XX instructions
y 16-levels subroutine (include interrupt) nesting
3. PIN CONFIGURATION
For W742S819 QFP 80 pin
12345678910 11 12 13 14 15 16 17 18 19
65
66
67
68
69
70
71
72
20 21 22 23 24
73
74
75
76
77
78
79
80
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
30
31
32
33
34
35
36
37
38
39
40
25
26
27
28
29
RA2
RA3
RB0
RB1
RB2
RB3
RC0
RC1
RC2
RC3
RD0
RD1
RD2
RD3
M
F
P
N
C
/
R
E
S
X
I
N
X
O
U
T
V
x
x
F
V
F
V
D
D
N
C
O
P
P
3
O
P
N
3
O
P
O
3
O
P
N
2
O
P
P
1
O
P
N
1
C
O
M
0
C
O
M
1
N
C
N
CR
E
1
R
E
2
V
S
S
S
E
G
0
N
C
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
9
S
E
G
1
0
S
E
G
1
1
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
COM6
COM5
COM4
COM3
RA1
RA0
R
E
0
COM7
S
E
G
1
2
C
O
M
2
R
F
3
R
F
2
R
F
1
R
F
0
R
E
3
D
T
M
F
T
E
S
T
O
P
O
1
O
P
P
2
O
P
O
2
W742S819
- 4 -
4. PIN DESCRIPTION
SYMBOL I/O FUNCTION
XIN I Input pin for 32.768 Hz oscillator. Con nected to 32.768 KHz crystal only.
XOUT O
Output pin for 32.768 Hz oscillator. Connected to 32.768 KHz crystal
only.
VXXF I Regulator for PLL circuit. Connected capacitor (10 uF) to VSS.
VF I Low pass filter for PLL circuit. Connected capacitor 0.022uF to VSS.
RA0-RA3 I/O
Input/Output port.
Input/output mode specified by port mode 1 register (PM1).
Internal pull-up resistors specified by RAM 7FEH(Refer to chapter 6.16.5)
RB0-RB3 I/O
Input/Output port.
Input/output mode specified by port mode 2 register (PM2).
Internal pull-up resistors specified by RAM 7FFH (Refer chapter 6.16.5)
RC0-RC3 I
4-bit port for input only.
Each pin has an independent interrupt capability.
RD0-RD3 I/O
Input/Output port.
Input/output mode specified by port mode 5 register (PM5).
RE0-RE3 O Output port only. With high sink current capacity for the LED application.
RF0-RF3 O Output port only.
MFP O
Output pin only.
This pin can output modulating or no nmodulating frequency, or Timer 1
specified frequency. It can be selected by bit 0 of BUZCR (BUZCR.0).
DTMF O This pin can output dual-tone multi frequency signal for dialing.
RES I System reset pin with low active.
SEG0-SEG23 O LCD segment output pins.
COM0-
COM7 O LCD common signal output pins.
The LCD alternating frequency can be selected by code optio n.
OPP1~3 I OpAmp1~3 positive input pins
OPN1~3 I OpAmp1~3 negative input pins
OPO1~3 O OpAmp1~3 output pins
TEST I For IC testing. Connected t o Vss in normal usage.
VDD I Positive power supply (+).
VSS I Negative power supply (-).
W742S819
Publication Release Date: Aug. 23, 2005
- 5 - Revision A1
5. BLOCK DIAGRAM
LCD
PC
STACK
(16 Levels)
RAM
(1536*4)
A
LU
Timer 0
(8 B it)
Timing G enerator
PORT
PORT
PORT
Modulation
Frequency
SEG0~SEG23 COM0~COM7
RA0-3
RB0-3
RC0-3
RD0-3
MFP
XIN
XOUT
VDD
VSS
ROM
(12288*16
(look_up table
4 8K*4 )
Timer 1
(8 B it)
A
CC
RES
Divider 0
(14 Bit)
Watch Dog
(4 B it)
HCF PEFHEFIEF
Central Control
Unit
EVF SEF
PSR0 SCR PR
MR0 MR1
. . .
PORT
MUX
SEL
+1(+2)
PORT
PM0
Divider 1
(
12/14 B it
)
RE0-3
DTMF
Generator DTMF
PM1 DTMF DTCR
PORT RF0-3
PLL
+
_
+
_
+
_
OPP1 OPN1 OPO1 OPP2 OPN2 OPO2 OPP3 OPN3 OPO3
W742S819
- 6 -
6. ABSOLUTE MAXIMUM RATINGS
PARAMETER RATING UNIT
Supply Voltage to Ground Potential -0.3 to +7.0 V
Applied Input/Output Voltage -0.3 to +7.0 V
Power Dissipation 120 mW
Ambient Operating Temperature 0 to +70 °C
Storage Temperature -55 to +150 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversel y affect the life and reliability
of the device
7. DC CHARACTERISTICS
7.1 DC CHARACTERISTICS: VDD-VSS=3.0V
(VDD-VSS = 3.0 V, Ffast = 3.6042MHz, Fslow = 32.768 KHz, Ta = 25° C, LCD on; Power-on reset circuit active, unless
otherwise specified)
PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT
Op. Voltage VDD - 2.4 - 5.5 V
Op. Current (Crystal type) IOP1
No load (Ext-V)
All OpAmps disabled
In dual-clock normal
operation.
- 0.7 1.0 mA
Op. Current (Crystal type) IOP3
No load (Ext-V)
All OpAmps disabled
In dual-clock Fslow
operation and Ffast is
stopped
- - 65
μA
Op. Current (Crystal type) IOP4
No load (Ext-V)
All OpAmps enabled
In dual-clock Fslow
operation and Ffast is
stopped
- - 75
μA
Hold Current (Crystal type) IHM1
Hold mode No load
(Ext-V)
All OpAmps disabled
In dual-clock normal
operation
- - 450
μA
W742S819
Publication Release Date: Aug. 23, 2005
- 7 - Revision A1
DC CHARACTERISTICS: VDD-VSS=3.0V, continued
PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT
Hold Current (Crystal type) IHM3
Hold mode No load
(Ext-V)
All OpAmps disabled
In dual-clock Fslow
operation and Ffast is
stopped
- 31 45 μA
Hold Current (Crystal type) IHM4
Hold mode No load
(Ext-V)
All OpAmps enabled
In dual-clock Fslow
operation and Ffast is
stopped
- 65 75 μA
Stop Current (Crystal type) ISM1
Stop mode No load
(Ext-V)
All OpAmps disabled
LCD driver should be
turned off
- 8 12
μA
Input Low Voltage VIL - VSS - 0.3VDD V
Input High Voltage VIH - 0.7VDD - VDD V
MFP Output Low Voltage VML IOL = 3.5mA - - 0.4 V
MFP Output High Voltage VMH IOH = 3.5mA 2.4 - - V
MFP Sink Current IML VOL = 0.9V 9 - - mA
Port RA, RB and RD Output
Low Voltage VABL IOL = 2.0mA - - 0.4 V
Port RA, RB and RD Output
high Voltage VABH IOH = 2.0mA 2.4 - - V
LCD Supply Current ILCD All Seg. ON - - 45 μA
SEG0-SEG31 Sink Current
(Used as LCD output) IOL1 VOL = 0.4V
VLCD = 0.0V 90 - - μA
SEG0-SEG31 Drive Current
(Used as LCD output) IOH1 VOH = 2.4V
VLCD = 3.0V 90 - - μA
Port RE Sink Current IEL VOL = 0.9V 9 - - mA
Port RE Source Current IEH VOH = 2.4V 0.4 1.2 - mA
DTMF Output DC level VTDC RL=5KΩ, VDD=2.5 to
3.8V 1.1 - 2.8 V
W742S819
- 8 -
DC CHARACTERISTICS: VDD-VSS=3.0V, continued
PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT
DTMF Distortion THD RL=5KΩ, VDD=2.5 to
3.8V - -30 -23 dB
DTMF Output Voltage VTO Low group, RL=5KΩ 130 150 170 mVrms
Pre-emphasis Col/Row 1 2 3 dB
DTMF Output Sink Curre nt ITL VTO=0.5V 0.2 - - mA
Pull-up Resistor RC Port RC 100 350 1000 KΩ
Pull-up Resistor RA Port RA 100 350 1000 KΩ
Pull-up Resistor RB Port RB 100 350 1000 KΩ
Input Leakage
Current IIN Vss≤VIN ≤VDD - - 1
μA
Input Resistance RIN 10 - -
MΩ
Input Offset Voltage VOS - - 25 mV
OP-
AMPs
Power Supply
Rejection Ratio PSRR 1KHz 0.1VPP ripple on
VDD 40 - - dB
Maximum
Capacitive Load CL - - 30 pF
OP1 Minimum Resistive
Load RL 500 - -
KΩ
Maximum
Capacitive Load CL - - 20 pF
OP2
OP3 Minimum Resistive
Load RL 1000 - -
KΩ
W742S819
Publication Release Date: Aug. 23, 2005
- 9 - Revision A1
7.2 DC CHARACTERISTICS: VDD-VSS=3.6V
(VDD-VSS = 3.6 V, Ffast = 3.6042MHz, Fslow = 32.768 KHz, Ta = 25° C, LCD on; Power-on reset circuit active, unless
otherwise specified)
PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT
Op. Current
(Crystal type) IOP1 No load (Ext-V)
All OpAmps disabled
In dual-clock normal ope ration. - 0.8 1.0 mA
Op. Current
(Crystal type) IOP3
No load (Ext-V)
All OpAmps disabled
In dual-clock Fslow operation and
Ffast is stopped
- - 65
μA
Op. Current
(Crystal type) IOP4
No load (Ext-V)
All OpAmps enabled
In dual-clock Fslow operation and
Ffast is stopped
- - 85
μA
Hold Current
(Crystal type) IHM1 Hold mode No load (Ext-V)
All OpAmps disabled
In dual-clock normal ope ration - - 450
μA
Hold Current
(Crystal type) IHM3
Hold mode No load (Ext-V)
All OpAmps disabled
In dual-clock Fslow operation and
Ffast is stopped
- 34 45 μA
Hold Current
(Crystal type) IHM4
Hold mode No load (Ext-V)
All OpAmps enabled
In dual-clock Fslow operation and
Ffast is stopped
- 75 85 μA
Stop Current
(Crystal type) ISM1 Stop mode No load (Ext-V)
All OpAmps disabled
LCD driver should be turned off - 8 12
μA
8. AC CHARACTERISTICS
PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT
Op. Frequency FOSC Crystal type - 32768 - KHz
PLL Frequency Ffast PLL enable - 3.6042 - MHz
Instruction cy cle time TI One machine cycle - 4/FOSC - S
Reset Active Width TRAW FOSC=32.768 KHz 1 - - μS
Interrupt Active Width TIAW FOSC=32.768 KHz 1 - - μS
W742S819
- 10 -
9. APPLICATIONS INFORMATION
9.1 Operating Voltage
The chip can be operated from 2.4V-5.5V. If users have much consideration for low power operation,
lower voltage supply system can be a better choice.
9.2 Drive Abilities of OP-AMPs
The OP-AMPS have 2 types according to their drive abilities. OP2 and OP3 have weaker drive
abilities than which OP1 does, so OP2 and OP3 are provided for driving input port like RC.n.
9.3 FSK Signal Detection and FSK Demodulation
9.3.1 FSK Signal Detection
Figure 10-1 is a typical application circuit for FSK signal detection and FSK demodulation. For p urpose
of signal detection, user should enable both OP1 and OP2, output low to control and sense the signal
by RC.n.
9.3.2 FSK demodulation
For purpose of FSK demodulation, user should enable both OP1 and OP2, output high to control, and
sense the FSK signal by RC.n. and demodulate FSK by software.
Figure 9-1 Application Circuit for FSK Signal Detection and FSK demodulation
W742S819
Publication Release Date: Aug. 23, 2005
- 11 - Revision A1
10. REVISION HISTORY
VERSION DATE PAGE MODIFICATION
A1 Aug. 23, 2005 - Initial data
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
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severe property or envi ronmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
