© Semiconductor Components Industries, LLC, 2008
February, 2008 - Rev. 8
1Publication Order Number:
NIS5102/D
NIS5102
High Side
SMART HotPlugt IC/Inrush
Limiter/Circuit Breaker
The NIS5102 is a controller/FET IC that saves design time and
reduces the number of components required for a complete hot swap
application. It is designed for +12 V applications.
This chip includes a time delay for sequencing applications. It has a
dual function OVLO pin that allows multiple units to be ganged
together for simultaneous turn-on and shutdown, allowing units to be
operated in parallel. It allows for user selectable undervoltage and
overvoltage lockout levels. Its unique current limit circuit allows for
adjustable current limit levels with no external power resistor. An
internal temperature limiting circuit greatly increases the reliability of
this device.
Features
•Integrated Power Device
•Power Device Thermally Protected
•No External Current Shunt Required
•Simultaneous Shutdown and Startup for Parallel Operation
•Enable/Timer Pin
•Power Good
•9.0 to 18 V Input Range
•10 mW
•Main/Mirror MOSFET Current Ratio 1000:1
•Pb-Free Packages are Available
Typical Applications
•High Availability Systems
•Electronic Circuit Breaker
•12 V Distributed Architecture
x = 1 or 2
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb-Free
5102QPxH
AWLYWWG
1
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12 PIN PLLP, 9x9 mm
CASE 488AB
MARKING
DIAGRAM
ÎÎ
Î
ÎÎ
Î
Î
Device Package Shipping†
ORDERING INFORMATION
NIS5102QP1HT1
(Latchoff)
9x9 mm
12 Pin PLLP
1500/Tape & Reel
NIS5102QP1HT1G
(Latchoff)
12 Pin PLLP
(Pb-Free)
1500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
PIN CONNECTIONS
12
11
10
9
8
7
1
2
3
4
5
6
13
(Bottom View)
NIS5102QP2HT1
(Auto-Retry)
9x9 mm
12 Pin PLLP
1500/Tape & Reel
NIS5102QP2HT1G
(Auto-Retry)
12 Pin PLLP
(Pb-Free)
1500/Tape & Reel
NIS5102
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2
13
UVLO
2
1
5
Source
10, 11, 12
GND
4
7
3
Figure 1. Block Diagram
Charge
Pump
Current
Limit
Voltage
Regulator
Thermal
Shutdown
Undervoltage
Lockout
Power
Good
Common
Shutdown
Overvoltage
Shutdown
Enable/
Timer
Enable/Timer
Ccharge
VCC
Power Good
OVLO
Current Limit
6
PIN FUNCTION DESCRIPTION
Pin Function Description
1 OVLO The overvoltage shutdown point is programmed by a resistor from this pin to the VCC supply. When
tied together with other devices, this pin also communicates a shutdown state due to undervoltage
and overtemperature reasons. All devices connected will simultaneously shutdown. Startup for this
condition may be simultaneous or sequenced.
2 UVLO A resistor from VCC to the UVLO pin adjusts the voltage at which the device will turn on.
3 Enable/Timer A high level signal on this pin allows the device to begin operation. Connection of a capacitor will
delay turn on for timing purposes. A low input signal inhibits the operation, and communicates to any
other paralleled devices (via the OVLO pin) to shutdown. This signal can also be used to reset the
thermal latch.
4Ground Negative input voltage to the device. This is used as the internal reference for the IC.
5 Ccharge An external capacitor is required from this pin to the source pin. This is the storage capacitor for the
internal charge pump. A small internal capacitor is included for noise filtering.
6 ILIMIT A resistor (RLIMIT) tied from this pin to the source pin sets the current limit level.
7Power Good A high impedance signal on this pin indicates that the power device is conducting.
8, 9 No Connection -
10, 11, 12 Source Source of power FET, which is also the switching node for the load.
13 VCC Positive input voltage to the device.
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3
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol Value Unit
Input Voltage, Operating, Steady-State (Input + to Input -) Vin -0.3 to 18 V
Input Voltage, Operating, Transient (Input + to Input -), 1 second Vin -0.3 to 25 V
Drain Voltage, Operating, Steady-State (Drain to Input -) VDD -0.3 to 18 V
Drain Voltage, Operating, Transient (Drain to Input -), 1 second VDD -0.3 to 25 V
Drain Current, Peak IDpk 20 A
Continuous Current (TA = 25°C, 0.5 in2 pad) IDavg 10 A
Voltage on Power Good Pin (Pin 7) Vmax7 20 V
Thermal Resistance, Junction-to-Air
0.5 in2 Copper
1 in2 Copper
QJA 76.5
41.2
°C/W
°C/W
Thermal Resistance, Junction-to-Lead QJL 3.2 °C/W
Power Dissipation (TA = 25°C, 0.5 in2 pad) Pmax 1.4 W
Operating Temperature Range (Note 1) TJ-40 to 175 °C
Non-Operating Temperature Range TJ-55 to 175 °C
Lead Temperature, Soldering (10 Sec) TL235 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temperature as
specified.
ELECTRICAL CHARACTERISTICS (VCC = 12 V, RLIMIT = 36 W, CCharge = 100 pF, TJ = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
POWER FET
Delay Time (Enable High to IS = 100 mA) Tdly - 2.0 - ms
Charging Time (IS = 100 mA to IS = 5.0 A, RLIMIT = 36 W)tchg - 1.0 - ms
ON Resistance (VCC = 12 V, IS = 5.0 A) (Note 2) RDSon - 10 13 mW
Zero Gate Voltage Drain Current
(VDS = 12 Vdc, VGS = 0 Vdc)
IDSS1 - - 10 mA
Zero Gate Voltage Drain Current
(VDS = 18 Vdc, VGS = 0 Vdc)
IDSS2 - - 100 mA
Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 10 kHz) - - - - pF
THERMAL LIMIT
Shutdown Temperature (Note 3) TSD 125 135 145 °C
Hysteresis (Note 3) Thyst - 40 - °C
OVER/UNDERVOLTAGE
UVLO Turn-on (Input + Increasing, RextUVLO = 620 k) Von 10.05 11.15 12.30 V
UVLO Hysteresis (Input + Decreasing, RextUVLO = 620 k) Vhyst 0.45 0.62 0.75 V
OVLO Turn-off (Input + Increasing, RextUVLO = 620 k) Voff 14.0 16.4 19.0 V
OVLO Hysteresis (Input + Decreasing, RextUVLO = 620 k) Vhyst 0.6 0.78 1.0 V
PARALLEL SHUTDOWN (Alternate Function on OVLO Pin)
Device Fan-out (Minimum External Resistor Value = 2.0 kW (Note 3) Nfan - - 4.0 Devices
Shutdown Voltage Threshold (OVLO Pin) VSD 0.6 0.8 - V
Shutdown State Output Voltage (Isink = 2.0 mA) Vlow - 0.3 0.4 V
2. Pulse Test: Pulse width 300 ms, duty cycle 2%.
3. Verified by design.
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ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V, RLIMIT = 36 W, CCharge = 100 pF, TJ = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
CURRENT LIMIT
Current Limit (Short Circuit, RLIMIT = 36 W)ILIM1 3.8 4.8 5.8 A
Current Limit (Overload, RLIMIT = 36 W) (Note 3) ILIM2 7.0 7.8 8.6 A
ENABLE/TIMER
Enable Voltage (Turn-On) VENon 2.2 - - V
Enable Voltage (Turn-Off) VENoff - - 1.6 V
Charging Current (Into External Capacitor) ICharge 65 77 88 mA
Turn-on Delay (Time from Enable High to Isource = 100 mA) tdelay - 2.2 - ms
CHARGE PUMP
CCharge (Voltage on Pin 5 with Respect to Ground)
VCC = 18 Vdc
VCcharge -
-
18
26
-
-
V
V
POWER GOOD
Power Good → High Z Signal when FET is Fully Enhanced - - - - -
Low Z State Output Voltage (ISink = 2 mA) Vpin7 - 230 300 mV
Leakage Current (Vpin7 = 12 V, High Z State) ILeak - 2.0 10 mA
Power Good Delay
(Time from Power FET is Fully Enhanced to Power Good FET Changing State)
tpwrgood - 15 - ms
TOTAL DEVICE
Bias Current (Operational, VCC = 12 V) IBias - 1.3 2.0 mA
Bias Current (Non-operational, VCC = 7 V)) IBias - 400 700 mA
Minimum Operating Voltage Vccmin - 8.5 9.0 V
Enable/Timer
Input
Threshold
Source Voltage
Output Current
Figure 2. Timing Diagram for External Enabled Delay
NIS5102
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0.1
1
10
100
10 100 1000
100 200 300 400 500 600 700 800 900 1000
UVLO TRIP POINT (V)
Figure 3. UVLO Adjustment Figure 4. OVLO Adjustment
RUVLO (kW)
19
Figure 5. Current Limit Adjustment
Overload
ILimit (A)
RILmit (W)
8
9
10
11
12
13
14
1000500 900
Turn-on
Turn-off
18
17
16
15
14
13
12
11
10
9
OVLO TRIP POINT (V)
ROVLO (kW)
Turn-on
Turn-off
Short Circuit
200 300 400 600 700 800
0.01
0.1
1
10
10 100 10000
Figure 6. Current Limit vs. Temperature for
182W
di/dt (A/ms)
LOAD CAPACITANCE (mF)
Vin = 12 V
Rext_ILimit = 100 W
1000
Figure 7. Load Capacitance vs. Output di/dt
105
95
85
75
65
55
45
35
25 13119.07.05.03.01.0
CONTINUOUS CURRENT, A
CASE TEMPERATURE, °C
1/4 sq in copper area
1 sq in copper area
2 sq in copper area
TYPICAL PERFORMANCE CURVES
(TA = 25°C unless otherwise noted)
Device Reaching
Thermal Shutdown
CURRENT (A)
Figure 8. Continuous Current vs. Case Temperature
(Test performed on a double-sided copper board, 1 oz)
TJ, JUNCTION TEMPERATURE, (°C)
4
6
8
10
12
9004010 20 30 50 70 8060
0
2
Overload
Short Circuit
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UVLO Trip Point, Volts
TYPICAL PERFORMANCE CURVES
(TA = 25°C unless otherwise noted)
RDS(on), (mW)
Figure 9. Typical RDS(on) vs. Junction
Temperature
TJ, JUNCTION TEMPERATURE, (°C)
4
6
8
10
12
14
16
125565-40 -25 -10 20 35 50 11080 95
0
2
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TYPICAL APPLICATION CIRCUITS AND OPERATION WAVEFORMS
(TA = 25°C unless otherwise noted)
Figure 10. Current Waveforms for Overload, Short Circuit and Thermal Shutdown
+
Gnd
En/Timer
VCC
OVLO
UVLO
Power Good
Source
Figure 11. Typical Applications Circuit
+
C
Ccharge
RUVLO
ROVLO
Cdelay
DC-DC
Converter
Figure 12. Turn-on Waveforms for 3300 mF Load
Capacitors
Figure 13. Turn-on Waveforms for Shorted
Output, Latchoff Device
Ccharge
Current
Limit
RLIMIT
Input Voltage
GND
Output Current
Output Voltage
Power
Good
Power Good
Delay
Turn on
Delay
Input Voltage
Output Current
Output Voltage
Device Reaching
Thermal Limit
20 ms/div
(2 V/div)
(2 A/div)
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TYPICAL APPLICATION CIRCUITS AND OPERATION WAVEFORMS (continued)
(TA = 25°C unless otherwise noted)
Input Voltage
Output Current
Output Voltage
Device Reaching
Thermal Limit
Power Good
Input Voltage
Output Current
Output Voltage
Device Reaching
Thermal Limit
Power Good
Input Voltage
Output Current
Overvoltage
condition
Output Voltage
Power Good
Input Voltage
Output Current
Overvoltage
Condition
Output Voltage
Power Good
Figure 14. Turn-On Waveforms for Shorted Output,
Auto-Retry Device
Figure 15. Device Response During an Overvoltage
Condition
NIS5102
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+
Gnd
En/Timer
VCC
OVLO
UVLO
Power Good
Source
+
+
Ccharge
RUVLO
ROVLO
Cdelay2
DC-DC
Converter
DC-DC
Converter
Ccharge
Cdelay1
Figure 16. Turn-on Sequencing Using Power Good Signal
RUVLO
ROVLO
+
+
Gnd
VCC
OVLO
UVLO
Power Good
Ccharge
En/Timer
Ccharge
ROVLO
RUVLO
DC-DC
Converter
Figure 17. Parallel Operation / Simultaneous Turn-on and Shutdown
Current
Limit
RLIMIT
Gnd
En/Timer
VCC
OVLO
UVLO
Power Good
Source
Ccharge
Current
Limit
RLIMIT
Cdelay
Source
Current
Limit
RLIMIT
Gnd
VCC
OVLO
UVLO
Power Good
En/Timer
Ccharge
Source
Current
Limit
RLIMIT
RUVLO
Ccharge
Figure 18. Turn-on Waveforms for Parallel Operation
Input Voltage
Output Voltage
Iout, Device1
Iout, Device2
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OPERATING DESCRIPTION
Operation
The NIS5102 has a variety of shutdown and protection
features that make this part extremely versatile as well as
rugged. For the unit to operate, the input voltage must be
within the operating range of the part which is set by the
UVLO and OVLO bias resistors. The enable must also be
high for operation. Current and thermal limit circuits
constantly monitor the operation and will protect the unit if
either of these parameters exceeds its preset limit.
An additional shutdown method, is the use of the OVLO
pin, which can be tied in parallel. This allows multiple units
to be either operated in parallel, and will shutdown and turn
on simultaneously for any fault other than an overvoltage, or
it allows these hot plug devices to control independent loads,
and shutdown and turn on simultaneously.
Faults
Once the load capacitance is charged, the SENSEFETt
will become fully enhanced as long as the current does not
reach the current limit threshold, or is shutdown due to an
overvoltage, undervoltage or thermal fault. Both the UVLO
and OVLO circuits incorporate hysteresis to assure clean
turn-on and turn-offs with no chatter. The thermal latching
circuit will require the input power to be recycled to resume
operation after a fault. The current limit is always active, so
any transient or overload will always be limited.
Circuit Description
Enable/Timer
The enable/timer pin can function either as a direct enable
pin, or as a time delay. In the enable mode, an open collector
device is connected to this pin. When the device is in its low
impedance mode, this pin is low and the operation of the chip
is disabled. If a time delay is required, a capacitor is added
to this pin. Figure 19 shows the equivalent circuit for the
enable.
Figure 19. Enable/Timer Circuit
Enable/
Timer
80 mA
-
+
2.2 V
Enabled
NIS5102
If a capacitor is added without an open collector device,
the turn on will be delayed from the time at which the UVLO
voltage is reached. If an open collector device is also used,
the delay will start from the time that it goes into its high
impedance state. The capacitor is charged by an internal
current source.
There is an inherent delay in the turn on of the hot plug
device, due to the method of gate drive used. The gate of the
power FET is charged through a high impedance resistor,
and from the time that the gate starts charging until the time
that it reaches its threshold voltage, there will be no
conduction. Once the gate reaches its threshold voltage, the
output current will begin a controlled ramp up phase.
This delay will be added to any timing delay due to the
enable/timer circuit.
Power Good
The power good circuit monitors the VGS voltage of the
power SENSEFET and compares it with the output voltage
of the internal charge pump. Once the VGS of the power
SENSEFET reaches around 90% of the internal charge
pump output voltage, the power good will change its state
from low impedance to high impedance but only after the
power good delay has elapsed. Figure 12 shows the power
good behavior during the startup of the NIS5102 device, an
external pullup resistor from power good to VCC was used.
The power good will change its state from high impedance
to low impedance in the event of any fault condition such as
short circuit and overvoltage.
Undervoltage Lockout
The UVLO circuit holds the chip off when the input
voltage is less than the turn-on limit. It includes internal
hysteresis to assure clean on/off switching. An internal
divider sets the turn-on voltage level at 16 V. This voltage
can be reduced by adding an external resistor from the
UVLO pin to the VCC pin. The equivalent circuit is shown
in Figure 20.
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11
VCC
RUVLO
400 k
UVLO
VGS(th) = 1.15 V
40 k
3 k
Ground
Source
Figure 20. Equivalent Undervoltage Lockout Circuit
Current
Limit
The theoretical equation for the UVLO turn-on voltage is:
RUVLO(KW)+400Vin *460
17.5 *Vin
The UVLO trip point voltage calculated through the
theoretical formula may show small variations with respect
to Figure 3, therefore it is recommended to use the formulas
gotten from the UVLO characterization, which are shown
below:
RUVLO(kW)+e[(UVLO )14.647)ń3.9858]; for TJ+25°C
where “UVLO” is the desired undervoltage lockout value,
and RUVLO is the programming resistor from the UVLO pin
to the VCC pin.
To reduce nuisance tripping due to transients and noise
spikes, a capacitor may be added from the UVLO pin to
ground. This will create a low pass filter with a cutoff
frequency of f. The required capacitance on this pin is:
CUVLO +1
2p·fƪ43K )ǒRUVLO·400K
RUVLO)400KǓƫ
Overvoltage Lockout and Parallel Shutdown
The overvoltage lockout (OVLO) is a dual function pin.
This pin will normally be biased somewhere between
ground and the input voltage, due to an internal voltage
divider which sets the turn-off voltage level at 22 V. This
voltage level can be reduced by adding an external resistor
from the OVLO pin to the VCC pin. When the input voltage
reaches the programmed trip point, operation of the device
is inhibited.
Figure 21 shows the equivalent circuit.
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12
VCC
ROVLO
300 k
OVLO
200 k
Ground
Source
Figure 21. Equivalent Overvoltage Lockout Circuit
2 M
7 V
The theoretical equation for the OVLO turn-on voltage is:
ROVLO(KW)+300Vin *2100
21.8 *Vin
The OVLO trip point voltage calculated through the
theoretical formula may show small variations with respect
to Figure 4, therefore it is recommended to use the formulas
gotten from the OVLO characterization, which are shown
below:
ROVLO(kW)+e[(OVLO )5.2)ń3.46]; for TJ+25°C
where “OVLO” is the desired overvoltage lockout value,
and ROVLO is the programming resistor from the OVLO pin
to the VCC pin.
To reduce nuisance tripping due to transients and noise
spikes, a capacitor may be added from the OVLO pin to
ground. This will create a low pass filter with a cutoff
frequency of f. The required capacitance on this pin is:
COVLO +[1 )(8.83E-6·ROVLO)]
2p·f·ROVLO
This pin is also used as a common shutdown pin. In this
mode, if this pin is pulled to ground, it will shutdown the chip
and all chips connected to its OVLO pin.
The OVLO pin has an internal switch to ground that will
pull it low, whenever the device is disabled due to any fault
other than an Overvoltage condition. An enable pin
shutdown is not considered a fault and will not cause a
common shutdown. This feature allows multiple units to
turn on and off simultaneously by tying the OVLO pins
together in parallel. This can be used for operating several
hot plug devices in parallel, or for use with separate loads,
when all devices need to startup and shutdown
simultaneously.
Temperature Limit
The temperature limit circuit senses the temperature of the
Power FET and removes the gate drive if the maximum level
is exceeded. For the auto-retry device, there is a nominal
hysteresis of 40°C for this circuit. After a thermal shutdown,
the device will automatically restart when the temperature
drops to a safe level as determined by the hysteresis. The
latching thermal circuit can be reset either by recycling the
input power, or by toggling the enable signal.
Current Limit
An external resistor from the current limit pin to the source
pins set the level at which the device will limit the current.
The plot of resistance vs. current limit includes two curves,
one for short circuit and one for overload.
A short circuit condition is one in which the SENSEFET
is not fully enhanced, and is therefore in a high impedance
mode of operation. In this case there are many hundreds of
millivolts across the drain to source pins of the SENSEFET.
This occurs when the output sees a very low impedance short
as well as when the capacitor is charging at turn on. In both
cases there are several volts or more across the FET.
An overload condition is one in which the SENSEFET is
still fully enhanced and the drain to source voltage is the
product of the drain current and the on resistance of the FET.
The sense voltage out of the SENSEFET has a different
relation to the drain current in these two conditions. The
difference in current limit levels for these two cases is called
DI, where:
DI+VrefńRDSon
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13
For this equation, Vref is the reference voltage of the
current limit circuit, and RDSon is the on resistance of the
SENSEFET. For more information on this, see application
note AND8140/D, “SMART HotPlugt Current Limit
Function”.
This inherent property of the SENSEFET allows for
simple dual level current limiting, in which a short circuit
condition will see a lower level of limiting than will an
overload. This operation will exist in start up as well as under
normal operation, so the device will be able to differentiate
between a short and an overload.
As with all SMART HotPlug devices, the current limit will
never shutdown the device. Only the thermal limit will stop
the flow of current to the load. Once the current is stopped due
to the thermal limit, it will remain off until input power is
recycled for the latching version, or it will continuously retry
to start again if it is the auto-retry version.
The ILimit graph shown in Figure 5 was generated from
the data of the ILimit characterization, the formula for the
short circuit curve is:
RILimit(W)+ǒ152.86
ILimit Ǔ1.02
for TJ+25°C
where “ILimit” is the desired short circuit ILimit value, and
RILimit is the programming resistor from the ILimit pin to the
source pin.
Turn-on Surge
During the turn-on event, there is a large amount of
energy dissipated due to the linear operation of the power
device. The energy rating is the amount of energy that the
device can absorb before the thermal limit circuit will shut
the unit down. This is very important specially for the latch
off device as it determines the maximum load capacitance
that the device can charge before the thermal limit shuts the
device down. The calculation of this is not very simple as it
depends on several factors such as the input voltage (Vin),
load capacitance (CL), current limit settings (ILimit) and
device's thermal transient response, therefore, it is
recommended to do lab evaluations for these purposes.
Figure 22 shows the device's thermal transient response for
minimum pad.
0.1
1
10
100
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
TIME (seconds)
THETA J(t) (°C/W)
Figure 22. Thermal Transient Response
1-in Pad
Min Pad
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PACKAGE DIMENSIONS
PLLP-12, 9x9 mm
CASE 488AB-01
ISSUE C
SOLDERING FOOTPRINT*
9.305
12 X
5.652 1.054 12 X
0.551
7.652
1.270 PITCH
Dimensions in mm
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLE 1:
PIN 1. OVLO
2. UVLO
3. ENABLE/TIMER
4. GND
5. CCHARGE
6. CURRENT LIMIT
7. POWER GOOD
8. N/C
9. N/C
10. SOURCE
11. SOURCE
12. SOURCE
DIM MIN MAX
MILLIMETERS
A1.750 1.950
A1 0.000 0.050
A3 0.254 REF
b0.400 0.600
D9.000 BSC
E9.000 BSC
e1.270 BSC
D2 5.400 5.600
E2 7.400 7.600
K0.850 REF
L0.850 0.950
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. COPLANARITY APPLIES TO THE LEAD,
DIMENSION B, AND EXPOSED PAD.
D
E
B
A
4 X
PIN ONE
SEATING
LOCATION
0.08 C
0.15 C
Î
Î
Î
Î
Î
Î
Î
D2
E2
b
K
12 X
L12 X
10 X e
e/2
12 X
A
M
0.10 BC
M
0.05 C
TOP VIEW
BOTTOM VIEW
SIDE VIEW
(A3)
A1
A
C
0.10 C
PLANE
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NIS5102/D
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