71M6511-IGTR/F - Hytronics - Product.Network

71M6511/71M6511H

Single-Phase Energ y Meter IC

DATA SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

GENERAL DESCRIPTION

The 71M6511 is a highly integrated SOC with an MPU core, RTC, flash,

and LCD driver. Our Single Converter Technology® with a 22-bit delta-

sigma ADC, three analog inputs, digital temperature compensation,

prec i si o n v olt a g e r ef er enc e, and 32-bit computation engine (CE) supports a

wide range of single-phase metering applications with very few low cost

external components. A 32kHz crystal time base for the entire system and

internal battery backup support for RAM and RTC further reduce system

cost.

Maximum design flexibility is supported with multiple UARTs, I2C, a power

fail comparator, a 5V LCD charge pump, up to 12 DIO pins and an in-

system programmable flash. The device is offered in high (0.1%) and

standard (0.5%) accuracy versions for multifunction

residential/commercial meter applications requiring multiple

voltage/curr ent inputs and com plex LCD or DIO configurations.

A com plete array of ICE and development tools, programming li braries and

reference designs enable rapid development and certification of meters that

m eet most dem anding worldwide electr icity metering standards.

MPU

RTC

TIMERS

XIN

XOUT

VREF

COM0..3

V3.3A V3.3D

VBAT

V2.5

VLCD

VBIAS

VDRV

SEG0..19

GNDA GNDD

SEG 24..32

DIO 0..11

SEG 32..41

DIO 12..21

ICE

LOAD

88.88.8888

EEPROM

POWER

FAULT

AMR

TEST PULSES

BATTERY

COMPARATOR

SENSE

DRIVE

SERIAL PORTS

OSC/PLL

CONVERTER

LCD DRIVER

DIO, PULSE

COMPUTE

ENGINE

FLASH

RAM

VOLTAGE REF

REGULATOR

5V BOOST

POWER SUPPLY

TERIDIAN

71M6511

3V/5V LCD

TEMP

SENSOR

V or I

32 kHz

LIVE

NEUT

CT/SHUNT

7/20/2007

FEATURES

 W h accuracy < 0.1% over 2000:1

range

 Exceeds IEC 62053/ANSIC 12.20

 Vol tage reference

< 10ppm /°C -- 71M6511H,

< 50ppm /°C -- 71M6511

 Three sensor inputs - VDD referenced

 Low j itt er Wh/VA Rh pulse outputs

 Pul se count for pul se outputs

 Four-quadrant metering

 Vol tage/curr ent angle

 Line frequency count for RTC

 Digital temperature compensation

 Sag detec tion

 Independent 32-bit com pute engine

 40-70Hz l ine fr equenc y r ange with

same calibration

 Phase com pensation (±7°)

 Battery backup for RAM and RTC

 22mW at 3.3V, 7. 2µW backup

 Flash memor y option with security

 22-bit delta-s igma ADC

 8-bit MPU (80515) - 1 clock cycle per

instruction

 LCD driver (≤ 128 pixels)

 High speed SSI serial output

 RTC for time-of-use functions

 Hardware watchdog timer

 Up to 12 general-purpose I/O pi ns

 64KB flash, 7KB RA M

 Two UARTs for IR and AMR

 64-lead LQFP package

19-5359; Rev 11/10

Single Converter Technology is a registered trademark of

Max im Inte grated Pr oducts , Inc .

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Table of Contents

GENERAL DESCRIPTION ..................................................................................................................................... 1

FEATURES ............................................................................................................................................. 1

HARDWARE DESCRI P TION ................................................................................................................................. 8

Hardware Overview .................................................................................................................................. 8

Analog Front End (AFE) ........................................................................................................................... 8

Multiplexer.................................................................................................................................. 8

ADC ........................................................................................................................................... 9

FI R Filter .................................................................................................................................... 9

Volta ge Refer ence ...................................................................................................................... 9

Temp erature Sens or ................................................................................................................... 10

Functional Description ................................................................................................................ 10

Computa ti on Engi ne (CE) ......................................................................................................................... 11

Meter Equations ......................................................................................................................... 12

Pulse Generator ......................................................................................................................... 12

Real-Tim e Monitor ...................................................................................................................... 13

CE Functiona l Overvie w ............................................................................................................. 13

80515 MPU Core ..................................................................................................................................... 15

80515 Overvie w ......................................................................................................................... 15

Me mory Organiz ation ................................................................................................................. 15

Special Function Registers (SFRs) .............................................................................................. 17

Special Function Registers (Generi c 80515 SFRs) ...................................................................... 18

Special Function Registers Specifi c to the 71M6511 .................................................................... 20

Instruction Set ............................................................................................................................ 21

UART ......................................................................................................................................... 21

Timers and Co unter s .................................................................................................................. 24

W D Timer (Software W atchdog Timer) ........................................................................................ 26

Interrupts .................................................................................................................................... 29

Ex ternal Interrupts ...................................................................................................................... 32

Interru pt P r iority L evel Structure .................................................................................................. 34

Interru pt S our ces and Vectors ..................................................................................................... 35

On-Chip Resour ces .................................................................................................................................. 37

DIO Ports ................................................................................................................................... 37

Physical Mem ory ........................................................................................................................ 38

Oscillator .................................................................................................................................... 39

Real-Time Clock (RTC)............................................................................................................... 40

LCD Dri v ers ............................................................................................................................... 40

LCD Voltage Boost Circui try........................................................................................................ 41

UART ( UART0) and O pti cal Port (UA RT1) ................................................................................... 41

Hardware Reset Mechanisms ..................................................................................................... 42

Reset Pin (RESETZ)................................................................................................................... 42

Hardware Watchdog T imer ......................................................................................................... 42

Crystal Frequency Monitor .......................................................................................................... 42

V1 Pin ........................................................................................................................................ 42

I2C Inte rfa c e (E E P ROM) ............................................................................................................ 43

Internal Cl ock s and Cl ock Dividers .............................................................................................. 44

Battery ....................................................................................................................................... 44

Inter nal Voltag es (VBIAS, VBAT, V2P5) ...................................................................................... 44

Test Ports .................................................................................................................................. 44

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

FUNCTI ONAL DESCRIPTION ............................................................................................................................... 47

Theory of Operation ................................................................................................................................. 47

System Timing Summary.......................................................................................................................... 47

Data Flow ................................................................................................................................................ 50

CE/MPU Communicati o n .......................................................................................................................... 50

Fault , Reset, Power-Up ............................................................................................................................ 51

Battery Ope ration ..................................................................................................................................... 52

Power Save Modes .................................................................................................................................. 52

Temp erature Comp ens ation ..................................................................................................................... 53

Chopping Circuitry .................................................................................................................................... 53

Int ernal/External Pulse Generation and Pulse Counting ............................................................................. 55

Program Se curity ..................................................................................................................................... 56

FIRMWARE INTERFACE ...................................................................................................................................... 57

I/O RAM MAP – In Nu merical Orde r .......................................................................................................... 57

SFR MAP (SFRs Specific to TERIDIAN 80515) – In Nume rical Order ........................................................ 58

I/O R AM (Config ur a tion RAM) – Alphabetical Order................................................................................... 59

CE Pr ogr am an d Enviro nment .................................................................................................................. 65

CE Pr ogr am ............................................................................................................................... 65

Formats...................................................................................................................................... 65

Constants ................................................................................................................................... 65

Environment ............................................................................................................................... 66

CE Calculations .......................................................................................................................... 66

CE RAM Locations ................................................................................................................................... 67

CE Front End Data (Ra w Data) ................................................................................................... 67

CE Status Word.......................................................................................................................... 67

CE Tr ans fer Variabl es ................................................................................................................ 68

TYPICAL PERFORMANCE DATA.......................................................................................................................... 75

Wh Ac cur ac y at Room Temp era ture ......................................................................................................... 75

VARh Accur ac y at Room T emp eratu re ..................................................................................................... 75

Harmonic Per formance ............................................................................................................................. 76

Meter Accuracy over Tem perature (71M6511H) ........................................................................................ 76

APPLICATION INFORMATION .............................................................................................................................. 77

Connecti on of Sensors (CT, Resistive Shunt, Rogowski Coil) .................................................................... 77

Distinction bet ween 71M6511 and 71M6511H Parts .................................................................................. 77

Temperature Compensation and Mains Frequenc y Stabilization for the RTC.............................................. 78

External Temperature Compensation ........................................................................................................ 79

Temp erature Measur emen t ...................................................................................................................... 79

Connecti ng LCDs ..................................................................................................................................... 80

Connecti ng I2C EEPROMs ....................................................................................................................... 82

Connecti ng 5V Devices ............................................................................................................................ 82

Optical Interface ....................................................................................................................................... 83

Connecti ng V1 and Reset Pins ................................................................................................................. 83

Flash Programming .................................................................................................................................. 84

MPU Firmware Library.............................................................................................................................. 84

SPECIFICATIONS ................................................................................................................................................. 85

Electrical Specifications ............................................................................................................................ 85

LOGIC LEVELS.......................................................................................................................... 86

VREF, VBIAS ............................................................................................................................. 88

CRYSTAL OSCILLATOR ............................................................................................................ 88

LCD BOO ST .............................................................................................................................. 90

LCD DRI VERS ........................................................................................................................... 90

RTC ........................................................................................................................................... 90

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

RESETZ..................................................................................................................................... 90

COMPARATORS ....................................................................................................................... 90

RAM AND FLASH MEMORY ...................................................................................................... 91

FLASH MEMO RY TI MING .......................................................................................................... 91

EEPROM INTERFACE ............................................................................................................... 91

Recommended External C omp onents ....................................................................................................... 91

Packaging Informa t ion .............................................................................................................................. 92

Pinout (Top View) ....................................................................................................................... 93

Pin Descriptions ......................................................................................................................... 94

I/O E quivalent Circuit s: ............................................................................................................... 96

ORDERING INFO RMATION .................................................................................................................... 97

Figures

Figure 1: IC Functional Block Diagram .......................................................................................................................... 7

Figure 2: General Topology of a Chopped Amplifier ..................................................................................................... 10

Figure 3: AFE Block Diagram...................................................................................................................................... 11

Figure 4: Samples in Multiplexer Cycle ....................................................................................................................... 13

Figure 5: Accumulation Interval.................................................................................................................................. 13

Figure 6: Memory Map .............................................................................................................................................. 15

Figure 7: Interrupt Structure ...................................................................................................................................... 36

Figure 8: DIO Ports Block Diagram ............................................................................................................................. 37

Figure 9: Oscillator Circuit ......................................................................................................................................... 40

Figure 10: LCD Voltage Boost Circuitry ....................................................................................................................... 41

Figure 11: Voltage Range for V1 ................................................................................................................................ 43

Figure 12: Voltage. Current, Momentary and Accumulated Energy................................................................................ 47

Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers ................................................................ 48

Figure 14: RTM Output Format .................................................................................................................................. 49

Figure 15: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ............................................................................................ 49

Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY) ................................................................. 49

Figure 17: MPU/CE Data Flow .................................................................................................................................... 50

Figure 18: MPU/CE Communication (Functional) ......................................................................................................... 51

Figure 19: MPU/CE Communication (Processing Sequence) ........................................................................................ 51

Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up ................................................. 52

Figure 21: Chop Polarity w/ Automatic Chopping ........................................................................................................ 54

Figure 22: Sequence with Alternate Multiplexer Cycles ................................................................................................ 54

Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping ........................................................... 55

Figure 24: Wh Accuracy, 0.3A - 200A/240V ................................................................................................................ 75

Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance ................................................................................... 75

Figure 27: Meter Accuracy over Harmonics at 240V, 30A ............................................................................................ 76

Figure 29: Resistive Voltage Divider (left), Current Transformer (right) ......................................................................... 77

Figure 30: Resistive Shunt (left), Rogowski Coil (right) ............................................................................................... 77

Figure 31: Crystal Frequency over Temperature .......................................................................................................... 78

Figure 32: Crystal Compensation ............................................................................................................................... 79

Figure 33: Connecting LCDs ...................................................................................................................................... 80

Figure 34: LCD Boost Circuit...................................................................................................................................... 81

Figure 35: EEPROM Connection ................................................................................................................................. 82

Figure 36: Interfacing RX to a 0-5V Signal .................................................................................................................. 82

Figure 37: Connection for Optical Components ........................................................................................................... 83

Figure 38: Voltage Divider for V1 ............................................................................................................................... 83

Figure 39: External Components for RESETZ .............................................................................................................. 84

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Tables

Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles .............................................................................. 8

Table 2: Channel control based on MUX_DIV and FIR_LEN ........................................................................................ 9

Table 3: CE DRAM Locations for ADC Results ............................................................................................................. 12

Table 4: Standard Meter Equations (inputs shown gray are scanned but not used for calculation) .................................. 12

Table 5: Stretch Memory Cycle Width......................................................................................................................... 16

Table 6: Internal Data Memory Map ........................................................................................................................... 17

Table 7: Special Function Registers Locations............................................................................................................. 17

Table 8: Special Function Registers Reset Values ........................................................................................................ 18

Table 9: PSW Register Flags ...................................................................................................................................... 19

Table 10: PSW bit functions ...................................................................................................................................... 19

Table 11: Port Registers ............................................................................................................................................ 20

Table 12: Special Function Registers .......................................................................................................................... 21

Table 13: Baud Rate Generation ................................................................................................................................. 22

Table 14: UART Modes .............................................................................................................................................. 22

Table 15: The S0CON Register ................................................................................................................................... 22

Table 16: The S1CON register .................................................................................................................................... 23

Table 17: The S0CON Bit Functions ............................................................................................................................ 23

Table 18: The S1CON Bit Functions ............................................................................................................................ 24

Table 19: The TMOD Register .................................................................................................................................... 24

Table 20: TMOD Register Bit Description .................................................................................................................... 25

Table 21: Timers/Counters Mode Description ............................................................................................................. 25

Table 22: The TCON Register ..................................................................................................................................... 25

Table 23: The TCON Register Bit Functions ................................................................................................................. 26

Table 24: Timer Modes .............................................................................................................................................. 26

Table 25: The PCON Register ..................................................................................................................................... 26

Table 26: The IEN0 Register (see also Table 34) ......................................................................................................... 27

Table 27: The IEN0 Bit Functions (see also Table 34)................................................................................................... 27

Table 28: The IEN1 Register (see also Tables 35/36) ................................................................................................... 27

Table 29: The IEN1 Bit Functions (see also Tables 35/36) ............................................................................................ 27

Table 30: The IP0 Register (see also Table 46)............................................................................................................ 28

Table 31: The IP0 bit Functions (see also Table 46) ..................................................................................................... 28

Table 32: The WDTREL Register ................................................................................................................................ 28

Table 33: The WDTREL Bit Functions ......................................................................................................................... 28

Table 34: The IEN0 Register ...................................................................................................................................... 29

Table 35: The IEN0 Bit Functions ............................................................................................................................... 30

Table 36: The IEN1 Register ...................................................................................................................................... 31

Table 37: The IEN1 Bit Functions ............................................................................................................................... 31

Table 38: The IEN2 Register ...................................................................................................................................... 31

Table 39: The IEN2 Bit Functions ............................................................................................................................... 31

Table 40: The TCON Register ..................................................................................................................................... 32

Table 41: The TCON Bit Functions .............................................................................................................................. 32

Table 42: The IRCON Register.................................................................................................................................... 32

Table 43: The IRCON Bit Functions............................................................................................................................. 32

Table 44: External MPU Interrupts ............................................................................................................................. 33

Table 45: Control Bits for External Interrupts .............................................................................................................. 33

Table 46: Priority Level Groups .................................................................................................................................. 34

Table 47: The IP0 Register:........................................................................................................................................ 34

Table 48: The IP1 Register:........................................................................................................................................ 34

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Table 49: Priority Levels ............................................................................................................................................ 34

Table 50: Interrupt Polling Sequence .......................................................................................................................... 35

Table 51: Interrupt Vectors ........................................................................................................................................ 35

Table 52: Data/Direction Registers and Internal Resources for DIO Pin Groups ............................................................. 37

Table 53: DIO_DIR Control Bit .................................................................................................................................. 38

Table 54: Selectable Controls using the DIO_DIR Bits ................................................................................................ 38

Table 55: MPU Data Memory Map.............................................................................................................................. 38

Table 56: Liquid Crystal Display Segment Table (Typical) ............................................................................................ 41

Table 57: EECTRL Status Bits ................................................................................................................................... 44

Table 58: TMUX[3:0] Selections ............................................................................................................................... 45

Table 59: SSI Pin Assignment .................................................................................................................................... 46

Table 60: Power Saving Measures ............................................................................................................................. 52

Table 61: CHOP_EN Bits .......................................................................................................................................... 53

Table 62: Frequency over Temperature ....................................................................................................................... 78

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

MUX

XIN

XOUT

VREF

CKTEST

32-bit Compute

Engine

MPU

(8051)

CONTROL

OPT_RX

OPT_TX

RESETZ

VBIAS

EMULATOR

PORT

CE_BUSY

OPTICAL

UART

XFER BUSY

CE PROG

RAM

(4KB)

COM0..3

LCD DISPLAY

DRIVER

RTC

DATA

00-FF

PROG

000-7FF

DATA

0000-FFFF

PROG

0000-FFFF 0000-FFFF

MPU XRAM

(2KB)

0000-07FF

DIGITAL I/O

CONFIG

RAM

2000-20FF

I/O RAM

CE RAM

(1KB)

MEMORY SHARE

3000-3FFF

1000-13FF

RTCLK

RTCLK (32KHz)

MUX_SYNC

CKCE

CKMPU

CE_RUN

CE_LOAD

CE_EN

RTM_EN

COMP_INT

COMP_STAT

POWER FAULT

LCD_EN

LCD_CLK

LCD_MODE

DIO_GP

RTC_SET

<4.9MHz

4.9MHz

GNDD

V3P3A

V3P3D

VBAT

VOLT

REG

2.5V to logic

0.1V

V2P5

MPU_DIV

SUM_CYCLES

PRE_SAMPS

EQU

CKOUT_EN

VLCD

TMUXOUT

FAULTZ

WAKE

VBIAS

DMUX

TMUX

CONFIGURATION

PARAMETERS

VDRV

GNDA

VBIAS

TEMP

October 5, 2005

CK_GEN

OSC

(32KHz)

OSC_DIS

CK32

CK_EN

MCK

PLL

VOLTAGE

BOOST

LCD_BSTEN

LCD_IBST

VREF

VREF_D IS

MUX

CTRL

MUX_DIV

CHOP_EN

EQU

STRT

MUX

CKFIR

4.9MHz

MUX_SYNC

RTM

SEG34/DIO14 ...

SEG37/DIO17

GNDA

WPULSE

VARPULSE

WPULSE

VARPULSE

TEST

GNDD

<4.9MHz

LCD_NUM

DIO_OUT

DIO_IN

LCD_NUM

RTC_HOLD

DGND

IBIAS

WDTR_EN

reserved

OPTRX

ANALOG

DIGITAL

PULSE V/ W

MUX_ALT

SEG24/DIO4 ...

SEG31/DIO11

CKMPU_2X

SCL

SDA

FLASH

(64KB)

EEWRSLOW

EERDSLOW

V3P3A

FIR_LEN

FIR

FILTER

CK_10M

CK_MPU

reserved

SEG0..SEG2

EEPROM

INTERFACE

DIO_EEX

PLL_2.5V

CK_2X

ECK_DIS

OPT_TXDIS

∆Σ ADC

CONVERTER

VREF

RTCLK

CE_BUSY

XFER_BUSY

VBIAS

V3P3

V2P5

SEG3/SCLK

SEG4/SSDATA

SEG5/SFR

SEG6/SRDY

SEG7/

MUX_SYNC

SEG8..SEG19

SSI

Figure 1: IC Functional Block Diagram

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

HARDWARE DESCRIPT ION

Hardw are Overview

The TERIDIAN 71M6511 single chip si ngle-phase meter integrat es all primary functional blocks required to implem ent a solid-

state electricity meter. Included on chip are an analog front end (AFE), an 8051-compatible microprocessor (MPU) which

executes one instruction per clock cycle (80515), an independent 32-bit digit al computation engine (CE), a voltage reference,

a t emperature sensor, LCD drivers, RAM, flash memory, a real time clock (RTC), and a variety of I/O pins. Various current

sensor technologies ar e supported including Current Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils.

In addition to advanced m easurem ent functi ons, the real time clock function allows the 71M6511/6511H to record time of use

(TOU) m et ering information f or multi-rate applications. Measurements can be displayed on either a 3V or a 5V LCD. Flexible

mapping of LCD dis play segments will facilitate int egration with any LCD form at. The des ign tr ade-of f b et ween t h e n umber of

LCD segments and DIO pins can be flexibly configured using memory-mapped I/O to accommodate various requirements.

The 71M6511 includes several I/O peripheral functions that improve the functionality of the device and reduce the component

c ou n t f or m ost m et er a ppl i c at io n s. Th e I /O p eri p h er al s i n cl u de t wo U AR Ts , dig ital I /O , com pa r at or i np ut s, L C D di sp l ay dr i ver s ,

I2C i nterface and an opt ical/IR i nterface.

One of the two internal UARTs (UART1) is adapted to support an Infrared LED with internal drive output and sense input but it

can also functi on as a standard UART.

A block diagram of the chip is shown in Figure 1. A d eta i led descr iption of va r ious har dware blocks follows.

Analog Front End (AFE)

The AFE of the TERIDIAN 71M6511 Power Meter I C is comprised of an input multiplexer, a delt a-sigma A/D convert er with a

v oltage ref eren ce, fol lo wed by an F IR filter. A block diagram o f the AFE is shown in Figure 3.

Multiplexer

The input multiplexer supports four input signals that are applied to the pins IA, VA, and IB plus the output of the internal

tem per at ure s ens or . The multiplexer can be operated in two mode s:

• Du ring a normal mul t ipl ex er c ycle, t he s ign als fr om the pins IA, V A, an d IB, are s elect ed.

• During the alt ernate multipl exer cycle, the temperatur e signal (TEMP) i s selected, along with the other signal sources

shown in Table 1.

Alt er n at e m ul t i pl ex er c yc l es a r e u su al l y per f or m ed i nf r equ en t l y ( ev er y sec o n d or s o ). V A i s not r ep l ac ed i n t h e alt er n at e mu l ti-

plexer cy cles. Mis sing samples due to al ternat e m ult iplex er cycles are a utomat ical ly interpolated by the CE.

EQU

Channels used from MUX

Sequence

Sta tes 0 → 3

Channels used from alternati ve

MUX Sequence

Sta tes 0 → 3

0 1 2 3 0 1 2 3

000 IA VA IB - TEMP VA - -

001 IA VA IB - TEMP VA IB -

Table 1: Inputs Selected i n Regular and Alternate M ultiplexer Cycles

In a typical application , the IA input is connected to a current transforme r that senses the line current. VA is typica lly connected

to a voltage sensor through resistor dividers. IB may be connected to a second curren t t r ansform er, e. g. f or opti onal t am per

detection.

The Multiplexer Control Circuit handles the setting of the multiplexer. The function of the Multiplexer Control Circuit is

governed by the I/O RAM registers MUX_ALT (0x2005[2]), EQU (0x2000[7:5]), and MUX_DIV (0x2002[7:6]). MUX_DIV controls

the num ber of samples per cyc le. It can r equest 2, 3, 4, or 6 multiplex er s tates per cycle.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

The MUX_ALT bit requests an alternate multiplexer cycle. The bit may be asserted on any MPU cycle and may be sub-

sequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the Control Circuit to wait

until the next multiplex er c ycle and implement a singl e alternate c ycle.

Multiplexer Control Circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The

M u ltiplex er Co n t ro l Circuit is clocked by C K32, the 32768Hz clock fro m the P LL block, and laun che s each pass through the C E

program.

Table 2 shows the possible settings for MUX_DIV and FIR_LEN and the resulting channels sampled along with sample

frequencies.

MUX_DIV

(0x2002[7.6]) Number of

channels

selected

( mu x sta tes

per cycle)

Number of

CK32 states

for code pass

Effective

sample

frequency

[Hz]

Number of

CK32 states

f o r c ode

pass

Effective

sample

frequency

[Hz]

FIR_LEN = 0 FIR_LEN =1

00 --- No t All o wed

01 4 9 3640.89 13 2520.615

10 3 7 4681.143 10 3276.8

11 2 5 6553.6 7 4681.143

Table 2: Channel control based on MUX_DIV and FIR_LEN

ADC

A single 21/22-bit delta-sigma A/D converter (ADC) digitizes the power inputs to the AFE. The resolution of the ADC is

programmable using the I/O RAM register FIR_LEN register (0x2005[4]). ADC resolution may be selected to be 21 bits

(FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversi on time is two cycles of CK32 with FIR_LEN = 0 and t hree c yc les with FIR_LEN

= 1.

In order to provide the maximum resolution, the ADC should be operated with FIR_LEN = 1. Accuracy, timing and

functional specificati ons in this data sheet ar e based on FIR_LEN = 1 and MUX_DIV = 1 (four CK32 cycles). Alternative

specifications are also provided for FIR_LEN = 1 and MUX_DIV = 2 (three CK32 cycles) in the CE Program and

Environment section.

Initiation of each ADC conversi on is controlled by the Multiplex er Cont rol Circ uit as desc r ib ed previ ously.

FIR Fi lt e r

The finite impulse response (FIR) filter is an integral part of the ADC and it is optimized for use with the multiplexer. The

purpose of the FIR is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output

da ta of th e FI R fi lter ( raw dat a) i s stor ed i nt o th e CE DRAM l oc ation det erm in ed b y t he m ulti plex er s el ect io n. The lo cat ion o f

the raw data in the CE DRAM is specified in the CE Program and Environment Sec ti on.

Voltage Reference

The 71M6511/6511H includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The

reference of t he 71M6511H is trimmed in production to minimize errors caused by component mismatch and drift. Th e result is

a voltage output with a predictable temperature coefficient.

The voltage reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register

CHOP_ENA (0x2002[5:4]). The two bits in the CHOP_ENA register enable the MPU to operat e the chopper circ uit in regular or

inverted operation, or in “toggling” mode. W hen the chopper ci rcuit is toggled in between m ultipl exer c ycles, DC offsets on the

measured signals w i ll aut omaticall y be averaged out.

The general t opology of a chopped amplifier is given in Figure 2.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

inp

outp

outn

inn

CROSS

Figure 2: General Topology of a Chopped Amplifi er

It is assumed that an offset voltage Voff appear s at the positive amplifier input. With all switches, as controlled by CRO SS in

the “A” position, the output voltage is:

Voutp – Vout n = G ( Vi np + Voff – Vinn) = G (Vinp – Vi n n) + G Voff

W ith all swit ches set to the “B” position by applying the inverted CROSS signal, the output voltage is:

Voutn – Vout p = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or

Voutp – Vout n = G ( Vi np – Vinn) - G Vo f f

Thus, w hen CROSS is t oggled, e.g. af ter each multipl exer cycle, t he of fset w ill alt ern ately appear on t he output as positiv e and

negative, which results in the off set ef fec t ively bein g eli mi nat ed, r egardles s of its polarit y or magni tu de.

The Functional Description Secti on contains a chapter with a detailed description on controlling the CHOP_ENA register.

Temperat ure Sensor

The 71M6511/6511H includes an on-chip temperature sensor implemented as a bandgap reference. It is used to determine

the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by

asserting MUX_ALT.

The prim ary use of the tem perature data is to determine the magnitude of com pensation required to offset the therm al drift in

the system (see sect ion titled “ Temper at ure Comp ens atio n”).

The z ero refer ence fo r the temp erat ure s ensor is VBIA S.

Funct io nal Description

The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB) are sampled and the

ADC counts obtained are stored in CE RAM where they can be accessed by the CE and, if necessary, by the MPU. Alternate

m ult iplex er cycles are init iated less frequ ent l y by the MPU to gather access to the slow temperature signal.

MUX

VREF VBIAS

VBIAS

TEMP

CK32

VREF

VREF_ D IS

MUX

CTRL

MUX_DIV

CHOP_EN

EQU

MUX

MUX_ALT

V3P3A

FIR_LEN

FIR

FILTER

∆Σ ADC

CONVERTER

VREF

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Figure 3: AFE Block Diagram

Co m putation Engine (CE)

The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure energy.

The CE calculations a nd pr ocess es inc lu de:

• Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when

multiplied with the constant sample time ).

• Frequency-insensitive delay cancellation on all six channels (t o compensate for the delay between sam ples caused

by the multiplexing scheme).

• 90° ph ase s hifter (for VA R c alculat io ns).

• Pulse generation.

• Monitoring of the input signal frequency (for frequency and phase information).

• Monitoring of the input signal amplitude (for sag det ect ion).

• Scaling of the processed samples based on chip temperature (temperature compensation) and calibration

coefficients.

The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then ex ecuted by the CE. Each CE instruction wor d

is 2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code

pass ends when a HALT instruction is executed. For proper operat i on, the code pass must be completed before the

m ult iplex er cycle ends (s ee System Tim in g Summar y in the Functional Descr iption Sect ion).

The CE data RAM (CE DRAM) can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time

s lots are reserv ed f or FIR, R TM, and M PU, r esp ect ively, suc h that mem ory accesses to CE_RAM do not collide. Holding re-

gisters are used to convert 8-bit wid e M PU d ata to/from 32-bit wide CE DRAM data, and wait states are inserted as needed,

depending on the frequency of CKMPU.

Table 3 shows the CE DRAM addresses allocated to analog inputs from the AFE.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Address (hex)

Name

Description

0x00 IA P hase A cur ren t

0x01 VA Phase A voltage

0x02 IB P hase B cur ren t

0x03 - Reserved

0x04 - Reserved

0x05 - Reserved

0x06 TEMP Temperature

0x07 -- Reserved

Table 3: CE DRAM Loc ations for ADC Res ults

Meter Equ at io ns

The Compute Engine (CE) program for residential meter configurations implements the equations in Table 4. The I/O RAM

register EQU specifies the equation to be used based on the num ber and arrangem ent of phases used for metering. In case of

single-phase meteri ng, the unconnected input should be tied to V3P3A, the analog supply voltage. The EQU selecti on enables

the 71M6511 to calculate single-phase power measurement based on the type of service used. Table 4 also states the

sequence of the mult iplex e r in the AFE .

EQU Formula

Channels used from MUX

Sequence

Sta tes 0 → 3

Channels used from alternati ve

MUX Sequence

States 0 → 3

0 1 2 3 0 1 2 3

000 VA IA

(1 element, 2W 1

) IA VA IB - TEMP VA - -

001 VA(IA-IB)/2

(1 element, 3W 1

) IA VA IB - TEMP VA IB -

Table 4: Standard Meter Equations (inputs shown gray are scanned but not used for calculation)

Pulse Generator

The CE contains two pulse generators w hich cre ate low jitter pulses at a rate se t by the CE DRAM re gisters APULSEW*WRATE

and APULSER*WRATE if EXT_PULSE (a CE input variable in CE DRAM) is 15. This mode puts the MPU in control of pulse

generation by pla cin g values in to the APULSEW and APULSER regi sters (“ext ern al pulse gener at ion” ) .

If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X. In this mode, the CE

generates pulse based on its internal computation of WSUM_X and VARSUM_X, the signed sums of energy from all three

elemen ts ( “i nternal pul se gener atio n”).

The DIO_PV and DIO_PW bit s as described in the Digital I/O section can be programm ed to route W PULSE and VARPULSE

to the output pins DIO6 and DIO7 respectively. DIO6 and DIO7 can be configured to generate interrupts (useful for pulse

counting by the MPU – see On-Chi p Resourc es (DIO Sect ion) .

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Real-Time Monitor

The CE contains a Real Time Monitor (RTM), which can be programm ed to monitor four selecta ble CE RAM l oc ati on s at f ul l

sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the

beginning of each CE code pass (see t he Test Ports Sect ion for det ai ls)

CE Functional Overview

The ADC processes o ne sam ple per c hannel per m ultiplex er cycle. Figure 4 shows the timing of the samples taken during one

m ult iplex er cycle.

The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS

(0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration tim e for each energy output is

PRE_SAMPS * SUM_CYCLES / 2520.6, wher e 2520.6 i s th e sampl e rate [ Hz] ( for MUX_DIV = 1)

For ex ample, PRE_SAMPS = 42 and SUM_CYCLES = 50 will est a bl is h 2100 samples per accumulation cycle. PRE_SAMPS = 100

and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation

c ycle i s com pleted , the XF ER_ BUS Y interru pt sig nals to t he MPU that accumula ted dat a are a vail able.

1/32768Hz =

30.518µs

13/32768Hz = 39 7µ s

per mux cycle

1/32768Hz =

30.518µs

13/32768Hz = 39 7µ s

per mux cycle

Figure 4: S amples in Mu lt i pl exer C ycl e

The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle,

status information, such as sag data and the digitized input signal, is available to the MPU.

XFER_BUSY

Interrupt to MPU

20ms

833ms

XFER_BUSY

Interrupt to MPU

20ms

833ms

Figure 5: Accumulation Interval

Figure 5 shows the accumulation inte rv al resulting from MUX_DIV = 1, PRE_SAMPS = 42 and SUM_CYCLES = 50, con sisting of

2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this exampl e is applied to a 50Hz signal.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES (even though when

SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a peri od of 16.6ms). Furthermore, sampling does not have to

start when the line voltage crosses the zero line.

Delay Co mpensat ion

When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that phase must be

sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.

delay

t360360 ⋅⋅=⋅=

Where f is the f r equency of the input signal and tdelay is th e sam pling delay bet ween volt age and cur ren t .

In t raditional met er ICs, sampling is accomplished by using two A/D converters per phase (one for voltage and the other one

f or c urr ent ) c ont rol led to s ample s im ultan eousl y. Teridian’s Single-Converter Technology®, h owev er, exploits t he 32-bit signal

processing capability of its CE to implement “constant delay” all-pass filters. These all-pass filters correct for the conversion

time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed A/D

converter.

The “constant delay” all-pass filters provide a broad-band delay β that is precisely matched to the difference in sample time

between the voltage and the current of a given phase. This digital filter does not affect the amplitude of the signal, but

provides a prec isel y co ntrolled phase r esp onse. T he delay com p ensati on im pl em ented in t he CE ali gns th e vol t age sam ples

with their corresponding current samples by routing the voltage sam pl es through the all-pass filter, t hus delaying the voltage

samples by β, resulting in the residual phase error β – Ф. The residual phase err or is negligible, and is typically less than ±1.5

milli-de gre es at 100Hz, thus it does not contribu te to errors in the ene rgy measure ments.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

80515 MPU Co re

80515 Overvi ew

The 71M6511/6511H includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle.

Using a 5MHz clock results in a proce ssing throughput of 5 MIPS. The 80515 arch itecture eliminate s re dundant bus sta te s and

implement s parallel exec ut ion of fetch and execution phases. Normally a machine cycle is ali gned with a memory fetch, there-

fore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average)

imp ro vem ent (in terms o f MIPS) o ver t he I ntel 8 051 device running at the sam e clock frequency.

Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations,

AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register

MPU_DIV[2:0].

Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are

available for the MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-appli cation programm ing interfa ce

li brary i s ava i labl e to h elp red uce des ig n cy cle.

Memory Organization

The 80515 MPU core incorporates the Harvard architecture wit h separate code and data spaces.

Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program

memory (flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, CE PRAM and I/O RAM, and

internal data memory (Internal RAM ). Figure 6 shows the me mory map (se e also Table 55).

I nter n al a nd Ext e r n al Dat a Memor y: Both internal and external data mem ory are physicall y located on the 71M6511 IC. Ex-

ternal data memory is only external to the 80515 MPU core.

0xFFFF

Flash memory

0xFFFF

---

0x4000

0x3FFF

CE PRAM

0x3000

0x2FFF

---

0x2100

0x20FF

I/O R AM

0x2000

0x1FFF

---

0x1400

0x13FF

CE DRAM

0x1000

0x0FFF

---

0x0800

0x07FF

XRAM

0xFF

SFRs, RAM,

reg. banks

0x0000

0x00

Pro gra m me mory

External data me mory

Interna l data memory

Figure 6: Memory Map

Prog ram Me mo ry: The 80515 can address up to 64KB of program m emory space from 0x0000 to 0xFFFF. Program m emory

is read when the MPU fetches instructi ons or performs a MOVC operation.

After r eset, t he MP U star t s pr ogr am execut ion from l ocati on 0x 0000. T he l ower pa r t of the pro gr am memor y includes r eset and

interru pt vectors. The int errupt vect ors are s paced at 8-byte intervals, starting from 0x0003.

External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to

0xFFFF, only the m em ory ranges shown in Figure 6 contain physical memory. The 80515 writes into external data memory

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external dat a m emor y by executing

a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction).

Clock Stretching: MOVX instructions can access fast or slow external RAM and ext ernal peri pherals. The thr ee low ordered

bits of t he CKCON register define the stretch m emory cycles. Sett ing all the CKCON stretch bits to one allows access to very

s low ex ternal RA M or exter nal peripheral s.

Table 5 shows how the signals of the E x ternal Memory Interface change when stretch values are set from 0 t o 7. The w idths of

the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table,

performs the MOVX instructions with a stretch value equal to 1.

CKCON regis ter Stretch Val ue Read signals width Write signal width

CKCON.2 CKCON.

1 CKCON.

0 memaddr memrd memaddr memwr

0 0 0 0 1 1 2 1

0 0 1 1 2 2 3 1

0 1 0 2 3 3 4 2

0 1 1 3 4 4 5 3

1 0 0 4 5 5 6 4

1 0 1 5 6 6 7 5

1 1 0 6 7 7 8 6

1 1 1 7 8 8 9 7

Table 5: S t re t ch M emo ry Cycl e W id t h

There are two types of i nstructions, differing in whether t hey provide an eight-b it or s i xteen -bit indirect address to the external

data RAM.

In t he first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight l ower-ordered bits of

address. The eight high-or der ed b i ts of a d dr ess ar e s p ecif i ed wi t h t he USR2 SFR. This m ethod allows the user paged access

(256 pages of 256 bytes each) to the full 64KB of external data RAM. In the second type of MOVX instruction (MOVX

A,@DPTR), the data pointer generates a sixteen-bit address. This f orm is f aster and m ore efficient when accessing very lar ge

data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address.

I t is possibl e to m ix t he t wo MO VX t ypes . T his pr ovid es t he us er wit h four sep ar ate d ata poi nt ers , two wi th d irect acc ess and

two with paged access to the entire 64KB of external m emory range.

Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit regi ster that is

used to address external m em ory or peripherals. In the 80515 core, the standard data pointer is call ed DPTR, the second data

pointer is called DPTR 1. The data pointer sele ct bit chooses the active pointer. The data pointer se le ct bit is loc ate d at the LSB

of the DPS register (DPS.0). DPTR is selected w hen D PS.0 = 0 and DPT R1 is select ed when D PS.0 = 1.

The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently

s elect ed DP TR for any activity.

The second data point er may not be supported by certain compilers.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data

memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. The Special Function

Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing

accesses the upper 128 bytes of Internal RAM.

The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight

registers (R0-R7). Two bits on the program m emory status word (PSW ) select which bank is in use. The next 16 bytes form a

bl ock of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible

through direct or indirect addressing. Table 6 shows the internal data memory map.

Address

Direct addr essin g

Indirect addressing

0xFF Special Function Registers

(SFRs) RAM

0x80

0x7F Byte-addressable area

0x30

0x2F Bit-addr essab le area

0x20

0x1F Register banks R0…R7

0x00

Table 6: Internal Data Memory Map

Special Function Regist ers ( SFRs)

A map of the Special Function Registers is shown in Table 7.

Hex\Bi

n Bit-

address-

able

Byte-addressable Bin/He

X000 X001 X010 X011 X100 X101 X110 X111

INTBITS

WDI

WDCON

PSW

IRCON

IEN1

IP1

S0RELH

S1RELH

USR2

FLSHCTL

PGADR

IEN0

IP0

S0RELL

DIR2

DIR0

S0CON

S0BUF

IEN2

S1CON

S1BUF

S1RELL

EEDATA

EECTRL

DIR1

DPS

ERASE

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON

DPL

DPH

DPL1

DPH1

WDTREL

PCON

Table 7: Special Function Registers Locations

Only a few addresses are occupied, t he others are not impl em ented. SFRs specific t o the 651X are shown in bold print. Any

read access to unimplemented addresses will return undefi ned data, while any write access will have no effect. The regist ers

at 0x80, 0x88, 0x90, etc., are bit-ad dressabl e, all oth ers ar e byt e-addressable.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Special Function Regist ers ( Generic 80515 SFRs)

Table 8 shows the locatio n of t he SF Rs and t he value t hey as sume at reset o r power -up.

Name Location R eset value Description

P0 0x80 0xFF Port 0

SP 0x81 0x07 S tac k Pointer

DPL 0x82 0x00 Dat a P ointer Low 0

DPH 0x83 0x00 Data Pointer High 0

DPL1

0x84

0x00

Dat a Poi nter Low 1

DPH1 0x85 0x00 Da ta P ointer High 1

WDTREL

0x86 0x00 Wat chdog Ti mer Relo ad r egist er

PCON 0x87 0x00 UART Speed Control

TCON 0x88 0x00 Timer /Counter Control

TMOD 0x89 0x00 Timer Mode Control

TL0 0x8A 0x00 Timer 0, low byte

TL1 0x8B 0x00 Timer 1, high byte

TH0 0x8C 0x00 Tim er 0, low byte

TH1 0x8D 0x00 Timer 1, high byte

CKCON

0x8E 0x01 Clock Control (Stretch=1)

0x90

0xFF

Port 1

DPS 0x92 0x00 Dat a Poi nter select Regi ster

S0CON 0x98 0x00 Ser ial Por t 0, Control Register

S0BUF 0x99 0x00 Ser ial P or t 0, Data Buffer

IEN2 0x9A 0x00 Int errupt En able Reg ist er 2

S1CON 0x9B 0x00 S erial Por t 1, Con tr ol Regist er

S1BUF 0x9C 0x00 S erial Port 1, Data Buffer

S1RELL 0x9D 0x00 Serial P or t 1, Relo ad Regi ster, l ow b y te

P2 0xA0 0x00 Port 2

IEN0

0xA8 0x00 Int errupt Enable Reg ist er 0

IP0

0xA9 0x00 Int errupt Prio r i ty Reg ister 0

S0RELL 0xAA 0xD9 S erial Por t 0, Relo ad Reg ister, l ow b yte

P3 0xB0 0xFF Port 3

IEN1 0xB8 0x00 Interrupt Enable R egister 1

IP1 0xB9 0x00 Inter ru pt Prior it y Reg ister 1

S0RELH 0xBA 0x03 S erial Port 0, Relo ad Regi ster, hig h b yte

S1RELH 0xBB 0x03 S erial Port 1, Relo ad Regi ster, hig h b yte

USR2 0xBF 0x00 U ser 2 Po r t , hig h address byt e for M OV X@Ri

IRCON 0xC0 0x00 Inter rupt Request Co ntrol Reg ister

PSW 0xD0 0x00 Program Status Word

WDCON

0xD8 0x00 B aud Rate Control Reg ist er (o nly

WDCON

.7 bit used)

A 0xE0 0x00 Accumulator

B 0xF0 0x00 B R egist er

Table 8: Special Function Registers Reset Values

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The

mnem onics for accum ulator-speci fi c instructi ons refer to accumula tor as “ A”, not ACC.

B Register: The B regis t er is used duri ng multiply and divide instructions. It can also be used as a scratch-pad regis ter to hold

temporary data.

Program Status Word (PSW):

MSB LSB

CV AC F0 RS1 RS OV - P

Table 9: PSW Register Fla gs

Bit Symbol Function

PSW.7 CV Carry flag

PSW.6 AC Auxil iary Carry flag for BCD operations

PSW.5 F0 G ener al purp ose Fla g 0 av ai labl e fo r us er . Not to be confus ed with the F0 flag

in the CESTATUS register.

PSW.4 RS1 Regist er b ank select co nt ro l bit s. T he c ont ent s of RS1 and RS 0 select t he

working registe r bank:

RS1/RS0

Bank selected

Location

00 Bank 0 (0x00 – 0x07)

01 Bank 1 (0x08 – 0x0F)

10 Bank 2 (0x10 – 0x17)

11 Bank 3 (0x18 – 0x1F)

PSW.3 RS0

PSW.2 OV Ov er flow fla g

PSW.1 - User defined flag

PSW.0 P Parity flag, affected by hardware to indicate odd / even number of “one” bits in the

Acc umu lator , i.e. even pa r i ty.

Table 10: PSW bit functions

Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before

PUSH and CALL instructions, causing the stack to begin at location 0x08.

Data Pointer: The data point er (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-

byte register (MOV DPTR,#data16) or as two registers ( e.g. MOV DPL,#data8). It i s generally used to access ext ernal c ode or

data space (e. g. MOV C A , @A +DP TR or MOVX A,@ DPT R r esp ect ively) .

Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented

during the fetching operation code or when operating on data from program memory.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be

observed on corresponding pins on t he chip. Writing a ‘1’ to any of the ports (see Table 11) causes the corresponding pin to

be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction

registers DIR0, DIR1, and DIR2 define indi vidual pins as input or output pins (see section On-Chip Resources – DIO Ports for

details).

Addres

R/W Description

P0 0x80 R/W Register for port 0 read and write operations (pins DIO4…DIO7)

DIR0 0xA2 R/W Data direction register for port 0. Setting a bit to 1 m ean s th at the corresponding pin is

an output.

P1 0x90 R/W Register for port 1 read and write operations (pins DIO8…DIO15)

DIR1 0x91 R/W Data direction register for port 1.

0xA0 R/W Register for port 2 read and write operations (pins DIO16-DIO17)

DIR2 0xA1 R/W Data direction register for port 2.

Table 11: Port Registers

All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P3’) , an output driver, and an input

buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the

state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under CE control.

Special Function Regist ers S pecif ic to the 71M 6511

Table 12 shows the location and description of the 71M6511-specific SFRs.

Name SFR

Addres

R/W Description

ERASE

FLSH_ERASE

0x94

This register is used to initiate either the Flash Mass Erase cycle or

the F lash Page E rase cyc le. Specific patt ern s ar e expected for

FLSH_ERASE in or der t o ini ti at e t he approp r iat e Era se cy cle (defaul t =

0x00).

0x55 – Initiate Flash Page Era se c ycle. M ust b e pr oceeded by a w ri te

to FLSH_PGADR @ SFR 0xB7.

0xAA – Initiat e Flash M ass E rase cycle. M ust be proceeded by a

write to FLSH_MEEN @ SFR 0xB2 and the debug port must

be enabled.

Any other pattern writt en to FLSH_ERASE will have no eff ect.

PGADDR FLSH_PGADR 0xB7 R/W Fl ash Page Erase Address register containin g t he fla sh mem or y

page address (page 0 thru 127) that will be erased during the Page

Erase cycle (default = 0x00).

Must be re-wr i tt en f or ea ch new Pa ge Era se cy cle.

EEDATA 0x9E R/W I2C EEPROM i nterf ace data regist er

EECTRL 0x9F R/W I2C EEPROM int erface c ontrol r egister. If the MPU w i sh es t o write a

byte of dat a to E EPROM, i t plac es the dat a i n EEDATA and then

writes the ‘Transmit’ code to EECTRL. The w r ite to EECTRL initiates

the transmit sequence. See the section I2C Interface (EEPROM) for

a description of the command and status bits available for EECTRL.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

FLSHCRL 0xB2 R/W

R/W

Bit 0 (FLSH_PWE): Pro gram Write E nable:

0 – MOVX commands r efer to XR A M Space, normal oper ation

(default).

1 – MOVX @DPTR ,A move s A to Program Space (flash) @

DPTR.

This bi t is aut omaticall y r eset after eac h byte w r itten to flash. Wri tes

to this bit are inhibit ed when interrupts are enabled.

Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mas s Er as e dis abled (default).

1 – Mass Erase enabled.

Must be re-wr i tt en f or ea ch new Ma ss Era se cy cle.

Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash

m emory and CE program RAM. This bit is reset on chip reset and

m ay o nly be set. Attempts to write zero ar e i gnored .

Bit 7 (PREBOOT):

Indic ates t hat the preb oot sequence is act ive.

WDI 0xE8

R/W

Only byte operations on the whole WDI register should be used

when writi ng. The byte m us t have all bits set except the bits that are

to be cleared.

The multi-pu rpose reg ister WDI contain s the fol lowing bit s:

Bit 0 ( IE_XFER) : XFE R Inter ru pt Flag:

This flag monitor s th e XFE R_B USY interrupt. It is set by hardw ar e

and must be cleared by the inter ru pt ha ndler

Bit 1 ( IE_RTC): RTC Interr upt Fl ag:

This flag monitors the RTC_1SEC interrupt. It is set by hardware and

must be cleared by the inter ru pt ha ndler

Bit 7 (WD_RST): WD Timer Reset:

The WD T is r eset wh en a 1 is writ ten t o this bi t.

INTBITS INT0…INT6 0xF8 R Int errupt inputs. The MPU m ay read th ese bit s to see t he i nput to

external interrupts INT0, INT1, up to INT6. These bits do not have

any memory and are primarily intended for debug use

Table 12: Special Function Registers

Instruction Set

All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated

op-codes is contained in the 651X Software User’s Guide (SUG).

UART

The 71M6511 includes a UART (UART0) that can be programm ed to communicate with a variety of AMR mo d ul es . A s ec o nd

UART (UART1) is connected to the optical port, as described in the optical port description.

The UA RT is a dedicat ed 2-wire seri al interf ace, which can communicate wit h an external host processor at up to 38,400 bits/s

((with MPU clock = 1.2288MHz). The operati on of each pin is as follows:

RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. The voltage applied

at RX must not exc eed 3.6V.

TX: T his pin is u sed t o output the serial data. The bytes are output LSB first.

The 71M6511 has, severa l UART -rel at ed regi st ers f or the control and buffer ing of s erial dat a.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

A single SFR register serves as both the transmit buff er and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR

0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and when read by the MPU, it acts as the

receive buffer. Writing data to the transmit buffer starts the transmission by the associated UART. Received data are

available by reading from the receive buffer. Both UARTs can simultaneously transmit and receive data.

WDCON[7] selects whether timer 1 or the internal baud rate gen erator is used. Al l UART tr a n sfer s are p rog ramm able f or pa rity

enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps.

Table 13 shows how the baud rates are calculated. Table 14 shows the selectable UART operation modes.

Using Timer 1

Using Internal Baud Rate Generator

Serial Interface 0

2smod * fCKMPU/ (384 * (256-TH1)) 2smod * fCKMPU/(6 4 * ( 210-S0REL))

Serial Interface 1

N/A fCKMPU/(32 * (2

-S1REL))

Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective tim er reload registers. SMOD is the

SMOD b i t i n t he SFR PCON. TH1 is t he high byt e of timer 1.

Table 13: Baud Rate Generation

UART 0 UART 1

Mode 0 N/A S ta rt bit, 8 dat a bits, par ity, sto p bit, var iabl e

baud rate (interna l baud rate generator)

Mode 1 Start bit, 8 data bits, stop bit,

variable baud rate (internal baud

rate generator or timer 1)

Start bit, 8 data bits, stop bit, variable baud rate

( internal baud rat e genera to r)

Mode 2

Start bit, 8 data bits, parity, stop bit,

fi xed bau d rate 1/32 or 1/64 of

fCKMPU

N/A

Mode 3

Start bit, 8 data bits, parity, stop bit,

variable baud rate (internal baud

rate generator or timer 1)

N/A

Table 14: UART Modes

Parity of serial data is availabl e through the P flag of t he accum ulator. Seven-bit serial modes with parity, such as those used

by the FLAG protocol, can be simulated by setti ng and reading bit 7 of 8-bi t o ut p ut d at a. Sev en -b i t ser ial modes wit hout parity

can be simulat ed by sett ing bit 7 t o a constant 1. 8-bit serial modes wit h parity can be simulated by setti ng and reading the 9th

bit, using the control bits TB80 (S0CON.3) and TB81 (S1CON.3) in the S0COn and S1CON SFRs for transmit and RB81

(S1CON.2) for receive operations. SM20 (S0CON.5) and SM21 (S1CON.5) can be used as handshake signals for i nt er-pro-

c essor c ommunication in mult i-proce ssor sys tems.

Serial Interface 0 Control Register (S0CON).

The function of the UART0 depends on the setting of the Serial Port Control Register S0CON.

MSB LSB

SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0

Table 15: The S0CON Register

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Serial Interface 1 Control Register (S1CON).

The function of the serial port depends on the setting of the Serial Port Control Register S1CON.

MSB LSB

SM21

REN1

TB81

RB81

TI1

RI1

Table 16: The S1CON register

Bit Symbol Function

S0CON.7 SM0 These tw o bi ts set t he UA RT0 mode:

Mode

Description

SM0

SM1

0 N/A 0 0

1 8-bit UART 0 1

2 9-bit UART 1 0

3 9-bit UART 1 1

S0CON.6 SM1

S0CON.5 SM20 Enables the inter-pr ocess or c om mu nicatio n fea ture.

S0CON.4 REN0 If set , enables serial recept ion. Clea red by softwar e t o disable rec ept ion.

S0CON.3 TB80 The 9th t ra ns mitted dat a bit in Modes 2 and 3. Set or cleared by the

MPU, depending on the function it performs (parity check, multiprocessor

c ommunication et c . )

S0CON.2 RB80 In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,

RB80 is th e stop bit. In Mode 0 this b it is not used. Must be cleared by

software

S0CON.1 TI0 Tra nsm it int errupt flag, set by har dware aft er c ompleti on of a seria l

tr ansfer. Must be cleared by s oftware.

S0CON.0 RI0 Receive i nterr upt fla g, s et by h ar dware aft er completion of a seria l

recepti on. Must b e c lea red by s oftware

Table 17: The S0CON Bit Functions

Note: The speed in Mode 2 depends on the SMOD bit i n the SFR PCON. S ee the PCON regist er d escr ipt ion.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Bit Symbol Function

S1CON.7 SM Sets t he baud rate for UART1

SM Mode Description Baud Rate

0 A 9-bit UART variable

1 B 8-bit UART variable

S1CON.5 SM21 Enables the inter-pr ocess or c om mu nicatio n fea ture.

S1CON.4 REN1 If set , enables serial recept ion. Clea red by softwar e t o disable rec ept ion.

S1CON.3 TB81 The 9th tr ansmitted dat a bit in M ode A . Set or clear ed by t he MPU,

depending on the function it performs (parit y check, multiprocessor

c ommunication et c . )

S1CON.2 RB81 In Modes 2 and 3, it is the 9th data bit rec eived. In Mod e B, if SM21 is 0,

RB81 is the stop bit. Must be cleared by software

S1CON.1 TI1 Tra nsm it int errupt flag, set by har dware aft er c ompleti on of a seria l

tr ansfer. Must be cleared by s oftware.

S1CON.0 RI1 Receive i nterr upt fla g, s et by h ar dware aft er completion of a seria l

recepti on. Must be cleared by software

Table 18: The S1CON Bit Functions

Ti mers and Count ers

The 80515 has two 16-bit tim er/counter registers: Tim er 0 and Tim er 1. These registers can be configured for counter or t imer

operations.

In timer mode, the register is incremented every machine cycle m eaning that it counts up after every 12 periods of the MPU

clock signal.

In counter m ode, t he regist er is increm ented when th e fal ling edge is observed at the corresponding input si gnal T0 or T1 (T0

and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Si nce it takes 2 machine cycl es

to recognize a 1-to-0 event, the maxim um input count rate is 1/2 of the oscillator frequency. There are no restrictions on the

duty cycle, however to ens ur e pr oper rec og nition of 0 or 1 stat e, a n input should be sta ble for a t lea s t 1 machine cycle.

Four operati ng modes can be selected for Tim er 0 and Tim er 1. Two Special Function Registers (TMOD and TCON) ar e us ed

to select the appropriate mode.

Timer/Counter Mode Control Reg ister ( TMOD):

MSB LSB

GATE C/T M1 M0 GATE C/T M1 M0

Timer 1 Timer 0

Table 19: The TMOD Register

Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 22 and Table 23) start their associated timers when set.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Bit

Symbol

Function

TMOD.7

TMOD.3 Gate If set , enables external gate c ontrol (pin int0 or i nt1 for Counter 0 or 1,

respe ctively). When int0 or int1 is high, and TRX bit is s et ( see TCON reg ister) , a

counter is incremented every falling edge on t0 or t1 input pin

TMOD.6

TMOD.2 C/T Selects Timer or Counter operation. When set to 1, a Counter operation is

perfo r med. When cleared to 0, t he correspo ndi ng r egist er will fu nctio n as a T imer.

TMOD.5

TMOD.1 M1 Selects t he mode for Timer/ Counter 0 or Timer/Counter 1, as shown in TMOD

description.

TMOD.4

TMOD.0 M0 Selects t he mode for Timer/ Counter 0 or Timer/Counter 1, as shown in TMOD

description.

Table 20: TMOD Register Bit Description

M1 M0 Mode Function

0 0 Mode 0 13-bit Count er/Timer with 5 low er bits in the TL0 or TL1 register and the

remaining 8 bits in the TH0 or TH1 register (fo r Timer 0 and Ti mer 1,

r esp ect ively) . The 3 h igh ord er bi ts of TL0 and TL1 are held at zero.

0 1 Mode 1 16-bit Count er/Timer .

1 0 Mode2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,

while TL0 or TL1 is incremente d every mac hine cyc le . When TL

(x) overflows,

a value f rom TH(x) is copied to TL(x).

1 1 Mode3 If Timer 1 M1 and M0 bi ts ar e set to '1', Ti mer 1 st ops. I f Timer 0 M1 and M0

bits are set to '1', Tim er 0 acts as two independent 8-bit Ti mer/Counters .

Table 21: Timers/Counters Mode Description

Note: TL0 i s affected by TR0 and gate contr ol bits, and sets TF0 flag on overflow.

TH0 is affected by TR1 bit, and sets TF1 flag on overflow.

Tim er/Counter Control Register (TCON)

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Table 22: The TCON Register

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Bit Symbol Function

TCON.7 TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag

can be cleared by software and is automatically cleared when an interrupt is

processed.

TCON.6 TR1 Timer 1 Run control bit. If cleared, Timer 1 stops.

TCON.5 TF0

Timer 0 overflow flag set by hardware when Tim er 0 overflows. This flag can be

c lea red by s oftware a nd i s aut omatical ly clear ed wh en an interr upt is

processed.

TCON.4 TR0 Timer 0 Run control bit. If cleared, Timer 0 stops.

TCON.3 IE1 Interrupt 1 edge flag is set by hardware when the falling edge on external pin

int1 is observed. Cleared when an interrupt is processed.

TCON.2 IT1 I nterrupt 1 type control b i t. S elect s eith er the fa llin g edge or l ow l evel on i nput

pin to c aus e an i nterr upt.

TCON.1 IE0 Int errupt 0 edge flag is set by hardware when the falling edge on external pin

int0 is observed. Cleared when an interrupt is processed.

TCON.0 IT0 I nterrupt 0 type control b i t. S elect s eith er the fa llin g edge or l ow l evel on i nput

pin to c aus e interrupt.

Table 23: The TCON Register Bit Functions

Table 24 s pec i fies the com bin ati ons of operati on modes all owed fo r t imer 0 a nd ti mer 1:

Timer 1

Mode 0 Mode 1 Mode 2

Timer 0 - mode 0 YES YES YES

Timer 0 - mode 1 YES YES YES

Timer 0 - mode 2 Not all o wed Not all o wed YES

Table 24: Timer Modes

Timer/Counter Mode Control Reg ister ( PCON):

MSB LSB

SMOD

Table 25: The PCON Register

The SMOD bit in the PCON regist er do ubles th e baud rat e when set.

WD Timer (S oftware Watchdog Timer)

The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the

watchdog tim er is disabled and all r egi s ters are s et t o zero. The watchdog consists of a 16-bit co unter (WD T), a reload register

(WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the

internal reset signal becomes act ive.

Note: It is recommended to use the hardware watchdog timer inste ad of the softwar e watchdog timer.

WD Timer Start Procedure: Th e W D T i s s t ar t ed by s et tin g t h e SWDT flag. W hen the WDT reg ist er en ters the s tat e 0x7 CFF,

an asynchronous WDTS signal will become active. The signal WDT S s et s bi t 6 in t h e IP0 r egis ter and reques ts a reset st ate.

WDTS is cleared eith er by t he r eset si gn al or by c hangi ng the st at e of the W DT timer.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from

becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction

sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock

cycles. If this period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is

reloaded with the content of the WDTREL register and WDT is automatically reset. Since the WDT requires exact timing,

firm ware needs to be designed with special care in order to avoid unwanted WDT resets. TERIDIAN strongly discourages the

use of the software WDT.

Special Function Registers for the WD Timer

Int errupt Enable 0 Regist er (IEN0):

MSB LSB

EAL WDT ET2 ES0 ET1 EX1 ET0 EX0

Table 26: The IEN0 Register (see also Table 34)

Bit

Symbol

Function

IEN0.6 WDT Watchdog timer refresh flag.

Set to initiat e a refr esh of the watchdog timer. Must be set di r ectl y b efo re SWD T

is set to prevent an unintentional refr esh of the watchdog timer. WDT is reset by

hardware 12 clock cycles after it h as been set.

Table 27: The IEN0 Bit Functions ( see also Table 34)

Note: The remaining bits in the IEN0 register are not used for watchdog control

Int errupt Enable 1 Regist er (IEN1):

MSB LSB

EXEN2 SWDT EX6 EX5 EX4 EX3 EX2

Table 28: The IEN1 Register (see also Tables 35/36)

Bit

Symbol

Function

IEN1.6 SWDT Wat ch dog t imer start/r efres h f la g.

Set to acti vate/refresh th e watc hdog timer. When dir ectly s et a fter s ett in g WDT, a

watchdog time r refresh is perfor med. Bit SWDT is re set by the hardware 1 2 clo ck

cycles after it has been set.

Table 29: The IEN1 Bit Functions ( see also Tables 35/36)

Not e: T he r em aini ng bits in t he IEN1 register are not used for wat chdog control

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Int errupt Priorit y 0 Register (IP0):

MSB LSB

-- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Table 30: The IP0 Register (see also Table 46)

Bit

Symbol

Function

IP0.6 WDTS Watch dog t i mer status f l ag. Set when the watchdog tim er was started. Can be

r ead by software.

Table 31: The IP0 bit Functions (see also Table 46)

Not e: T he r em aini ng bits in t he IP0 register are not used for wat c hdog control

Watchdog Timer Reload Register (WDTREL):

MSB LSB

7 6 5 4 3 2 1 0

Table 32: The WDTREL Register

Bit

Symbol

Function

WDTREL.7 7 Pr escaler select bit. When set, the watchdog is clocked through an additi onal

divide-by-1 6 pr esc al er

WDTREL.6

WDTREL.0 6-0 Seven bit r eload val ue f or t he hi gh-b yte of the w atchdog t imer. Thi s value i s

loaded to the WDT when a refresh is triggered by a consecutive sett i ng of bits

WDT and SWDT.

Table 33: The WDTREL Bit Functions

The WDTREL register can be loaded and read at any time.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Interrupts

The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request f lag(s) located in a special

function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or

disabled by the enable bits in SFRs IEN0, IEN1, and IEN2.

External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the

71M6511/6511H, for example the CE, DIO, RTC EEPR OM interface, comparators.

Interrupt Overview : When an interr upt occurs, the MPU will vector to the predetermined address as shown in Table 51. Once

interrupt service has begun, it can be interrupted only by a higher priority int errupt . The interrupt service is terminated by a

return from instruction, "RETI". When a RETI instruction is performed, the processor will return to the instruction that would

have been next when the interrupt occurred.

When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of

wh eth er t he int erru pt i s en abled or di sabl ed. Eac h inter rupt flag is sam pled on ce per mac hin e cy cle, th en s amp les are p ol l ed

by the har dware. If the sam ple in dicates a pending interr upt when the interrupt is enabled, then the interr upt request fl ag is set.

On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector

address, if the following conditions are met:

• No inter rupt o f equal or higher pr iority is alr ead y in progress.

• An instruction is currently being executed and is not completed.

• Th e inst ruction in pro gres s is not RET I or a ny wr i te a cc ess to the reg isters I EN0, IEN 1, IEN2, IP0 or IP1.

Int errupt response will require a varying amount of time depending on t he state of the MPU when the interrupt occurs. If the

MPU is performing an i nterrupt service with equal or greater pr iorit y, the new i nterrupt will not be invoked. In other cases, the

response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This

includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL.

Special Function Registers for Interrupts:

Int errupt Enable 0 register (IE0)

MSB LSB

EAL WDT ES0 ET1 EX1 ET0 EX0

Table 34: The IEN0 Register

Bit Symbol Function

IEN0.7 EAL EAL=0 – disable a ll int errupts

IEN0.6 WDT Not used for interrupt control

ES0=0 – disable serial channel 0 interrupt

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

ET1=0 – disable timer 1 overflo w i nterrupt

EX1=0 – disable ext ern al interru pt 1

ET0=0 – disable timer 0 overflo w i nterrupt

EX0=0 – disable ext ern al interru pt 0

Table 35: The IEN0 Bit Functi ons

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Int errupt Enable 1 Regist er (IEN1)

MSB LSB

SWDT EX6 EX5 EX4 EX3 EX2

Table 36: The IEN1 Register

Bit Symbol Function

IEN1.7 -

IEN1.6 SWDT Not used for interrupt control

IEN1.5 EX6 EX6=0 – di sable external interru pt 6

IEN1.4 EX5 EX5=0 – di sable external interru pt 5

IEN1.3 EX4 EX4=0 – di sable external interru pt 4

IEN1.2 EX3 EX3=0 – di sable external interru pt 3

IEN1.1 EX2 EX2=0 – di sable external interru pt 2

IEN1.0 -

Table 37: The IEN1 Bit Functi ons

Int errupt Enable 2 register (IE2)

MSB LSB

- - - - - - - ES1

Table 38: The IEN2 Register

Bit Symbol Function

IEN2.0 ES1 ES1=0 – dis able ser ia l channel 1 interru pt

Table 39: The IEN2 Bit Functi ons

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Tim er/Counter Control Regi ste r (TCON)

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Table 40: The TCON Register

Bit Symbol Function

TCON.7 TF1 Ti mer 1 o verflow fla g

TCON.6 TR1 Not used for interrupt control

TCON.5 TF0 Ti mer 0 o verflow fla g

TCON.4 TR0 Not used for interrupt control

TCON.3 IE1 External interrupt 1 flag

TCON.2 IT1 External interrupt 1 type contr ol bit

TCON.1 IE0 External interrupt 0 flag

TCON.0 IT0 External interrupt 0 type contr ol bit

Table 41: The TCON Bit Functions

Interrupt Request regis te r (IRCON)

MSB LSB

EX6 IEX5 IEX4 IEX3 IEX2

Table 42: The IRCON Register

Bit Symbol Function

IRCON.7 -

IRCON.6 -

IRCON.5 IEX6 Exte rnal inte r rupt 6 edge flag

IRCON.4 IEX5 External interrupt 5 edge flag

IRCON.3 IEX4 External interrupt 4 edge flag

IRCON.2 IEX3 External interrupt 3 edge flag

IRCON.1 IEX2 External interrupt 2 edge flag

IRCON.0 -

Table 43: The IRCON Bit Functions

Note: Only TF0 and TF1 (timer 0 and tim er 1 overflow flag) will be automatically cleared by hardware when the service routine

is called (Signals T0ACK and T1ACK – port ISR – activ e hig h when t he servic e rou t ine is c alled ).

Extern al Interrupts

The ext ernal interrupts are connected as shown i n Table 44. The polarit y of int errupts 2 and 3 is programmable in the MPU.

Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4

through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to

achieve the edge polarity shown in Table 44.

SFR (speci al f unction register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has

its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6

enable and flag bits (see Table 45), and t hese int errupts must be clear ed by t he MP U soft w are.

External

Interrupt Connection Polarity Flag Reset

0 Digital I/O H igh Priority see DIO_Rx automatic

1 Dig ital I/O Low Priorit y see DIO_Rx automatic

2 Com parator 2 or 3 falling automatic

3 CE_BUSY falling automatic

4 Com parator 2 or 3 rising automatic

5 EEPROM busy falling automatic

6 XFER_BUSY OR RTC_1SEC falling manual

Table 44: Ex te rnal MPU Interrup ts

Interrupt 6 is edge-sensitive. The RTC_1SEC interrupt from the RTC and the XFER_BUSY interrupt from the CE are com-

bined using a logic OR function and the result is routed into interrupt 6. Therefore, both flags must be cleared at least once

durin g initializat ion , an d bot h fla gs must alw ays be cleared bef or e exiting t he int errupt servi ce rout in e ( IS R) for i nterr upt 6.

Note 1: If cleari ng of both fl ags is not perf ormed, then no edge can occur to trigger interrupt 6 later resulting i n t he I SR for the

XFER_BUSY ce asing to run.

Note 2: Clearing both flags reliably requires some care. Either flag can be set by hardware whil e interr upt 6 code is running on

behalf of the other interrupt. In this s i tuation, the unprocessed interrupt can create a lockout condition similar to the one in note

1. To preven t thi s l oc kout one m us t alw ays process both interru pt flags i n the same s ervic e r out ine.

Not e 3: A f ter a r eset f rom an in-circ uit emul ator, the IE_XFER flag may not be cleared because the CE may continue to run.

The fla gs fo r the RTC_1SEC and the XFER_BUS Y in te rrupts are located in the WDI SFR (add re ss 0xE8) .

Enable Bit Description Flag Bi t Description

EX0 Enable external interrupt 0 IE0 Exte rnal inte r rupt 0 flag

EX1 Enable external interrupt 1 IE1 External interrupt 1 flag

EX2 Enable external interrupt 2 IEX2 External int errupt 2 flag

EX3 Enable external interrupt 3 IEX3 External int errupt 3 flag

EX4 Enable external interrupt 4 IEX4 E x te rnal interrupt 4 flag

EX5 Enable external interrupt 5 IEX5 External int errupt 5 flag

EX6 Enable external interrupt 6 IEX6 External int errupt 6 flag

EX_XFER Enable XFER_BUSY interrupt IE_XFER XFER_BUSY interr upt flag

EX_RTC Enable RTC_1SEC interrupt IE_RTC RTC_1SEC interr upt flag

Table 45: Contr ol Bits for External Interrupts

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

In t errup t P rio rity Level Structure

All interrupt sources are combined in groups, as shown in Table 46:

Group

0 Ex ternal interrupt 0 Ser ial c hannel 1 in terr upt

1 Timer 0 inter ru pt - Ex ternal interrupt 2

2 Ex ternal interrupt 1 - Ex ternal interrupt 3

3 Timer 1 inter ru pt - Ex ternal interrupt 4

4 Serial channel 0 in terr upt - Ex ternal interrupt 5

5 - - Ex ternal interrupt 6

Table 46: Priority Level Gr oups

Each group of int errupt sources can be programm ed individually to one of four priority levels by setting or clearing one bit in

the special function register IP0 and one in IP1. I f r eq ues t s o f t h e same p r i ori t y l evel a r e r ecei v ed s imult a n eou sl y , an i nt er na l

polling sequenc e as per Table 50 determines which request is s ervic ed fi rs t .

IEN enable bits must be set to permit any of these int errupts to occur. Likewise, each int errupt has its own flag bit that is set by

the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,

which are OR-ed together, have their own enable and flag bits in additi on to the interrupt 6 enable and flag bits (see Table 45),

and these interrupts must be c l eared by the MPU software.

An overview of the interrupt structure is given in Figure 7.

Int errupt Priorit y 0 Register (IP0)

MSB LSB

-- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Table 47: The IP0 Register:

Note: WDTS is not used for interrupt controls

Int errupt Priorit y 1 Register (IP1)

MSB LSB

- - IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0

Table 48: The IP1 Register:

IP1.x IP0.x Priority Level

0 0 Level 0 ( lowes t )

0 1 Level1

1 0 Level2

1 1 Level3 ( highest)

Table 49: Priority Levels

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Ex ternal interrupt 0

Polling sequence

Serial channel 1 in terr upt

Timer 0 inter ru pt

Ex ternal interrupt 2

Ex ternal interrupt 1

Ex ternal interrupt 3

Timer 1 inter ru pt

Ex ternal interrupt 4

Serial channel 0 in terr upt

Ex ternal interrupt 5

Ex ternal interrupt 6

Table 50: Int errupt Polling Sequence

In t errup t Sources and Vectors

Table 51 shows the interrupts with their associated flags and vector addresses.

Int errupt Request Flag Description Interrupt Vector Address

IE0 Ex te rnal inte r rupt 0 0x0003

TF0 Timer 0 inter ru pt 0x000B

IE1 Ex te rnal inte rrupt 1 0x0013

TF1 Timer 1 inter ru pt 0x001B

RI0/TI0 Ser ia l channel 0 in terr upt 0x0023

RI1/TI1 Ser ia l channel 1 in terr upt 0x0083

IEX2 Ex te rnal inte r rupt 2 0x004B

IEX3 Ex te rnal inte r rupt 3 0x0053

IEX4 Ex te rnal inte r rupt 4 0x005B

IEX5 Ex te rnal inte r rupt 5 0x0063

IEX6 Ex te rnal inte r rupt 6 0x006B

Table 51: Interrupt V e ctors

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

IE0

External

Interrupt

Flags

RI1

TI1

Internal

Interrupt

Flags

Source

>=1

TF0

INT2

IE1

INT3

TF1

INT4

RI0

TI0 >=1

INT5

INT6

>=1

IRCON.1

I2FR

IRCON.2

I3FR

IRCON.3

IRCON.4

IRCON.5

IEN0.7

IP1.0/

IP0.0

IP1.1/

IP0.1

IP1.2/

IP0.2

IP1.3/

IP0.3

IP1.4/

IP0.4

IP1.5/

IP0.5

Interrupt

Control

Priority

Assignment

Interrupt

Vector

Polling Sequence

Interrupt

Enable

Logic and

Polarity

Selection

DIO

UART1

(optical)

Tim er 0

Compar-

ators

Compar-

ators

DIO

Tim er 1

CE_BUSY

UART0

EEPROM/

I2C

XFER_BUSY

RTC_1S

IEN0.0

IEN2.0

IEN0.1

IEN1.1

IEN0.2

IEN1.2

IEN0.3

IEN1.3

IEN0.4

IEN1.4

IEN1.5

Figure 7: Interrupt Structure

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

On-Chip Resources

DIO Por t s

The 71M6511/6511H includes up to 12 pi ns of general purpose digital I/O. These pins are dual functi on and can alternatively

be used as LCD drivers. Figure 8 shows a block diagram of the DI O section.

On reset or power-up, all DIO pins are inputs until they are configured for the desired direction. The pins are configured and

controlled by t he DIO and DIO_DIR r egi st ers (SFR s) a nd b y th e fi ve bit s of the I/ O r egi st er LCD_NUM (0x2020[4:0]). See the

description for LCD_NUM i n th e I /O RA M S ec ti o n f or a ta bl e l i st i n g th e a va i l a bl e segmen t pi n s vers u s DI O pins, depending on

the selection for LCD_NUM. Generally, increasing the value for LCD_NUM will configure an increasing number of general

purpose pins to be LCD segment pins, starting at the higher pin numbers.

COM0..3

LCD DISPLAY

DRIVER

DIGITAL I/O

LCD_EN

LCD_CLK

LCD_MODE

DIO_GP

SEG34/DIO14 ...

SEG37/DIO17

LCD_NUM

DIO_OUT

DIO_IN

LCD_NUM

PULSEV/W

SEG24/DIO4 ...

SEG31/DIO11

SEG0..SEG2

DIO_EEX

SEG3/SCLK

SEG4/SSDATA

SEG5/SFR

SEG6/SRDY

SEG7/

MUX_SYNC

SEG8..SEG19

Figure 8: DIO Ports Block Diagram

Each pin declared as DIO can be configured independentl y as an input or output wit h the bits of the DIO_DIRn registers. Table

52 lists the directi on registers and configurability associated wit h each group of DIO pins. Table 53 shows the configuration for

a DIO pin through its associated bit in its DIO_DIR register.

DIO

Pin numbe r

Dat a Register bit

DIO0=P0 (SFR 0x80)

DIO1=P1 (SFR 0x90)

Directi on Register

bit

DIO_DIR0 (SFR 0xA2)

DIO_DIR1 (SFR 0x91)

Internal Resources

Configurable -- -- -- -- Y Y Y Y Y Y Y Y -- -- N N

DIO

Pin numbe r

Dat a Register bit

DIO2=P2 (SFR 0xA0)

Directi on Register

bit

DIO_DIR2 (SFR 0xA1)

Internal Resources

Configurable N N -- -- -- -- -- --

Table 52: Data/Direction Registers and Int ernal Resources for DIO Pin Groups

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

DIO_DIR bit

0 1

DIO Pin Function input output

Table 53: DIO_DIR Contr ol Bit

Values read from and wr itt en i nto the DIO ports use the data registers P0, P1 and P2.

A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when

configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 52 for D IO pins

available for this option). This way, DIO pins can be tracked even if they are configured as outputs. This feature is useful for

pulse counti ng. The control resources selectabl e for the DIO pins are listed in Table 54. If more than one input is connected to

the same resource, the resource s are combine d using a logical OR.

DIO_R

Value Resource Selected for DIO Pin

0 NONE

1 Reserved

2 T0 (counter0 clock)

3 T1 (counter1 clock)

4 High priority I/O interrupt (INT0 rising)

5 Low priority I/O interrupt (INT1 rising)

6 High priority I/O interrup t (INT0 falling)

7 L ow prior it y I /O i nterr upt (IN T1 f all ing)

Table 54: Selectable Controls using the DIO_DIR Bits

Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6,

VARPULSE = DIO 7) using t he I/O RAM r egisters DIO_PW ( 0x2008[2]) and DIO_PV (0x2008[3]). In t his case, DIO6 and DIO7

are under CE cont r ol . D IO 4 a nd DIO 5 ca n be c o nf ig u r ed to im pl ement t h e EE PRO M I nt er f ac e by s et tin g t h e I/O R AM regi ster

DIO_EEX (0x2008[4]).

Physical Memory

Data bus address space is allocated t o on-chip me mo ry as sh own in Table 55.

Address

(hex) Memory

Technology Memory Type Typical Usage Wait States

(at 5MHz) Memory Size

(bytes)

0000-FFFF Flas h Memory Non-volatile

Program and non-volatile

data

0 64KB

0000-07FF

Static RAM

Battery-buffered

MPU data

2KB

1000-13FF

Static RAM

Volatile

CE data

1KB

2000-20FF Static RAM Volatile

Configuration RAM

(I/O RAM)

0 256

3000-3FFF

Static RAM

Volatile

CE Program code

4KB

Table 55: MPU Data Memory Map

Flash Memory: The 71M 6511 includes 64KB of on-chip flash memory. The flash memo ry is intende d to primarily conta in MPU

program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O

RAM . On power-up, before enabling the CE, the MPU must copy these images to their respective me mory locations.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Th e I/O RAM bit reg ist er FLASH66Z defines the pulse width for accessing flash memory. To minimize supply current draw,

thi s bit should be set to 1.

Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special

patt ern/sequence requir ements prevent inadvertent erasure of the flash mem ory.

The mass era se sequenc e is:

1. Write 1 t o the FLSH_MEEN bi t (S FR ad dres s 0 xB2[1].

2. Write pattern 0xAA to FLSH_ERASE (SFR addre ss 0x 94)

Note: The mass erase cycle can only be initiat ed when the ICE port is enabled.

The page erase sequence is:

1. Write the page addre ss to FLSH_PGADR (SFR address 0xB7[7:1]

2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94)

Writing to flash memory:

The MPU may write to the flash memory for non-volatile data storage or when implementing a boot-loader. The I/O RAM

between flash and XRAM w rites. Before setting FLSH_PWE, all interrupt s nee d to be disabled by se tting EA L =1. Afte r the w rite

operation, FLSH_PWE must be cle are d.

Th e or igin al stat e of a fl as h by te i s 0xFF (all bits ar e 1) . Ov erwriting programmed flash cells with a different value usually re-

quires that the cell i s erased first. Since cell s cannot be erased individually, the page has to be copied to RAM, foll owed by a

page erase. After this, the page can be updated in RAM and then writt en back to the flash m emory.

Writing to flash locations will affect the corresponding XRAM cells, i.e. 0x2000 to 0x20FF (I/O RAM), 0x0000 to

0x07FF (MPU RAM), plus CE DRAM and CE PRAM. It is critical to maint ain the integrity of the cells 0x2000…0x2007

as a mi nimum (where im portant system settings are stor ed) during the flash-write operat ion. This can be achieved by

excluding the critical addresses from the write operation.

MPU RAM: The 71M6511 includes 2KB of static RAM memory on-chip (XRAM), which are backed-up by the battery plus 256-

bytes of i nternal R A M in t he MPU core. The 2KB of static RAM are used for data storage during normal MPU operations.

CE DRAM: The C E D RA M is the data memory of the C E. The MPU can re ad and write the C E DRAM as the prima ry mea ns of

data com mu nicat ion between t he t wo proc ess or s.

CE PRAM: The CE PRAM is t he program memory of the CE. The CE PRAM has to be loaded with CE code before the CE

starts operating. CE PRAM cannot be accessed by the MPU when the CE is running.

Oscillator

The oscillator drives a standard 32.768kHz watch crystal (see Figure 9). Crystals of this type are accurate and do not require a

high current oscillator circuit. The oscillator in the TERIDIAN 71M6511 Power Meter IC has been designed specifically to

handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power

dissipat ion i s ver y low t o maxim ize the lifetime of any battery backup dev ice at tac hed to the VBAT pin.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

crystal

XOUT

XIN

71M651X

Figure 9: Os cillato r Circ uit

The oscillator should be placed as close as possible to the IC, and vias should be avoided. An external resistor

across the crystal m ust not be added.

Real-T ime Clock (RTC)

The RTC is driven directly by the crystal oscillator. In the absence of the 3.3V supply, the RTC is powered by the external

battery (VBAT p in). The RT C consists of a counter chain and output registers. The counter chain consists of se conds, minutes,

hours, day of week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own

output regist er. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since the

RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the

sam e (r equ ir es ei ther 2 or 3 rea ds) . At thi s poi nt, all RT C ou tp ut reg ister s w ill ha ve t he c or rec t tim e. Regard less of t he MPU

clock speed, RTC reads require one wait state.

The RTC i nt errupt must be enabled using t he I/O RAM register EX_RTC ( addr ess 0x2002[1]). RTC tim e is set by writing to the

I/O RAM registers RTC_SEC, RTC_MIN, through RTC_YR. Each byte written to RTC must be delayed at least 3 CK32 cycles

from any previous byte written to RTC.

Two time correction bits, the I/O RAM registers RTC_DEC_SEC (0x201C[1]) and RTC_INC_SEC (0x201C[0]) are provided to

adjust the RTC time. A pulse on one of these bit s causes the t ime to be decremented or i ncrem ented by an additi onal second

at the next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can

int egrate tem perature and correct the RTC time as necessary as discussed in temperature compensation.

LCD Dri vers

The 71M6511 contai ns 15 dedicated LCD segment pins, 5 LCD segment pins that rare shared wit h the SSI port and/ or other

functions, and an additional 12 multi-purpose pins (LCD/DIO) that may be configured as LCD segment drivers (see I/O RAM

cycle. At seven segments per digit, the LCD can be designed for 11 to 18 digits for display. Since each pixel is addressed

individually, the LCD display can be a combination of alphanumeric digits and enunciator symbols. The information to be

displayed is written into the lower four bits of I/O RAM registers LCD_SEG0 through LCD_SEG37. Bit 0 corresponds to the

s egmen t selected when COM0 pin i s activ e w hile bit 1 is allo cated to CO M 1.

The LCD driver circuitry is grouped into four common outputs (CO M 0 t o CO M 3) a nd up to 3 2 segment o utp uts ( see Table 56).

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Dedicated Segm ent Pins Shared w/ DIO4-DIO11 Shared w/ DIO14-DIO17

SEG0 SEG1 … SEG19 SEG24 … SEG31 SEG34 … SEG37

COM0 P0 P4 … P76 P80 … P108 P112 … P124

COM1 P1 P5 … P77 P81 … P109 P113 ... P125

COM2 P2 P6 … P78 P82 … P110 P114 … P126

COM3 P3 P7 … P79 P83 … P111 P115 … P127

Table 56: Liquid Crystal Display Segment Table (Typical)

Not e: P 0, P1, … Rep resent the pixel/segmen t n umb ers o n the LCD.

A charge pum p suitabl e for driving VLCD is included on-chip. This circuit creates 5V from the 3.3V supply. A contrast DAC is

provided that permits the LCD full-scale voltage to be adjusted between VLCD and 70% of VLCD. The LCD_NUM register

defin es the number of dual purpose pins used for LCD segm ent interf ace.

LCD Vol t age Boost Circu itry

A voltage boost circuit may be used to generate 5V from the 3.3V supply to support low-power 5V devices, such as LCDs.

Figure 10 sh ows a block diagram of the voltage boost circuitry including the voltage regulators for V2P5 and V2P5NV. When

activated using the I/O RAM register LCD_BSTEN (0x2020[7]), the boost circuitry provides an AC voltage at the VDRV output

pin (s ee th e Appli cat ions sec t ion for details).

GNDD

V3P3D

VBAT

VOLT

REG

0.1V

V2P5

VLCD

VDRV

VOLTAGE

BOOST

LCD_BSTEN

LCD_IBST

GNDD

GNDD GNDD

V2P5

V3P3DV2P5NV

Figure 10: LCD Volt age Boost Circuitry

UART (UART0) and Optical Port (UART1)

The 71M6511/6511H includes an interf ace to implement an IR or optical port. The pin OPT_TX is desi gned to directly drive an

external LED for transmitting data on an optical link (low-active). The pin OPT_RX, also low-active, is designed to sense the

input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated

UART port. OPT_TX can be tristated if it is desired to multiplex another I/O pin to the OPT_TX output. The control bit for the

OPT_TX output is the I/O RAM register OPT_TXDIS (0x2008[5]).

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Hardw are Reset M echanisms

Sever al condit io ns will ca use a har dware r eset of t he 71M6511/6511H:

• Voltage at the RESETZ pin low

• Voltage at the E_RST pin low

• Vo lt age at the V1 pi n b elow reset thres hold (VBIAS)

• The crystal fr equency monitor detected a crystal malfunction

• Hardware Watchdog timer

Reset Pi n (RE S ETZ)

When the RESETZ pin is pulled low (or when V1 < VBIAS), all digital activity in the chip stops while analog circuits are still

active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared.

Hardware Watchdog Timer

In addition to the basic software watchdog timer i ncluded in the 80515 MPU, an independent, r obust, fixed-duration, har dware

watchdog timer (W DT) i s included in the 71M6511/6511H. This timer will reset the MPU if it is not refreshed peri odically, and

can be used to recove r the MPU in situations where program control is lost.

The watchdog tim er uses the RTC crystal oscillator as its time base and requir es a reset under MPU program control at least

ev er y 1 . 5 s eco n d s. W hen th e W DT o v erf l o w oc c ur s, t he M PU i s m oment a ri l y res et a s if R ES ET Z wer e pulled low for half of a

crystal oscillator cycle. Thus, after 4100 cycles of the CK32 (32768Hz clock), the MPU program will be launched fr om address

00.

An I/O RAM r egister status bit, WD_OVF (0x2002[ 2]), is set when WDT overflow occurs. This bit is powered by the V BAT

pin and can be read by the MPU to determine if the part is initializing after a W DT overflow event or aft er a power up. After

r ead in g this bit, MP U f irmw are must clear WD_OVF. The WD_OVF bit i s also clear ed by the RESET Z pin.

The watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, WD_OVF is set and a

s ystem reset will be performed when t he crysta l oscillator r esumes .

There is no internal digital state that deactivates the WDT. For debug purposes, however, t he WDT can be disabled by tying

the V1 pin to V3P3 (see Figure 11 and WD Disable Threshold [V1-V3P3A] in the Comparator Section of the Electrical

Sp ec i f i ca tio ns ). O f co ur s e, t hi s al s o d eac tiv at es t h e po w er f au l t d et ec ti on implem ented with V1. Since there is no way i n firm-

ware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the MPU might find itself in, it will be

reset to a known state upon watchdog timer overflow.

In normal operation, t he WDT is r eset by peri odically writing a one to the WDT_RST bit. The watchdog timer i s also reset when

W AKE=0 and, during development, when a 0x14 command is received from the ICE port.

Crystal Frequency Monit or

The hardware watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, the I/O RAM

r egister WD_OV F i s set and a system r eset will be performed w hen th e c ry stal os c il lator resumes.

V1 Pin

Th e c omp ar a to r at th e V 1 pi n co n tr ol s th e s t at e o f th e d i git al ci r c ui tr y o n t h e chip. W hen V1 < VBIAS (or when the RESTZ pin

is pull ed low), all di gital activity in t he chip s tops while analog circuits including the oscill ator and RTC module are stil l active.

Additionally, when V1 < VBIAS, all I/O RAM bits are cleared. As long as V1 is greater than VBIAS, the int ernal 2.5V regulator

wil l continu e to p rovid e power to t he digital s ectio n.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

V3P3

V3P3 -

400mV

V3P3-10mV

VBIAS

Battery or

reset

mode

Normal

operation,

WDT

enabled

WDT dis-

abled

when

(V1 < VBIAS)

the battery is

enabled

Figure 11: Voltage Range for V1

I2C Int erf ace ( E E P ROM)

A dedicat ed 2-pin s eri al i n t erf a c e im pl em en t s a n I 2C d ri v er that can be used to communicate with external EEPROM devi ces.

The interface can be multiplexed onto the DIO pins DIO4 (SCK) and DIO5 (SDA) by setting the I/O RAM register DIO_EEX

(0x2008[4]). The MPU comm unicates with the interface through two SFR regist ers: EEDATA (0x9E) and EECTRL (0x9F). If the

MPU wishes to wri t e a byte of data to EEPROM, it places the data i n EEDATA and t hen writ es the ‘Transm it ’ code to EECTRL.

Th e w r i t e t o EECTRL initiat es the transmit sequence. By observi ng the BUSY bit in EECTRL the MPU can determ ine when the

transmit operation is finished (i.e. when the BUSY bit transitions from 1 to 0). INT5 is also asserted when BUSY fal ls. The M P U

can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.

A byte is read by writing the ‘Receive’ command to EECTRL and waiting for BUSY to fal l. Up on c ompl et ion , t he r ecei ved data

will appear in EEDATA.

The serial transmit and receive clock is 78kHz during each transmission, and SCL is held in a high state until the next

transmission. The bits in EECTRL are shown in Table 57.

The EEPROM interface can als o be operated by controlling the DIO 4 and DIO5 pins directly. However, controlling DIO4 and

DIO5 directly is discouraged, because it may tie up the MPU to the point where it may becom e too busy to process

interrupts.

Note: Clock str etching and multi-maste r operat ion is not supported for the I2C inter face.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Status

Bit Name Read/

Write Reset

State Polarity Description

7 ERROR R 0 Positive 1 when an illegal command is received.

6 BUSY R 0 Positive 1 when s erial data bus is busy.

5 RX_ACK R 1 Negative 0 indicates that the EEPROM sent an ACK bit.

4 TX_ACK R 1 Negative 0 indicates when an ACK bit has been sent to the EEPROM

3-0 CMD[3:0

] W 0 Positive,

s ee C M D

Table

CMD Operation

0 No-op. Applying the no-op command will stop the I2C clock

( SCK , DIO4) . Fail ure to is sue t he no-op comm and will keep

the SCK signal toggling.

2 R eceive a byt e f rom EEPROM an d s end ACK .

3 Transmit a byte to EEPROM.

5 Issue a ‘STOP’ sequence.

6 R eceive t he l ast byt e from E EPROM an d do not s end ACK .

9 Is sue a ‘ST ART ’ seq uence.

Others No Oper ati on, set the ERROR bit.

Table 57: EECTRL Status Bits

In t ernal Clo cks and Clo ck Divid ers

All internal clocks are based on t he watch crystal f requency (CK32 = 32,768Hz) applied to the XIN and XOUT pins. The PLL

multiplies this frequency by 150 to 4.9152MHz. This frequency is supplied to the ADC, the FIR filter (CKFIR), the clock test

output pin (CKTEST), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU

( CKMPU) and one for the CE ( CKC E).

The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2-MPU_DIV Hz where

MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down to

38.4kHz.

The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM register

ECK_DIS (0x2005[5]) is asserted by the MPU.

Battery

The VBAT pin provides an input for an external battery that can be used to support the crystal oscillator, RTC, the WD_OVF bit

and XRAM in the absence of the mai n power supply. If the battery is not used, the VBAT pin should be connected to V3P3.

Internal Voltages (VBIAS, VBAT, V2P5)

The 71M6511 requires two supply voltages, V3P3A, for the analog section, and V3P3D, for the digital section. Both voltages

can be tied together outside the chip. The internal supply voltage V2P5 is generated by a regulator from the 3.3V supplies.

The batt ery volt age, VBAT, is required when crystal oscillat or, RTC and XRAM are required to keep operating whil e V3P3D is

removed (battery mode). VBAT, usually supplied by an external battery, powers crystal oscillator, RTC and XRAM (and the

WD_OVF bit).

VBIAS (1.5V) is generated int ernally and used for the V1 comparator and for the reference of the temperature sensor.

Test Ports

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

TMU XO UT P i n: One out of 16 digital or 4 analog signals can be s elected to be output on the TMUXOUT pin. The function of

the multiplexer is controlled with the I/O RAM register TMUX (0x2000[3:0]), as shown in Table 58.

TMUX[3:0] Mode Function

0 analog DGND

1 analog IBIAS

2 analog PLL_2.5V

3 analog VBIAS

4 digital RTM (R eal ti me outp ut from CE)

5 digital WDTR_EN (Comparator 1 Output AND V1LT3)

6 digital reserved

7 digital reserved

8 digital RXD (from Optical interface)

9 digital MUX_SYNC

A digital CK_10M

B digital CK_MPU

C -- reserv ed f or produ ction test

D digital RTCLK

E digital CE_BUSY

F digital XFER_BUSY

Table 58: TMUX[3:0] Selections

Em ulator Port: The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX provides control of the MPU through

an external in-ci rcui t emulator . Th e emulat or p ort is comp atible w ith the ADM51 emula tors manufa ctur ed by Sig num Systems .

The s ig nals of t he emulat or po r t ha ve weak pull-ups. Adding 1kΩ pull-up resistors on the PCB is recommended.

Real-Time Monitor: The RTM output of the CE is available as one of the digital mu ltiple xe r options. RTM data is read from the

CE DRAM locations specifi ed by I/O RAM registers RTM0, RTM1, RTM2, and RTM3 aft er the rise of MUX_SYNC. The RTM can

be enabled and disabled with I/O RAM register RTM_EN. The RTM output i s clocked by CKTEST. Each RTM word is clocked

out in 35 cycles and contains a leading flag bit. Figure 13 in th e Syst em Timi ng Sect ion illust rates th e R TM o utput f or mat. RTM

is low when not in use.

SSI Int erf a ce: A hi gh -speed seri al interface with handshake capability is available to send a contiguous block of CE data to an

external data logger or DSP. The block of data, configurable as to location and size, is sent starting 1 cycle of 32kHz before

each CE code pass begins. If the block of data is big enough that transmission has not completed when the code pass begins,

it wi ll complete during the CE code pass wit h no timing impact to the CE or the serial data. In this case, care m ust be taken

that the transmitted data is not modified unexpectedly by t he CE. The SSI i nterface is enabled by the SSI_EN bit and consists

of SCLK, SSDATA, and SFR as outputs and, optionally, SRDY as input. The interface is compatible with 16bit and 32bit

processors. The operation of each pin is as follows:

SCLK is the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls

whether SCLK runs continuously or is gated off when no SSI activit y is occurring. If SCLK is gated, it will begin 3 cycles before

SFR rises and will pers ist 3 c ycles after the l ast data bit is o ut put.

The pins used for the SSI are m ultiplexed with the LCD segment outputs, as shown in Table 59. Thus, the LCD should be

disabled when the SSI is i n use.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

SSI Signal LCD Segment

Output Pin

SCLK SEG3

SSDATA SEG4

SFR SEG5

SRDY SEG6

Table 59: SSI Pin Assignment

SRDY is an optional handshake input that indicates that the DSP or data-logging device is ready to receive data. SRDY must

be high to enable SFR to rise and initiate the transfer of the next field. It is expected that SRDY changes state on the rising

edges of SCLK. If SRDY is not high when the SSI port is ready to transmit the next field, transmission will be delayed until it is.

SRDY is ignored except at the beginning of a field transmission. If SRDY is not enabled (by SSI_RDYEN), the SSI port will

behave as if SRDY is always one.

SSDATA is the serial output data. SSDATA changes on the rising edge of SCLK and outputs the cont ents of a block of CE

RAM words starting with address SSI_STRT and ending with SSI_END. T he words ar e out put M SB firs t.

Th e f i eld si ze i s s et w it h th e SSI_FSIZE register: 0 entire data block, 1-8 bit fi elds, 2-16 bit fi elds, 3-32 bit fi elds. The polarity of

the SFR pulse can be inverted with SSI_FPOL. If SRDY does not delay it, the first SFR pulse in a fram e will rise on the third

SCLK after MUX_SYNC (fourth SCLK if 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger

or DSP.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

FUNCT IONAL DESCRIPTION

Theory of Operation

The ener gy deliv ered by a power s our ce int o a load ca n be expr ess ed as:

∫

tdttItVE

)()(

Assuming phase angles are consta nt, the follow ing for mulae apply:

 P = Rea l En erg y [Wh] = V * A * cos φ* t

 Q = R eac t ive En ergy [ VAR h] = V * A * sin φ * t

 S = Apparent Energy [VAh] =

QP +

For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change

constantly. Thus, simple RMS m easurem ents ar e inherently inaccurate. A modern solid-st at e el ect ri cit y m eter I C such as the

71M6511/6511H functions by em ulating the integral operation above, i.e. it processes current and voltage samples through an

ADC at a constant frequency. As long as the ADC resolution is high enough and the sampl e frequency is beyond the harmonic

range of interest, the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantit y f or

the momentary energ y. Summin g up t he momen tary energ y quan t ities over t i me will res ult i n accumul ated energy .

-500

-400

-300

-200

-100

100

200

300

400

500

0 5 10 15 20

time [ms]

V [V], I [A], P [Ws]

Current [A]

V oltage [V]

Energy per Interval [Ws]

A ccumulated Energy [Ws]

Figure 12: Voltage. Curr ent, Moment ary and Accumulated Energy

Figure 12 shows the s hapes of V(t), I(t), the mom entary and the accumulat ed energy, resulting from 50 samples of the voltage

and current signals over a period of 20ms. The application of 240VAC and 100A results in an accumulation of 480Ws over the

20ms p eri od, as indi ca ted by the Accum ulated Pow er c urve.

The desc ribed s ampling meth od work s reliabl y , ev en in th e pres ence of dynamic p hase shift and har mo nic dist or tion.

System Timing Summary

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Figure 13 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output

streams. In this example, MUX_DIV = 1 (four mux states) and FIR_LEN = 1 (3 CK32 cycles). Since FIR filter conversions

require two or three CK32 cycles, the duration of each MUX cycl e is 1 + 2 * st at es defined by MUX_DIV if FIR_LEN = 0, and 1

+ 3 * states defi ned by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 cycle.

Each CE program pass begins when MUX_SYNC falls. Dependi ng on the length of the CE program, it may continue running

until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the

same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete.

The CE code is designed to tol erate sudden changes in ADC data. The exact CK count when each ADC value is loaded int o

DRAM is sh own in Figure 13.

Figure 13 also shows that the two serial data stre ams, RTM and S SI, begin transmit ting at the be ginning of MUX_SYNC . R TM ,

consisting of 140 CK cycles, will always finish befor e the next code pass starts. The SSI port begins transmitting at the sam e

tim e as RTM, but may significantly overrun the next code pass if a lar ge block of data is required. Neither the CE nor the SSI

port will be affected by this overlap.

CK32

MUX STATE 0

MUX_DIV Conversions (MUX_DIV=4 is shown) Settle

ADC MUX Frame

ADC EXECUTION

MUX_SYNC

CE_EXECUTION

RTM 140

MAX CK COUNT

0450

150

900 1350 1800

ADC0 ADC1 ADC2 ADC3

CK COUNT = CE_ CYCLES + floor((CE _CYCLES + 2) / 5)

ADC, CE an d S E RIAL TIMING

NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNT S.

2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.

3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.

CE_BUSY

XFER_BUSY INITIATED BY A CE OPCODE AT END OF SUM INTERVAL

ADC TIMING

CE TIMING

RTM and SSI TIMING

1 2 3

BEGIN SSI TRANSFERLAST SSI TRANSFER

SSI

Figure 13: Timing Relati onship between ADC MUX, CE, and Serial Transfers

Figure 14, Figure 15, and Figure 16 show the RTM an d S SI tim i ng, respectiv ely.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

CKTEST

TMUXOUT/RTM

FLAG

RTM DATA0 (32 bits)

LSB

SIGN

LSB

SIGN

RTM DATA1 (32 bits)

LSB

SIGN

RTM DATA2 (32 bits)

RTM DATA3 (32 bits)

0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31

FLAG FLAG FLAG

MUX_SYNC

CK32

Figure 14: RTM Output Format

SCLK (Output)

SSDATA (Output)

SFR (Output)

SRDY (Input)

31 30 16 15 1 0 31

SSI_BEG

30 16 15 1 0 31

SSI_BEG+1

1 0

SSI_END

If 16bit f i el ds If 32bit f i el ds

If SSI_CKGATE =1 If SSI_CKGATE =1

MUX_SYNC

Figure 15: SSI Timing , (SSI_FPOL = SSI_RDYPOL = 0)

SC L K (Out put)

SSDATA (Output)

SF R (O utput)

SR D Y (Input)

31 30 16 15 14 13

16 16 16 1229 18 17

Next field is delayed while SRDY is low

Figure 16: S SI Timin g , 1 6-bit Field Example (External Device Delays SRDY)

SFR is the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entir e data block as a single

f i el d, a s m ul tipl e 1 6 -bit fields, or as m ul t i pl e 3 2 -bit fi elds. The SFR pulse is one SCLK clock cycle wide, changes stat e on the

r ising edge of SCLK and prec edes th e fi rst bit of each field.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Data Flo w

The data flow between CE and MPU is shown in Figure 17. In a typical application, the 32-bit compute engine (CE)

sequentiall y processes the samples from the voltage inputs on pins IA, VA, and IB, performing calculations to measure active

power (W h), r eactive power (VARh), A2h, and V2h for fo ur-quadrant metering. These m easurem ents are then accessed by t he

MPU, processed further and output using the peri pheral devices avail able to the MPU.

CE MPU

Pre-

Processor Post-

Processor

IRQ

Processed

Metering

Data

Pulses

I/O RAM (Configuration RAM)

Samples Data

Figure 17: MPU/CE Data Flow

CE/M P U Communication

Figure 18 show s the functional relationship between CE and MPU. The CE is controll ed by the MPU via shared registers in the

I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY,

which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively

processing data. This signal will occur once every multi plexer cycle. XFER_BUSY indicates that the CE is updating data to the

output region of the CE RAM. This will occur whenev er the CE has finished generating a sum by completing an accumulation

interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the

XFER_BUSY and CE_BUSY signals.

Figure 19 shows the s equenc e of events between CE and MPU upon reset or power-u p. In a typica l application, the sequence

of events is as follows:

1) Upon power-up, t he MP U ini tializes t he har dware, includi ng disablin g th e CE

2) The MPU loads the code for the CE into the CE PRAM

3) Th e M PU loads CE data into the CE DRAM.

4) Th e M PU st arts the C E by setting t he CE_EN bit i n t he I/O R AM.

5) The CE then repeti ti vely executes it s code, generating results and storing them in the CE DRAM

It is important to note that the length of the accumulation interval, as determined by NACC, the product of SUM_CYCLES and

PRE_SAMPS is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), t he r esulting

accumulation interval is:

ACC

75.999

62.2520

2520

32768

4260 ==

⋅

This means that accurate tim e m easurements should be based on the RTC, not the accumulation interval.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

I/O RAM (CONFIGURATION RAM)

MPU

PULSES

DATA

INTERRUPTS

DISPLAY (me-

mory-mapped

LCD segments)

DIO

EEPROM

(I2C)

SERIAL

(UART0/1)

SAMPLES

APULSEW

APULSER

VAR (DIO7) W (DIO6)

VARSUM

WSUM

ADC

EXT_PULSE

CE_BUSY

XFER_BUSY

Mux Ctrl.

Figure 18: MPU/CE Com munication (Functional)

The MPU will wait for the CE to signal that fresh data is ready (the XFER interrupt). It will read the data and perform additional

processing such as energy accumulation.

CE_EN

CE PRAM

COMPUTATION

ENGINE

CE DRAM

FLASH

MPU

XFER Interrupt

Figure 19: MPU /CE Communicat ion (Processing Sequence)

Fau lt, Reset, Power-Up

Reset Mod e: Whe n the R ES ETZ pin is pulled low or when V1 < VBIAS, all digital activity in the chip stops while analog circuits

are still active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared. As long as V1, the

input voltage at the power fault block, is greater than VBIAS, the internal 2.5V regulator will continue to provide power to the

digital secti on.

Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100

cycles of the real time clock after RESETZ goes high, at which time the MPU will begin executing its preboot and boot

s equences from addr ess 00. See the sec urity sectio n f or more d esc ript ion of preb oot and boot .

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Power-Up: After p o wer -up, the 71M6511/ 6511H is in reset as long as V1 < VBIAS. As soon as V1 exceeds VBIAS, the reset

t im er i s st art ed whi ch tak es th e MPU out of r eset aft er 4100 oscill ato r cy cl es ( see Figure 20) . Th e MPU th en i nit iat es it s pr e-

boot phase lasting 32 cycles. The supply current will be low but not zero duri ng power-up. It will increase, once V1 exceeds

VBIAS and will increase to the nominal value once the preboot phase starts. The supply current may then be reduced under

firm ware control, followi ng the steps specifi ed in Battery Operation and Power Save Modes.

V3P3

SUPPLY CURRENT

3.3V

1.5V

PRE-

BOOT

RESET TIMER FIRMWARE HAS CONTROL OVER CHIP...

1ms

V2P5

POWER

DOWN

V1 > VBIAS

PWR

0mA

nominal

125ms

Figure 20: Timing Diagr am for Voltages, Current and Operation Modes after Power-Up

Battery O peration

W hen V1 is lower than VBIAS, the external battery will power the followi ng parts of the 71M6511/6511H:

• RTC

• Cryst al o scillator cir c uit r y

• MPU XRAM

• WD_OVF bit

Power Save Modes

In normal mode of operation, running on 3.3V supply, various resources of the 71M6511/6511H may be shut down by the

MPU firmware in order to reduce power consumption while other essential resources such as UARTs may remain active.

Table 60 o utl in es these res ou rc es and thei r ty pical cur ren t con sumption (bas ed on initial condition MPU_DIV = 0) .

Power Saving Measur e

Software Control

Typical

Savings

Disable the C E CE_EN = 0 0.16mA

Disable the ADC ADC_DIS = 1 1.8mA

Disable c lock test out put CKT EST CKOUTDIS = 1 0.6mA

Disable emulator clock EC K _DIS = 1 *) 0.1mA

Set flash rea d pulse timing t o 33 ns FLASH66Z =1 0.04mA

Disable the LCD v oltag e boost c i rcui t ry LCD_BSTEN = 0 0.9mA

Disable RTM o utput s RTM_EN = 0 0.01mA

Incr ease t he c lock divid er for the M PU MPU_DIV = X 0.4mA/MHz

*) This bit is to be us ed with caution! Inadvertently setti ng this bit will inhibit access to the part with the ICE i nterface and thus

preclude flash erase and programming operations.

Table 60: Power Saving Measures

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Temperat ure Comp ensation

Int ernal Compensati on: The internal voltage reference is cali brated during device m anufacture. Trim data is stored in on-chip

fuses.

For the 71M6511, the temperature coefficients TC1 and TC2 are given as constants that represent typical component

behavior.

For the 71M6511H, the temperature characteristics of the chip are measured during production and then stored in the fuse

registers TRIMBGA, TRIMBGB and TRIMM[2:0]. TC1 and TC2 can be derived from the fuses by using the relations given in the

Elect r ical Specif ications s ectio n. T C 1 and TC2 can be f urther pro ces sed to g enerate the coef fi cients PPMC and PPMC2.

TRIMM[2 :0], T R IMBGA and TRIMBGB are read by first wr it in g either 4, 5 or 6 to TRIMSEL (0x20FD) and then reading the value

of TRIM (0x20FF).

When the EXT_TEMP register in CE DRAM (address 0x38) is set to 0, the CE automatically compensates for temperature

errors by controlling the GAIN_ADJ r egis ter (address 0x2E) based on the PPMC, PPMC2, and TEMP_X regi st er v alu es. In th e

case of internal compensation, GAIN_ADJ is an output of the CE.

External Compensation: Rather than internally compensating for the temperature variation, the bandgap temperature is

provided to the embedded MPU, which then may digitally compensate the power outputs. This permits a system-wide

temperat ure correction over the entir e system rather than local to the chip. The inc orporated thermal c oefficients may include

the current sensors , the voltage se nsors, and other influence s. Since the band gap is chopper stabilize d via the CHOP_EN bits,

the mos t signi fi cant l ong-term drift mechanism in the voltage reference is re moved.

W hen the EXT_TEMP reg ister i n CE DRAM is s et to 15, t he CE ig nor es t he PPMC, PPMC2, and TEMP_X r egister v alues and

applies the gain supplied by the MPU in GAIN_ADJ. E xt er n al comp en s at i on ena b l es t h e MP U t o c on tr o l t he C E g ai n ba sed o n

any variable, and when EXT_TEMP = 15, GAIN_ADJ is an input to the CE.

Chopping Circuitry

As explained in the hardware section, the bits of the I/O RAM register CHOP_ENA[1:0] have to be toggled in between

m ult iplex er cycles t o achieve t he desired eli minati on of DC off set.

Th e amp l if i er wi t hin t h e r ef er en c e i s aut o -zeroed by m eans of an internal signal that is controlled by the CHOP_EN b its. W h en

t his si gnal is HIG H, the c onnecti on of t he am plif ier i np uts i s rev ers ed. Th is preser ves th e ov era ll pol ari ty of t he am pli fi er gain

but i nvert s t he input offset. By alternately reversi ng the connecti on, the offs et of the amplifier is averaged to zero. The two bits

of the CHOP_EN r egister have the function spec i fi ed in Table 61.

CHOP_EN[1] CHOP_EN[0] Function

0 0 Toggle chop signal

0 1 Reference connection positive

1 0 Reference co nnect ion r ever sed

1 1 Toggle chop signal

Table 61: CHOP_EN Bits

For automatic chopping, the CHOP_EN bits are set to either 00 or 11. In this mode, the polarity of the signals feeding the

reference amplifier will be automatically toggled for each multiplexer cycle as shown in Figure 21. With an even number of

m ult iplex er cycles i n eac h accumulatio n interval, the numb er of cy cles with positive r eference c onnectio n will equal t he n umber

of cycles with reversed connection, and the offset for each sampled signal will be averaged to zero. This sequence is

acceptable when only the primar y signals (meter voltage, meter current) are of interest.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Accumulation Interval m

MUX

cycle n

MUX

cycle 2 MUX

cycle 3

Chop Polarity

Positive Positive Positive Positive

Re-

versed Re-

versed

MUX

cycle n

MUX

cycle 1 MUX

cycle 1

Accumulation Interval m+1

CE_BUSY interrupt

(falling edge)

XFER_BUSY interrupt

(falling edge)

Accumulation Interval m+2

Positive Positive

Re-

versed

Figure 21: Chop Polarity w/ Automatic Chopping

If temperature compensation or accurate reading of the die temperature is required, alternate multiplexer cycles have to be

inserted in between the regular cycles. This is done under MPU firmware control by asserting the MUX_ALT bit whenever

necessary. Since die temperature usually changes very slowly, alternate multiplexer cycles have to be inserted very

infrequently. Usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each

XFER _BU SY inter rup t . T his sequence is shown in Figure 22.

Accumulation Interval m

MUX

cycle n

MUX

cycle 2 MUX

cycle 3

Chop Polar it y

Positive Positive Positive Positive

Re-

versed Re-

versed

MUX

cycle n

Accumulation Interval m+1

alt. MUX

cycle alt. MUX

cycle

CE_BUSY interrupt

XFER_BUSY interrupt

Accumulation Interval m+2

Positive Positive

Re-

versed

MUX_ALT

Figure 22: Sequence with Alternate Multiplexer Cycles

This sequence has the disadvantage that the alternate multiplexer cycle is always operated with positive connection.

Consequently, DC offset will appear on the tem perature m easurem ent, which wi ll decrease the accuracy of this m easurem ent

and thus cause temperature reading and compensation to be less accurate.

The sequence shown in Figure 23 uses the CHOP_EN bits to control the chopper polarity after each XFER_BUSY interrupt.

CHOP_EN is controlled to alternate between 10 (positive) and 01 (reversed) for the first multiplexer cycle following each

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

XFER_BUSY interrupt. After these first two cycles, CHOP_EN returns t o 11 (automatic toggle). The val ue of CHOP_EN, wh en

set after the XFER_BUSY interrupt, is in force for the entire following multiplexer cycle.

When using this sequence, the alternate multiplexer cycle is toggled between positive and reversed connection resulting in

accurate temperature measurement.

An example for proper application of the CHOP_EN bits can be found in the Demo Code shipped with the 6511 and 6511

Demo Ki ts. Fir mware implem entat io ns sh ould closel y follow th is example.

alt. MUX

cycle alt. MUX

cycle

Accum ulation Interval m Accumul a tion Interval m+1

Positive Positive

Positive Positive Positive

Accum ulation Interval m+2

Positive Positive

re-

versed re-

versed

MUX

cycle 2 MUX

cycle 2

MUX

cycle 3 MUX

cycle 3

MUX

cycle n MUX

cycle n

Chop Polarity

01 11 01 11(11) (11) (11) (11)(11) (11)(11) 10 11 (11)

CHOP_EN

(11)

CE_BUSY interrupt

XFER_BUSY interrupt

MUX_ALT

Figure 23: Sequence with Alternate Multiplexer Cycl es and Controlled Chopping

Internal/External Pulse Generation and Pulse Counting

The CE is the source for pulses. It can generate pulses directly based on the voltage and current inputs and the configured

pulse generation parameters. This is called “internal pulse generation”, and applies when the CE RAM register EXT_PULSE

(address 0x37) equals 0. Alternatively, the CE can be configured to generate pulses based on registers t hat are controlled by

the MPU (“external pul se generati on”), i.e. when the r egister EXT_PULSE equals 15. In the case of external pulse generati on,

the M P U writes values to the CE reg isters APULSEW (0x26) and APULSER (0x27).

Th e p u l s e r at e, u s u al ly i nv er s el y exp r essed a s “ Kh ” ( a nd measured in Wh per puls e), is determi ned by the CE RAM registers

WRATE, PULSE_SLOW, PULSE_FAST, In_8, a s wel l as by t he s ensor scalin g VMAX and IMAX per the equation:

]/[

8_ 1132.47 pulseWh

XNWRATEIn IMAXVMAX

ACC

⋅⋅⋅

⋅⋅

where

In_8 is the gain factor (1 or 8) controlled by the CE variable In_SHUNT,

X is the pulse gain factor controlled by the CE variables PULSE_SLOW and PULSE_FAST

NACC is the accumu lation coun t (PRE_SAMPS * SUM_CYCLES)

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Program Security

When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked.

This guarant ees the securit y of the user’s MPU and CE program code. Security is enabl ed by MPU code that is executed in a

32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to

perform a global erase of the flash memory, followed by a chip reset. Global flash erase also clears the CE PRAM.

The fi r st 32 cycles of t he MPU boot code are call ed the preb oot phase because during this phase the ICE is inhi bited. A read-

only st at us bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of the preboot sequence, the

ICE can be enabled and is permitt ed to take control of the MPU.

SECURE (SFR 0xB2[6]), the security enable bit, is res et w he n ever th e MP U i s r es et . H ar d w ar e a s s ociat ed w it h t h e bi t p erm it s

only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once

SECURE i s set , t he pr eboot c ode is protected and no external read of program code is possible .

Specifically, when SECURE is set:

• Th e IC E is li mited to bul k fl ash era se o nly.

• Page zero of fl ash memory, the preferred location for the user’s preboot code, m ay not be page-erased by either MPU or

ICE. Page zero may on ly be erased with globa l flash erase . Note that global flash e rase erase s CE program R AM w he the r

SECURE i s set or no t.

• Writes to page zero, whether by MPU or ICE, are inhibited.

The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE

interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ICE

Int erface description).

Additionally, by se tting the I/O RAM re gister ECK_DIS to 1, the emulator clo ck is disable d, inhibiting access to the program with

the emu lator . See the cautionary note in the I/O RAM Register descri ption!

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

FIRMWARE INTERFACE

I/O RAM MAP – In Numerical Order

‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and

should not be changed.

Name

Addr

Bi t 7

Bi t 6

Bi t 5

Bi t 4

Bi t 3

Bi t 2

Bi t 1

Bi t 0

Configuration:

CE0

2000

EQU[2:0]

CE_EN

TMUX[3:0]

CE1

2001

PRE_SAMPS[1:0] SUM_CYCLES[5:0]

CE2

2002

MUX_DIV[1:0] CHOP_EN[1:0] RTM_EN WD_OVF EX_RTC EX_XFR

COMP0

2003

RESERVED

COMP_STAT[0]

CONFIG0

2004

VREF_CAL RESERVED CKOUT_DIS VREF_DIS MPU_DIV

CONFIG1

2005

RESERVED ECK_DIS FIR_LEN ADC_DIS MUX_ALT FLASH66Z MUX_E

VERSION

2006

VERSION[7:0]

Digital I/O:

DIO0

2008

OPT_TXDIS

DIO_EEX

DIO_PW

DIO_PV

DIO1

2009

RESERVED

DIO2

200A

RESERVED

DIO3

200B

DIO_R5[2:0]

DIO_R4[2:0]

DIO4

200C

DIO_R7[2:0]

DIO_R6[2:0]

DIO5

200D

DIO_R9[2:0]

DIO_R8[2:0]

DIO6

200E

DIO_R11[2:0]

DIO_R10[2:0]

Real Time Clock:

RTC0

2015

RTC_SEC[5:0]

RTC1

2016

RTC_MIN[5:0]

RTC2

2017

RTC_HR[4:0]

RTC3

2018

RTC_DAY[2:0]

RTC4

2019

RTC_DATE[4:0]

RTC5

201A

RTC_MO[3:0]

RTC6

201B

RTC_YR[7:0]

RTC7

201C

RTC_DEC_SEC

RTC_INC_SEC

LCD Di spl ay Interface:

LCDX

2020

LCD_BSTEN

LCD_NUM[4:0]

LCDY

2021

LCD_EN

LCD_MODE[2:0]

LCD_CLK[1:0]

LCDZ

2022

LCD_FS[4:0]

LCD0

2030

LCD_SEG0[3:0]

LCD1

2031

LCD_SEG1[3:0]

…

LCD19

2043

LCD_SEG19[3:0]

LCD20

2044

RESERVED

…

LCD23

2047

RESERVED

LCD24

2048

LCD_SEG24[3:0]

…

LCD31

204F

LCD_SEG31[3:0]

LCD32

2050

LCD_SEG32[3:0]

LCD33

2051

LCD_SEG33[3:0]

LCD34

2052

LCD_SEG34[3:0]

LCD35

2053

LCD_SEG35[3:0]

LCD36

2054

LCD_SEG36[3:0]

LCD37

2055

LCD_SEG37[3:0]

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

LCD38

2056

RESERVED

LCD39

2057

RESERVED

LCD40

2058

RESERVED

LCD41

2059

RESERVED

RTM Probes:

RTM0

2060

RTM0[7:0]

RTM1

2061

RTM1[7:0]

RTM2

2062

RTM2[7:0]

RTM3

2063

RTM3[7:0]

Synchronous Serial Interface:

SSI

2070

SSI_EN SSI_10M

SSI_CKGATE

SSI_FSIZE[1:0] SSI_FPOL SSI_RDYEN SSI_RDYPOL

SSI_BEG

2071

SSI_BEG[7:0]

SSI_END

2072

SSI_END[7:0]

Fuse Selection Registers:

TRIMSEL

20FD

TRIMSEL[7:0]

TRIM

20FF

TRIM[7:0]

SFR M AP (SFRs Speci f ic to TERIDIAN 80515) – In N umerical Order

‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and

should not be changed. This table lists only the SFR registers that are not generi c 8051 SFR registers.

Name

SFR

Addr

Bi t 7

Bi t 6

Bi t 5

Bi t 4

Bi t 3

Bi t 2

Bi t 1

Bi t 0

Digital I/O:

DIO_0[7:4] (Po rt 0) RESERVED

DIR0

DIO_DIR0[7:4] 1111

DIO_1[7:6] (Po rt 1) DIO_1[3:0] (Po rt 1)

DIR1

DIO_DIR1[7:6]

DIO_DIR1[3:0]

RESERVED

DIO_2[1:0] (Po rt 2)

DIR2

1111

DIO_DIR2[1:0]

Int errupts and WD Timer:

INTBITS

INT6 INT5 INT4 INT3 INT2 INT1 INT0

WDI

WD_RST

IE_RTC IE_XFER

Flash:

ERASE

94 FLSH_ERASE[7:0]

FLSHCTL

PREBOOT

SECURE

FLSH_MEEN FLSH_PWE

PGADR

FLSH_PGADR[6:0]

Serial EEPROM:

9E EEDATA[7:0]

9F EECTRL[7:0]

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

I/O RAM (Configuration RAM) – Alphabetical Order

Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its para-

meters from the I/O RAM.

Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and

copied to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory

space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all

bits are cleared to zero unless otherwise stated. Generic SFR registers are not listed.

Name Location

[Bit(s)] Dir Description

ADC_DIS 2005[3] R/W D is ables ADC and r emo ves bias current

CE_EN 2000[4] R/W CE enable.

CHOP_EN[1:0] 2002[5:4] R/W Chop enable for the reference band gap circ uit.

00: enabled 01: disabled 10: disabled 11: enabled

RESERVED 2004[5] R/W Must be 0.

CKOUT_DIS 2004[4] R/W CKOUT Disable. When zero, CKTEST is an active output.

RESERVED 2003[4:3] R/W Must be 0.

RESERVED 2003[2:0] R Reserved

DIO_R4[2:0]

DIO_R5[2:0]

DIO_R6[2:0]

DIO_R7[2:0]

DIO_R8[2:0]

DIO_R9[2:0]

DIO_R10[2:0]

DIO_R11[2:0]

200B[2:0]

200B[6:4]

200C[2:0]

200C[6:4]

200D[2:0]

200D[6:4]

200E[2:0]

200E[6:4]

R/W

Connects dedic ated I / O pins 4 t o 11 t o selecta ble inter nal resourc es. I f

more than one input is connected to the same resource, the ‘Multiple’

c ol umn b elow specifies how th ey are c ombin ed. S ee S oft w are U ser ’s

Guide for details).

DIO_GP Resource Multiple

NONE

Reserved

T0 (counter0 clock)

T1 (counter1 clock)

High priority I/O interrupt (int0 rising)

Low priority I/O interrupt (int1 rising)

High priority I/O interrupt (int0 falling)

Low priority I/O interrupt (int1 falling)

DIO_DIR0[7:4] SFR A2 R/W Pr ogr ams the direction of DIO pins 7 through 4. 1 indicates output.

Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW

for special o ption f or DIO 6 and DIO7 outputs. See DIO_EEX for s pecial

option for DIO4 and DIO5.

Note: Bit 0, Bit 1, Bit 2 and Bit 3 must be set to 1.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

DIO_DIR1[7:6]

DIO_DIR1[3:0] SFR91 R/W Progr ams the direction of DIO pins 15, 14 and 11 through 8. 1

indicates output. Ignored if the pin is not configured as I/O.

Not e: Bi t 4 and B i t 5 must be set to 1.

DIO_DIR2[1:0] SFRA1[5:0] R/W Progr ams the direction of DIO pins 17 and 16. 1 indicates output.

Ignored if the pin is not configured as I/O.

Note: Bit 2, Bit 3, Bit 4 and Bit 5 must be set to 1.

DIO_0[7:4]

DIO_1[7:6],

DIO_1[3:0]

DIO_2[1:0]

SFR80

SFR90

SFRA0[1:0]

R/W

Port 0

Port 1

Port 2

The value on the DIO pins. Pins configured as LCD will read

zero. When written, changes data on pins configured as

outputs. Pins configured as LCD or input will ignore writes.

DIO_EEX 2008[4] R/W When set, convert s DIO4 and DIO5 to interf ac e with ext ern al

EEPR OM. D IO 4 becomes S CK an d DIO5 becomes bi-directional SDA.

LCD_NUM must b e less t han 18.

DIO_PV 2008[2] R/W Causes VARPULSE to be output on DIO7, if DIO7 is confi gured as

output. LCD_NUM mus t be les s th an 15.

DIO_PW 2008[3] R/W Causes W PULSE to be output on DI O6, if DIO6 is configured as

output. LCD_NUM must b e les s th an 17.

EEDATA[7:0] SFR 9E R/W Serial EEPROM int erface data

EECTRL[7:0] SFR 9F R/W Serial EEPROM int erface control

ECK_DIS 2005[5] R/W Emula tor clock disable. When one, the emulator clock is di sab led .

This bit is to be used with caution! Inadvertently setting

thi s bit will inhibit access to the part with the ICE

int erface and thus preclude flash erase and programming

operations. If ECK_DIS is set, it should be done at least 1000ms after

power-up t o giv e emulat ors and programming devices enough ti me to

c omplet e an era se operation.

EQU[2:0] 2000[7:5] R/W Specifie s the power equa tion to the CE.

EX_XFR

EX_RTC 2002[0]

2002[1] R/W Interrupt enable bits. These bits enable the XFER_BUSY and the

RTC_1SE C interrupts to the MPU. Note that if either interrupt is to be

enabled, EX6 in the 80515 must also be set.

FIR_LEN 2005[4] R/W The length of the ADC decimation FIR filter.

1: 22 ADC bits/3 CK32 cycles (384 CKFIR cycles),

0: 21 ADC bits/2 CK32 cycles (288 CKFIR cycles)

FLASH66Z 2005[1] R/W Shoul d be s et to 1 to mi ni mize s up ply cur ren t.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

FLSH_ERASE SFR 94 W Flash Era se I nit iate

FLSH_ERASE is used to initiate either the Fl ash M ass Era se cy cle or

the F lash Page E rase cyc le. Specific patt ern s ar e expected for

FLSH_ERASE in or der t o ini ti at e t he approp r iat e Era se cy cle.

(default = 0x00).

0x55 – Initiate Flash Page Era se c ycle. M ust b e pr oceeded by a w ri te

to FLSH_PGADR @ SFR 0xB7.

0xAA – Initiat e Flash M ass E rase cycle. M ust be proceeded by a write

to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must

be enabled.

Any other pattern writt en to FLSH_ERASE will have no effec t .

FLSH_MEEN SFR B2[ 1] W Mass Erase Enable

0 – Mass Erase disabled (default).

1 – Mass Erase enabled.

Must be r e-written for each new Mass Erase cycle.

FLSH_PGADR SFR B7 [7:1] W Flash Page Erase Address

FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be

erased during the Page Erase cycle. (default = 0x00).

Must be r e-written for each new Page Erase cycle.

FLSH_PWE SFR B2[ 0] R/W Progra m Wri te Enab le

0 – MOVX commands refer to XRAM Space, normal operation

(default).

1 – MOVX @DPTR,A moves A to Program Space (flash) @ DPTR.

This bi t is automatically reset after each byte written to flash. Writes to

thi s bit are i nhibited when i nterr upt s ar e enabled.

IE_XFER

IE_RTC SFR E8[0]

SFR E8[1] R/W I nt errupt flags. These flags are part of the WD I SFR register and mo-

nitor the XFER_BUSY interrupt and the RTC_1SEC interrupt. The

fl ags are set by hard war e and m ust be cleared by the i nterr upt handler.

See also WD_RST.

INTBITS SFR F8[6:0] R Interrupt inputs. The MPU may read these bits to see the input to

external interrupts INT0, INT1, up to INT6. These bits do not have any

m emory and are primarily intended for debug use.

LCD_BSTEN 2020[7] R/W Enables the LCD voltage boost circuit.

LCD_CLK[1:0] 2021[1:0] R/W Sets the LCD clock frequency for COM/SEG pins (not t he f ram e rate.

No te: fw = CKFIR/128

00: fw/29, 01: fw/28, 10: fw/27, 11: fw/26

LCD_EN 2021[5] R/W Enables the LCD dis play. When disabled, VLC2, VLC1, and VLC0 are

ground as are the COM and SEG outputs.

LCD_FS[4:0] 2022[4:0] R/W Contr ols the LCD full scale voltage, VLC2:

)

3.07.0(2 FSLCD

VLCDVLC +⋅=

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

LCD_MODE[2:0

] 2021[4:2] R/

W The LCD bias mode.

000 : 4 sta tes, 1/3 bias

001 : 3 sta tes, 1/3 bias

010: 2 stat es, ½ bias

011: 3 stat es, ½ bias

100 : static di splay

LCD_NUM[4:0] 2020[4:0] R/

W Controls the number of dual-purpose LCD/DIO pins to be configured

as LCD. LCD_NUM will be between 0 and 18. The first dual-purpose

pin to b e alloc at ed as LCD is SEG3 7/DI O17. The table b elow l ists

which SEG and DIO functions are selected for each LCD_NUM value.

LCD_NUM SEG DIO

1-4 None DIO4-11, DIO14-17

5 SEG37 DIO4-11, DIO14-16

6 SEG36-37 DIO4-11, DIO14-15

7 SEG35-37 DIO4-11, DIO14

8-10 SEG34-37 DIO4-11

11 SEG34-37, SEG31 DIO4-10

12 SEG34-37, SEG30-31 DIO4-9

13 SEG34-37, SEG29-31 DIO4-8

14 SEG34-37, SEG28-31 DIO4-7

15 SEG34-37, SEG27-31 DIO4-6

16 SEG34-37, SEG26-31 DIO4-5

17 SEG34-37, SEG25-31 DIO4

18 SEG34-37, SEG24-31 None

LCD_SEG0[3:0]-

LCD_SEG19[3:0],

LCD_SEG24[3:0]-

LCD_SEG31[3:0],

LCD_SEG34[3:0]-

LCD_SEG37[3:0],

2030[3:0]

2043[3:0]

2048[3:0]

204f[3:0],

2052[3:0]

2055[3:0]

W LC D Segmen t Data. Each w ord c ont ains i nformation for from 1 to 4

time di visions of ea ch segmen t . I n each word, bi t 0 cor responds to

COM0, o n up t o bit 3 for COM 3.

MPU_DIV[2:0] 2004[2:0] R/

W Th e M PU c lock divider (from CK C E). These bits may be pr ogr ammed

by the MPU without risk of losing control .

000 - CKCE, 001 - CKCE/ 2, …, 111 - CKCE/27

MPU _DIV is 000 on power-up.

MUX_ALT 2005[2] R/

W The MPU asserts this bit when it wishes the MUX to perform ADC

conversions on an alternate set of inputs.

MUX_DIV[1:0] 2002[7:6] R/

W The number of states in the input multiplexer.

00 - 6 states 0 1 - 4 sta tes 1 0 - 3 sta tes 11 - 2 states

MUX_E 2005[0] R/ MUX_SYNC enable. When high, converts SEG7 into a MUX_SYNC

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

output.

OPT_TXDIS 2008[5] R/

W Trist ates t he OPT _TX out put .

PREBOOT SFR

B2[7] R Indicat es t hat th e preb oot seq uen ce i s a ct ive.

PRE_SAMPS[1:0] 2001[7:6] R/

W Together w/ SUM_CYCLES, t his val ue deter mines the num ber of

s amples i n o ne s um cy cle bet ween XF ER inter rup ts for the CE.

Number of sam ples = PRE_SAMPS*SUM_CYCLES.

00-42, 01-50, 10-84, 11-100

RTC_SEC[5:0]

RTC_MINI[5:0]

RTC_HR[4:0]

RTC_DAY[2:0]

RTC_DATE[4:0]

RTC_MO[3:0]

RTC_YR[7:0]

2015

2016

2017

2018

2019

201A

201B

R/W

The RTC interface. These are the ‘year’, ‘month’, ‘day’, ‘hour’,

‘minute’ and ‘second’ parameters for the RTC. The RTC is set by

writi ng t o th ese registers. Year 00 is defin ed as a leap year .

SEC 00 to 59

MIN 00 to 59

HR 00 to 23 (00=Midnight)

DAY 01 to 07 (01=Sunday)

DATE 01 to 31

MO 01 to 12

YR 00 to 256

RTC_DEC_SEC

RTC_INC_SEC 201C[1]

201C[0] W RTC tim e corr ection bits. Only one bit may be pulsed at a time. When

pulsed, causes the RTC time value to be incremented (or

decremented) by an additional second the next time the RTC_SEC

correction is desired, the MPU must wait 2 seconds before pulsing

one of the bits again.

RTM_EN 2002[3] R/W

Real Time Monitor enable. When ‘0’, the RTM output is low. This bit

enables the two wir e version of RTM

RTM0[7:0]

RTM1[7:0]

RTM2[7:0]

RTM3[7:0]

2060

2061

2062

2063

R/W

Four RTM probes. Before each CE code pass, the values of these

registers are serially output on the RTM pin. The RTM registers are

ignored when RTM_EN=0.

SECURE SFR

B2[6] R/W Enables security provisions that prevent

external reading of flash

memory and CE program RAM. This bit is reset on chip reset and

m ay o nly be set. Attempts t o writ e z ero ar e i gnored.

SSI_EN 2070[7] R/W Enables the Synchronous Serial Interf ace (SSI) on SEG3, SEG4, and

SEG 5 p ins. If SSI_RDYEN is set , S EG 6 is en ab l ed al s o. T he pi n s t ak e

on the new functions SCLK, SSDATA, SFR, and SRDY, respecti vely.

When SSI_EN is high and LCD_EN is lo w, t h ese p i ns ar e c o nver ted t o

the SSI function, regardless of LCDEN and LCD_NUM. For proper

LCD operation, SSI_EN mus t not be high w hen LCD_EN is high.

SSI_10M 2070[6] R/W SSI clock speed: 0: 5MHz, 1: 10MHz

SSI_CKGATE 2070[5] R/W SSI gated clock enable. When low , the SCLK is continuous . When

high, the clock is held low when data is not being transfe rred.

SSI_FSIZE[1:0] 2070[4:3] R/W S SI f rame pulse fo r mat:

0: once at beginning of SSI sequence (whole block of data),

1: ever y 8 bits , 2: ever y 16 bits, 3: ev ery 32 bits.

SSI_FPOL 2070[2] R/W SFR pulse polarity: 0: positi ve, 1: negativ e

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

SSI_RDYEN 2070[1] R/W SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is

configured as SRDY. Otherwise, it is an LCD driv er.

SSI_RDYPOL 2070[0] R/W SRDY polarity: 0: positive, 1: negati ve

SSI_BEG[7:0]

SSI_END[7:0] 2071[7:0]

2072[7:0] R/W The beginning and ending address of the transfer region of the CE

data memory. If the SSI is enabled, a block of words starting with

SSI_BEG and ending with SSI_END will be sent. SSI_END must be

lar ger than SSI_BEG. The maxim um number of output words is limited

by the number of SSI clocks in a CE code pass—see FIR_LEN,

MUX_DIV, and SSI_10M.

SUM_CYCLES

[5:0] 2001[5:0] R/W Together w/ PRE_SAMPS, thi s val ue d etermines (for the C E) the

numb er of sam ples in on e sum c ycle betw een XF ER inter ru pt s.

Number of sam ples = PRE_SAMPS*SUM_CYCLES.

TMUX[3:0] 2000[3:0] R/W Sel ects one of 1 6 input s for TMUXOU T.

0 – DGND (analog)

1 – IBIAS (ana log )

2 – PLL_2 .5V (ana log)

3 – VBIAS (analog)

4 – RTM (Real time output fr om CE)

5 – W DTR_EN (Comparator 1 Output AND V1LT3)

6 – reserved

7 – reserved

8 – RXD (f rom Optical interface)

9 – MUX_SYNC (from MUX_CTRL)

A – CK_10M

B – CK_MPU

C – reserved for production test

D – RTCLK

E – CE_BUSY

F – XFER_BUSY

RESERVED 2005[7] R/W Must be zero.

TRIMSEL 20FD W S elect s t he temper at ure tri m fuse t o be r ead with the TRIM register

(TRIMM[2:0]: 4, TRIMBGA: 5, TRIMBGB: 6)

TRIM 20FF R Contains TRIMBGA, TRIMBGB, or TRIMM[2:0] depe nding on the

value written to TRIMSEL. If TRIMBGB = 0 the n the IC is a 6511 else

the IC is a 6511H.

VERSION[7:0] 2006 R The silicon revision number. This data sheet does not apply to

revisions < 000 0100.

VREF_CAL 2004[7] R/W B rin gs VR EF out to th e VREF pin. T his feature is disabl ed when

VREF_DIS=1.

VREF_DIS 2004[3] R/W Disabl es the i nternal volta ge r eference.

WD_RST SFR

E8[7] W Resets the WD timer. The WDT is reset wh en a 1 is written t o this bit.

Onl y b yte oper at ions on t he wh ole WDI r egist er s hould be used.

WD_OVF 2002[2] R/W The WD over fl ow status bit . T his bit is set w hen t he WD ti mer

overflows. It is power ed by the VBAT pin and at boot-up will in d icate if

the part is recovering from a WD overflow or a power fault. This bit

should be cleared by the MPU on boot-up. It is als o a utoma tically

cleared when RESETZ is low.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

CE Program and Environment

CE Program

The CE program is supplied by TERIDIAN as a data image that can be merged with the MPU operational code for meter

applications. Typically, the CE program covers most applications and does not need to be modified. The description in this

s ect ion applies to CE c ode rev ision CE 11B05.

Formats

All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement (-1 = 0xFFFFFFFF). ‘Calibration’

parameters are defined in flash memory (or external EEPROM) and must be copied to CE memory by the MPU before

enabling the CE. ‘Internal’ variables are used in internal CE calculations. ‘Input’ variables allow the MPU to control the

behavior of the CE code. ‘Output’ variables are outputs of the CE cal culati ons. The corresponding MPU address for t he most

signif i cant byte is given by 0x1000 + 4 x CE_address and 0x1003 + 4 x CE_address for the least significant byte.

Constants

Constants used in the CE Data Memory tables are:

 Sampling freque ncy: FS = 32768Hz/13 = 2520.62Hz (MUX_DIV = 1) or 32786/10 = 3276.8Hz (MUX_DIV = 2)

 F0 is the fundamental signal frequency, typic ally 50 or 60Hz.

 IMAX is the ex te rnal rms c ur re nt cor re sponding to 250 mV peak at the inputs IA or IB.

 VMAX is the external rms voltage corresponding to 250mV peak at the input VA.

 NACC, the accumulation count for energy measurements is PRE_SAMPS*SUM_CYCLES. This value resides in

SUM_PRE (C E addr ess 36).

 Accumulation count time for energy measurements is PRE_SAMPS*SUM_CYCLES/FS.

 In_8 is a gain constant of curr ent channel n. Its value is 8 or 1 and is controlled by In_SHUNT.

 X is a g ain const ant of t he pulse generator s. Its val ue is d eterm ined by PULSE_FAST and PULSE_SLOW.

 Voltage LSB = VMAX * 3.3243*10-9 V ( peak).

The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as used by the CE) to

external, i.e. metering quantities. Their values are determined by the scaling of the voltage and current sensors used in an

actual meter. The LSB values used in this document relate digital quantities at the CE or MPU interf ace to external m eter input

quantities. For example, if a SAG threshold of 80V peak is desired at the meter input, the digital value that should be pro-

grammed into SAG_THR would be 80V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the des cr iption of SAG_THR.

The parameters EQU, CE_EN, PRE_SAMPS, and SUM_CYCLES are essential to the function of the CE and are stored in I/O

RA M (see I/O RA M s ectio n).

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Environment

Befor e starti ng the CE using the CE_EN bit, the MPU has to establish the proper environment for the CE by implem enting the

following steps:

• Loading the image for the CE code into CE PRAM.

• Loading the CE data into CE DRAM.

• Establishing the equation to be applied in EQU.

• Establishing the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES.

• Estab lish ing the number of cycles per ADC mux cycle.

The default configurat ion is FIR_LEN = 1 (three cycles per conve rsion) and MUX_DIV = 1 (4 conversions pe r mux cycle). There

must be thirteen CK32 cycles (see System Timing Diagram, Figure 13). This means that the product of the number of cycles

per A DC c onv ers ion and t he n umb er of c onver s io ns p er cy c le must be 12 (all owi ng for on e settlin g cyc le).

Alternatively, the 71M6511 can be operat ed at t en CK32 cycles per ADC mux cycl e (MUX_DIV = 2). CE quantities a r e s ta t ed

in this section for MUX_DIV = 2, if they differ from those associat ed wi th t he defaul t setting.

During operation, the MPU is in charge of controlling the m ultiplexer cycles, for example by inserting an alternate multiplexer

sequence at regular intervals using MUX_ALT. This enables temperature m easurem ent. The polarity of CHOP must be altered

for each sam ple. It must also alternate for each alternate multiplexer reading.

Th e MP U mu st pr o gr am CHOP_EN alternately between 01 and 10 on every CE_BUSY interrupt except for the fir st CE_BUSY

after an XFER_BUSY interrupt. Note that when XFER_BUSY occurs, it will always be at the same time as a CE_BUSY

interrupt.

Operating CE codes with environment parameters deviating from the values specified by Teridian will lead to

unpredictable results.

CE Calcul at ions

The CE performs the precision computations necessary to accurately measure power. These computations include offset

cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag

detecti on, peak detection, and voltage phase m easurem ent. All data computed by the CE is dependent on the selected meter

equation as given by EQU (in I/O RAM). As a function of EQU, the element components V0 through I2 take on different

meanings.

• EQU Watt & VAR Formula

(WSUM/VARSUM) Element In put Mapping

W0SUM/

VAR0SUM W1SUM/

VAR1SUM I0SQSUM I1SQSUM

0 VA IA ( 1 elemen t, 2W 1 φ) VA*IA VA*IB IA IB

1 VA*(IA-IB)/2

(1 e lement, 3W 1φ) VA*(IA-IB)/2 VA*IB IA-IB IB

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

CE RAM Locat ions

CE Fron t End Dat a (Raw Dat a)

Access to the raw data provided by the AFE is possible by reading addresses 0 through 7, as listed below.

Addr es s (HE X) Name Description

Phase A cur ren t

Phase A voltage

Phase B cur ren t

Reserved

TEMP

Temperature

Reserved

CE Status Word

Since the CE_BUSY interrupt occurs at 2520.6Hz (or at 3276.8Hz when MUX_DIV = 2), it is desirable to minimize the

computation required in the interru pt ha ndl er o f the MPU. Th e M P U can r ead CESTATUS at ever y CE_B USY int errupt.

Address Name Description

0x51 CESTATUS See descripti on of CE stat us wor d bel ow

The CE Status Word is useful for generating early warnings to the MPU. I t contains sag warnings for phase A, as well as F0,

the derived clock operating at the fundamental input frequency. CESTATUS provides information about the status of voltage

and input AC signal fr equency, which ar e useful for generating an early power fail warning to i nitiate necessary data st orage.

CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt).

Note: The CE does not store sag alarms from one code pass to the next. CESTATUS is refreshed at every CE_BUSY

interrupt and remains valid f or up to 100µs after the CE_BUSY int errupt occurs. Unsynchronized read operations of

CESTATUS will yiel d unreliable results.

The significance of the bits in CESTATUS is shown in t he tabl e below :

CESTATUS

[bit]

Name

Description

31-29

Not Us ed

These unused bits will always be zero.

F0 is a square wave at the exact fundamental input frequency.

RESERVED

25 SAG_A

Normal ly zero . B ecomes one wh en VA remains belo w SAG_THR for SAG_CNT

s amples. Wil l not retu rn to zero unt i l VA r i ses above SAG_THR.

24-0

Not Us ed

These unused bits will always be zero.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

For generating proper status information, the CE is initialized by the MPU using SAG_THR (default of 80V RMS at the meter

input if VMAX=600V) and SAG_CNT (default 80 samples). Using the default value for SAG_CNT, the peak -to-peak signal has to

be below SAG_THR value f or 32 m illiseconds to act ivat e the SAG_X status bits.

Address Name Default Description

0x31 SAG_THR +56,722,300

(0x361837C)

Meter voltage inputs must be above this threshold to prevent sag alarms.

LSB = VMAX * 3.3243*10-9 V peak.

For ex ample, i f a sag threshold of 80V RMS is desired,

103243.3 280

−

⋅⋅

=VMAX

THRSAG

0x32

80 Number of cons ecut ive volt age sam ples below SAG_THR before a sag alarm

is declared. 80*397µs = 31.8 ms (for MUX_DIV = 1) .

CE T ransfer Variabl es

W hen the MPU receives the XFER_BUSY i nterrupt, it knows that fresh data is available in the transfer variables. CE transfer

variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout

each accumul atio n i nt erval. In t his dat a s heet, t he names of CE t ra nsfer varia bles always end wi th _X.

Fundame ntal Po w er Measur ement V ariable s

The tabl e below describes each transfer variabl e for fundam ental power m easurement. All variables are signed 32 bit integ ers .

Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the

int egration time is 1 second. Additi onally, the hardware will not permit output values to ‘fold back’ upon overflow.

Address Name Description

42 RESERVED

43 W0SUM_X The sum o f Watt sam ples from each wat t met er element (In_8 i s the gain

configured by IA_SHUNT or IB_SHUNT).

LSB = 6.6952*10-13 VMAX I MAX / In_8 Wh (for MUX_DIV = 1)

LSB = 5.1501*10-13 VMAX IMAX / In_8 Wh (for MUX_DIV = 2)

44 W1SUM_X

45 RESERVED

46 RESERVED

47 VAR0SUM_X The sum of V AR samples from ea ch w attmeter el emen t (In_8 is the gain

configured by IA_SHUNT or IB_SHUNT).

LSB = 6.6952*10-13 VMAX I MAX / In_8 Wh (for MUX_DIV = 1)

LSB = 5.1501*10-13 VMAX IMAX / In_8 Wh (for MUX_DIV = 2)

48 VAR1SUM_X

49 RESERVED

WxSUM_X is the W h value accumulated for elem ent ‘X’ in the last accumulation interval and can be com put ed based on t he

specified LSB value.

For ex ample with VMAX = 600V and IMAX = 208A, LSB (for WxSUM_X ) is 0.08356 µWh (MUX_DIV = 1 ) .

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Inst antaneous Power Measurement Variables

The FREQSEL Register selects the input phase used for frequency measurement and for the MAIN_EDGE counter. The

freque ncy measu rement is implemente d using the freque ncy lo ck ed l oop of th e C E for t he select ed pha se.

IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval.

INSQSUM_X can be used for computing the neutral current.

Address Name Description

33 RESERVED

41 FREQ_X

Fundamental frequency.

LSB

10587.

−

⋅≈≡

Hz for MUX_DIV = 1

32 10763.0

−

⋅≈

Hz for MUX_DIV = 2

4A I0SQSUM_X The s um o f squar ed cu r ren t samples fr om ea ch element .

LSB = 6.6952*10-13 IMAX2 / In_82 A2h (for MUX_DIV = 1)

LSB = 5.1501*10-13 IMAX2 / In_82 A2h (for MUX_DIV = 2)

4B I1SQSUM_X

4C RESERVED

4D RESERVED

4E V0SQSUM_X The s um o f squar ed vo l ta ge s amples fr om ea ch el emen t .

LSB= 6.6952*10-13 VMAX2 V2h (for MUX_DIV = 1)

LSB = 5.1501*10-13 VMAX2V2h (for MUX_DIV = 2)

4F RESERVED

50 RESERVED

The RMS values can be computed by the MPU fr om the squared current and voltage samples as per the formulae:

Note: FS = 2520.6Hz (MUX_DIV = 1) or 3276.8Hz (MUX_DIV = 2)

Other Measure men t Para meters

MAINEDGE_X i s us efu l fo r im plem ent i ng a r eal-tim e clock based on the input AC signal. MAINEDGE_X is the number of half-

cycles accounted for in the last accumulated interval for the AC signal of the phase specified in the FREQSEL register.

Address Name Description

52 RESERVED

53 RESERVED

55 MAINEDGE_X Th e numb er of edge cr os sings of the select ed volt age in t he previous

acc umu lat io n interval. Edge cr ossings are either direc ti on and are d e-

bounced.

ACC

RMS

NFLSBVxSQSUM

Vx ⋅⋅⋅

=3600

ACC

RMS NFLSBIxSQSUM

Ix ⋅⋅⋅

=3600

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Temperature Measurement and Temperature Compensation

Input variables: TEMP_NOM is the reference value for temperature measurement, i.e. when this value is set with

TEMP_RAW_X at known tem perature. The 71M6511/6511H measures temperature with reference to this value.

DEGSCALE is th e s lo pe or r ate of temper atu re increase or decrease from the TEMP_NOM for TEMP_X measurement.

PPMC and PPMC2 are t emperature com pensation coeffici ents. Their values should reflect t he characteristics of the band gap

voltage re fe re nce of the chip. PPMC and PPMC2 follow the square law characte ristics to compe nsate for nonl ine ar te mpera ture

behaviors, when the 71M6511/6511H is in internal temperature compensation mode.

Addres

Name Defaul

t Description

0x11 TEMP_NOM 0 Dur ing cal ibra t ion, t he value of TEMP_RAW_X should be placed in

TEMP_NOM.

0x30 DEGSCALE 9585 Scal e factor for TEMP_X.

TEMP_X = -DEGSCALE*2-22*(TEMP_RAW_X-TEMP_NOM).

0x38 EXT_TEMP 0

Should be 15 or 0. W hen 15, causes the CE to ignore internal tem-

perature compensation and permits the MPU to control GAIN_ADJ.

When internal te mpera ture comp ensatio n is select ed, GAIN_ADJ w il l be:











⋅

⋅

++=

116384_ PPMCXTEMPPPMCXTEMP

floorADJGAIN

Defa ult is 0 (int ern al compen sat ion).

0x39 PPMC 0

Linear te mperature com pensation factor. Equals the linear temperature

coef fi cient (PPM/°C) of V REF multiplied by 26.8 4, or TC1 (expr ess ed in

µ V/ °C, see Elect r ical S pecif ications) m ult ipl ied by 22. 46. A posit iv e

value will cause the meter to run faster when hot. The compensation

factor aff ects both V and I and wil l theref ore have a double effect on

products.

0x3A PPMC

2 0

Square-law temperature comp ensatio n fa c tor. Equ als the square-law

temperature coef fi cient (PPM/°C2) of V REF multiplied by 1374, or TC2

(expr essed in µV/ °C2, s ee El ect ri cal Sp ecif icat ions) m ult iplied by

1150.1. A pos itive value w il l cause th e meter to run f ast er w hen hot. The

compensat ion factor aff ects both V and I and will therefor e have a

double eff ect on products.

EXT_TEMP al l o ws t he M PU t o s el ec t b et w een d i r ec t c o nt r ol of GAIN_ADJ or managem ent of GAIN_ADJ by the CE, based on

TEMP_X and the temperature cor rec ti on coefficients PPMC and PPMC2.

Output variables: TEMP_X is the temperature measurement from reference temperature of TEMP_NOM. TEMP_X is

computed using TEMP_RAW_X and DEGSCALE. Thi s qu ant ity is posi ti ve w hen th e temperat ur e i s abov e th e ref erenc e and is

negative for cold tem peratures.

TEMP_RAW_X is the raw processed value from ADC output and is the fundamental quantity for temperature measurement.

TEMP_RAW_X is less than TEMP_NOM at higher temperatures. TEMP_RAW_X is more than TEMP_NOM for cooler

temperatures tha n ref eren ce temp erature.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

GAIN_ADJ is a scaling factor for power measurements based on temperature (when in internal temperature compensation

mode). In general, for higher tem peratures it is lower than 16384 and higher than 16384 for lower tem peratures. GAIN_ADJ is

mainly dependent on the PPMC, PPMC2 and TEMP_X register values. This parameter is automatically computed by the CE

and is used by the CE for temperatur e compensati on.

Address Name Description

0x40 TEMP_X Deviation from Calibration temperat ure. LSB = 0.1 0C.

0x54 TEMP_RAW_X Filtered, u nscaled r eading from temperatur e sensor . This

value should be written to TEMP_NOM during meter

calibration.

0x2E GAIN_ADJ

Scales all voltage and current inputs. 16384 provides

unity gain. Default is 16384. I f EXT_TMP = 0, GAIN_ADJ

is updated by the CE.

Pulse Generation

Input variables: The combination of the PULSE_SLOW and PULSE_FAST parameters control the speed of t he pulse rate. The

default values of 1 and 1 wil l maintai n the original pulse rate given by the Kh equation.

WRATE controls the number of pulses that are generated per measured Wh and VARh quant ities. The lower WRATE it is the

slower is the pulse rate for measured power quantity. The metering constant Kh is derived from WRATE as the amount of

energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the meter of 120V and 30A results in one

pulse per second. If the load is 240V at 150A, ten pulses per second will be generated.

Control is transferred to the MPU for pulse generation if EXT_PULSE > 0. In this case, the pulse rate is determined by

APULSEW and APULSER. The MPU has to load the source for pulse generation in APULSEW and APULSER to generate pulses.

I rr es p ec t i v e o f t h e EXT_PULSE, status the output pulse rate controlled by APULSEW and APULSER is implem ented by t he CE

only. By setting EXT_PULSE > 0, the MPU is pr oviding the source for pulse generati on. If EXT_PULSE is negative, W0SUM_X

and VAR0SUM_X are the default pulse generation sources. In this case, creep cannot be controlled since it is an MPU function.

The maximum pulse rate is FS /2= 1260.3Hz (MUX_DIV = 1).

PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external equipment. When

MUX_DIV = 1, t he mi nimum p ulse wi dth possible is 397µs.

The ma x i mum t ime ji tt er is 397µs (for MUX_DIV = 1) and is independent of t he number of pulses m easured. Thus, if the pulse

gener at or is monitored for 1 second, the peak jitter is 397PPM. After 10 seconds, the peak jitter is 39.7PPM. Th e av era ge jitter

is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its

maximum rate without exhibiting any roll-ove r characte r istics. The ac t ual pulse rate, using WSUM as an examp le, is:

FWSUMWRATEX

RATE

⋅⋅⋅

Wh ere F S = 2520.6Hz (sampli ng frequency for MUX_DIV = 1) or 3276.8Hz (sampling fr equency for MUX_DIV = 2) and X is the

pulse gain factor derived from C E v ariables PULSE_SLOW and PULSE_FAST (see table b elow).

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Address Name Default Description

0x28

PULSE_SLOW

When PULSE_SLOW > 0, the pulse generator input is reduced 64x.

When PULSE_FAST > 0, the pulse generator input is increased 16x.

Thes e two parameters c ont rol th e pul se g ain factor X ( see tabl e below ) .

Allow ed values are either 1 or –1.

X PULSE_SLOW PULSE_FAST

1.5 * 22 = 6 -1 -1

1.5 * 26 = 96 -1 1

1.5 * 2-4 = 0.09375 1 -1

1.5 1 (default) 1 (default)

0x29 PULSE_FAST 1

0x2D WRATE 1556 Kh =

VMAX*IMAX*47.1132 / (In_8*WRATE*NACC*X) Wh/pulse (for MUX_DIV = 1).

VMAX*IMAX*36.2409 / (In_8*WRATE*NACC*X) Wh/pulse (for MUX_DIV = 2).

0x36 SUM_PRE 2520 PRE_SAMPS * SUM_CYCLES. This varia ble i s also called NACC.

0x37 EXT_PULSE 15 Should be 15 or 0. W hen zero, causes the pulse generators to respond to

WSUM_X and VARSUM_X. Oth erwise, the gener at or s res pond t o values the

MPU places in APULSEW and APULSER.

0x3C PULSE_WIDTH 50

The maximum pulse w idth (low-going pulse) is:

(2 * PULSE_WIDTH + 1) * 397µs (for MUX_DIV = 1 )

(2 * PULSE_WIDTH + 1) * 305µs (for MUX_DIV = 2 )

0 is a legitimate value.

0x26 APULSEW 0

W h pulse generator input, to be updated by the MPU when using external pulse

generation (see DIO_PW b it). T he outp ut pu lse rate i s :

APULSEW * FS * 2 -32 * WRATE * 2-14

This input is buffered and can be updated by the MPU during a computation in-

ter val . Th e ch ange wi l l t ake ef fect at the beginnin g of the nex t int erval .

0x27 APULSER 0

VARh pulse generator i nput to be updated by the MPU when using external

pulse gene ration (see DIO_PV bit). The output p ulse rate i s:

APULSER * FS*2-32 * WRATE * 2-14

This input is buffered and can be updated by the MPU during a computation in-

ter val . Th e ch ange wi l l t ake ef fect at the beginnin g of the nex t int erval .

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

TF 0

Current Shunt Variables

Input variables: IA_SHUNT and IB_SHUNT can configure the current inputs to accept shunt resistor sensors. In this case the

CE provides an additional gain of 8 to the current inputs. This will enable the pulse rate to change by 8 times. In order to

maintain a normal pulse rate WRATE may have t o be decreased by 8 times . Whenev er IA_SHUNT or IB_SHUNT are s et to 1 or

a positi ve number, In_8 is assigned a value of 8 in the equation for Kh.

Address Name Default Description

2A IA_SHUNT -1 W hen +1, these variabl es increase the respective current gain by 8. The

gain f actor c ont rol led by In_SHUNT is referred to as In_8 thr oughout this

doc ument. All owed valu es are 1 or –1. F or exam pl e, if IB_SHUNT=-1, IB_8

= 1, if IB_SHUNT = 1, IB_8 = 8.

IA_SHUNT co rresponds to IA_8, IB_SHUNT corresponds to IB_8.

2B IB_SHUNT -1

2C RESERVED

CE Cal ib ratio n Param et ers

The t able belo w list s the paramet ers t hat are t yp i ca l ly ent ered to affect calib ration of meter a cc ura cy.

Address Name Default Description

8 CAL_IA 16384

These constants control the gain of their respective channels. The nominal

v al u e f or ea c h p ar amet er s i s 214 = 16384. The gain of each channel is directly

proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow,

CA L s hould b e sc aled by 1/(1 – 0.01).

9 CAL_VA 16384

A CAL_IB 16384

B RESERVED

C RESERVED

D RESERVED

E PHADJ_A 0 These two constants control the CT phase compensation. No compensation

occurs when PHADJ_X = 0. As PHADJ_X is increased, more compensation

(l ag) i s introduced. Range: ±215 – 1. If it is d esir ed t o dela y the current by the

angle Φ:

Φ⋅−

Φ⋅

=TANcb TANa

XPHADJ

)2cos()21(2)21(1

929

TFa

−−

−−−+=

)2sin()21(

TFb

−

−=

)2cos()21(1 0

9TFc

−

−−=

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Ot her CE Par ameters

The tabl e below shows CE parameters used f or suppression of noise due to scaling and truncati on eff ect s as wel l as sc ali ng

factors.

Address Name Default Description

22 QUANTA

QUANTB 0

Thes e parameters are a dded to t he Wat t ca lculation to compens at e fo r input

noise and truncation.

LSB=(VMAX*IMAX / IA_8) *7.4162*10-10 W for phase A, and

LSB=(VMAX*IMAX / IB_8) *7.4162*10-10 W for phase B

24 QUANT_VARA

QUANT_VARB 0

These parameters are added to the VAR calculation to compensate for input

noise and truncation.

LSB = (VMAX*IMAX / IA_8) * 7.4162 *10-10 W for phase A, and

LSB = (VMAX*IMAX / IB_8) * 7.4162 *10-10 W for phase B

23 QUANT_IA

QUANT_IB 0

These parameters are added to compensate for input noise and truncation in

the squari ng calculations for I2 and V2.

LSB=VMAX2*7.4162*10-10 V2,

LSB= (IMAX2/IA_82)*7.4162*10-10 A2 for phase A and

LSB= (IMAX2/IB_82)*7.4162*10-10 A2 for phase B.

3B KVAR

6448

12880

Scale factor for the VAR calculation. The default value of KVAR should never

need to be changed.

for MUX_DIV = 1

for MUX_DIV = 2

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

TYPICAL PE RFORMANCE DATA

Wh Accuracy at Ro o m Temperature

Figure 24: Wh Accuracy, 0.3A - 200A/240V

VARh Accuracy at Room Temperature

Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Harmon ic Performance

-8

-7

-6

-5

-4

-3

-2

-1

1357911 13 15 17 19 21 23 25

Harmonic

Error [%]

50Hz Harmonic Data 60Hz Har monic Dat a

T est p erform ed at cu r r ent dis t or ti on am plitu d e of 40% and volt ag e dist ort i on am pl it u d e of 10% as per IEC 62 0 53, part 22.

Figure 26: Meter Accuracy over Harmonics at 240V, 30A

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

AP P L ICATIO N IN F OR M ATION

Con ne c t io n of Se ns or s ( CT, Res is t iv e Shunt, Rogowsk i C oil )

Figure 27 and Figure 28 show how resist ive dividers, current transform ers, restive shunts, and Rogowski coil s are connected

to the voltage and current inputs of the 71M6511 .

The analog i nput pins of the 71M6511 are designed for s ens ors with low source im pedance. RC filters with resistance

values higher than those i mple mented in the Teridian Demo Boards should be avoided.

VA = Vin * R

out

/(R

out

+ R

)

out

Figure 27: Resistive Voltage Divider (left), Current Transformer

(right)

Figure 28: Resistive Shunt (left), Rogowski Coil (right)

Distinction betw een 71M6511 and 71M 6511H P art s

71M6511H parts go through a process of trimming and characterization during production that make them suitable to high-

accuracy applications.

The first process applied to the 71M6511H is the trimming of the reference volt age, which is guaranteed to have accuracy over

tem per at ure o f bet ter that ±10PPM/°C.

The second process applied to the 71M6511H is the characterization of the reference voltage over temperature. The

coef fi ci ent s for t he r ef eren ce v ol ta ge a re s to red in so -called trim fuses (I/O RAM r egist ers TRIMBGA, TRIMBGB, TRIMM[2:0].

The MPU program can read these trim fuses and calculate the correction coefficients PPM1 and PPM2 per the formulae given

in t he Performance Specificat ions sec t ion ( V REF, VBIAS). S ee the Temper atur e C omp ens ation sec t ion f or det ails.

The f us e TRIMBGB is non-zero for the 71M6511H part and ze ro for the 71M6511 part.

Trim fuse informat ion is not available for non-H pa r ts. Thus, th e st andar d ar e to be applied. These set tin gs ar e:

• PPMC = TC 1 * 22. 46 = –149

• P PMC2 = TC2 * 1150.1 = –392

Vout = dI

/dt

out

1/N

V3P3

Vout = dI

/dt

out

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Temperature Compensation and Mains Frequency Stabilization for the RTC

The accuracy of the RTC depends on the stability of the external crystal. Crystals vary in terms of initial accuracy as well as in

terms of behavior over temperature. The flexibility provided by the MPU allows for compensation of the RTC using the sub-

strate temperature. To achieve this, the crystal has to be characterized over temperature and the three coefficients Y_CAL,

Y_CALC, and Y_CAL_C2 have to be calculated. Provided the IC substrate temperatures tracks the crystal temperature, the

coefficients can be used in the MPU firmware to trigger occasional corrections of the RTC seconds count, using the

RTC_DEC_SEC or RTC_INC_SEC registers in I/O RAM.

It is not recommended to measure crystal frequency directly due to the error introduced by the measurement probes. A

practical method to measure the crystal frequency (when installed on the PCB with the 71M6511) is t o have a DIO pin t oggle

every second, based on the RTC interrupt, with all other interrupts disabled. When this signal is measured with a precision

timer , the crystal frequency can be obtai ned fr om the measured tim e period t (in µs):

tµs

32768=

Example: Let us assume a crystal characterized by the measurements shown in Table 62. The values show that even at

nominal temperature (the temperature at which the chip was calibrated for energy), the deviation from the ideal crystal

frequency is 11.6 PPM, resulting in about one second inaccuracy per day, i.e. more than some standa rds allow.

Deviation from

Nominal

Temperature [°C]

Measured

Frequency [Hz] Deviation from

Nominal

Frequency [PPM]

+50 32767.98 -0.61

+25 32768.28 8.545

0 32768.38 11.597

-25 32768.08 2.441

-50 32767.58 -12.817

Table 62: Frequenc y over Temperature

As Figure 29 shows, even a constant c ompensation would not bring much improvem ent, since the temperature characteristics

of the crystal are a mix of constant, linear, and quadratic eff ects (in commercially available crystals, the constant and quadratic

eff ect s are dominant).

32767.5

32767.6

32767.7

32767.8

32767.9

32768

32768.1

32768.2

32768.3

32768.4

32768.5

-50 -25 025 50

Figure 29: Crystal Frequency over Temperature

The tem perat ure characteristics of the crystal ar e obtai ned from t he curve in Figure 29 by curve-fitting the PPM deviations. A

fai r ly c lose curv e fi t is achieved with t he coeff ic ients a = 10. 89, b = 0.12 2, a nd c = –0.00714 ( see Figure 30).

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

When applying the inverted coefficients, a curve (see Figure 30) will result that effectively neutralizes the original crystal

characteristics. The frequenc i es were calculated using the fit coeff ici ents as foll ows:











+++⋅=

101010

nom

32767.5

32767.6

32767.7

32767.8

32767.9

32768

32768.1

32768.2

32768.3

32768.4

32768.5

-50 -25 025 50

crystal

cur ve fit

inverse cur ve

Figure 30: Crystal Compensation

Th e MPU Dem o C ode supplied wit h t he TERI DI AN Dem o Kits has a dir ect i nter face for th ese c oef fici ent s and it direc tl y co n-

tr ols the RTC_DEC_SEC or RTC_INC_SEC registers. The Dem o Code uses the coefficients in the following form:

1000 2_

100

)(

CALCY

CALY

ppmCORRECTION ⋅+⋅+=

Note that the coefficients are scaled by 10, 100, and 1000 to provide more resolution. For our example case, the coefficients

would then becom e (after rounding, since the Demo Code accepts only integers):

Y_CAL = 109, Y_CALC = 12, Y_CALC2 = 7

Alternatively, the mains frequency may be used to stabilize or check the function of the RTC. For this purpose, the CE

provides a count of the zero crossings detected for the selected line voltage in the MAIN_EDGE_X address. This count is

equivalent to twi ce the line frequency, and can be used to synchronize and/or correct the RTC.

External Tem perature Compensat ion

In a production electricity meter, the 71M6511 or 71M6511H is not the only component contributing to temperature de-

pendency. In fact, a whol e range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors)

will exhibi t slight or pronounced temperature effects. Since the output of the on-chip temperature sensor is accessible t o t he

MPU, temperature-compensation mechanisms with great flexibility, i.e. beyond the capabilities implemented in the CE, are

possible.

Temperat ure Measuremen t

Temperature measure ment can be implemented with the following steps:

1) At a known temperature TN, re ad the TEMP_RAW register of the CE and writ e the value into TEMP_NOM.

2) Read the TEMP_X r egi s ter at t he kno w n t emp era ture. The obt ai ned value should be <±0.1°C.

3) The temperature T (in °C) at any environm ent can be obtained by reading TEMP_X and applying the following

formula:

10_XTEMP

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Crystal Oscillator

The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these

cr yst al s a nd i s c om patibl e wit h th eir hi g h i m pedanc e a nd l im i ted power handling cap abili ty. The oscillator power dissipation is

very low t o maximize the lifetim e of any battery backup device att ached to VBAT.

Board layouts with minimum capacitance from XIN to XOUT will r equire less battery current. Good layouts will have XIN and

XOU T shield ed from each oth er.

For best rejection of electromagnetic interference, connect the crystal body and the ground terminals of the two

crystal capacitors to GNDD through a ferrite bead. No external resistor should be connected across the crystal,

since the oscillator is self-biasing.

Connecting LCDs

The 71M6511 has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 31 shows the basic

connection for a LCD.

segments

71M6511

LCD

commons

segments

71M6511

LCD

commons

Figure 31: Connecting LCDs

Figure 32 shows how 5V LCDs can be operated even when a 5V supply is not available. Setting the I/O RAM register

LCD_BSTEN to 1 starts the on-chip boost circuitry that will output an AC frequency on the VDRV pin. Using a small coupling

capacitor, two gener al-purpose diodes and a reservoir capacit or, a 5VDC voltage is gener ated which can be fed back int o the

VLCD pin of the 71M6511. The LCD drivers are enabled with the I/O register LCD_ON; I/O register LCD_FS is used to adjust

contrast, and LCD_MODE selects the operation mode (LCD type).

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

LCD_BSTEN

segments

71M6511

5V LCD

commons

VLCD

V3P3

5VDC

VDRV

V3P3

LCD_FS

LCD_EN

LCD_MODE

Contrast

ON/OFF

LCD t ype

LCD_BSTEN

segments

71M6511

5V LCD

commons

VLCD

V3P3

5VDC

VDRV

V3P3

LCD_FS

LCD_EN

LCD_MODE

Contrast

ON/OFF

LCD t ype

Figure 32: LCD Boost Circuit

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Connecting I2C EEPROMs

I 2 C E EP RO Ms or ot h er I 2C com p at i bl e d ev i c es s h o ul d b e c on nec t ed t o th e DI O pins DIO4 and DIO5, as shown in Figure 33.

Pull-up resistors of roughly 3kΩ to V3P3 should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM

must be set to 1 in order to convert the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA.

DIO4

DIO5

71M6511

EEPROM

SCL

SDA

V3P3

3kΩ

DIO4

DIO5

71M6511

EEPROM

SCL

SDA

V3P3

3kΩ

Figure 33: EEPROM Connection

Connect ing 5V Devices

In general, all pins of the 71M6511 are compatible with external 5V devices. The exc epti ons are the power supply pins and the

RX pin of t he UA RT (see s ect ion Electrical Specifications).

71M651X

R1 = 100kΩ

V3P3

Figure 34: Interfacing RX to a 0-5V Signal

Figure 34 shows how a 5V signal from an external device can be safely int erfaced to the RX pin.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Opt ical Interface

The pins OPT_TX and OPT_RX can be used for a regular serial interface, e.g. by connecting a RS_232 transceiver, or they

can be used to directly operate optical components, e.g. an infr ared diode and phototr ansistor implementing a FLAG interface.

Figure 35 shows the basic connections. The OPT_TX pin becom es active when the I/O RAM register OPT_TXDIS is set to 0.

OPT_TX

OPT_RX

71M6511

V3P3

Phototransistor

LED

100kΩ

100pF

V3P3

OPT_TX

OPT_RX

71M6511

V3P3

Phototransistor

LED

100kΩ

100pF

V3P3

Figure 35: C onnec t io n for Opt ical C omp onent s

Connect ing V1 and Reset Pins

A voltage divider should be used to establi sh a safe range for V1 when the meter is i n mission mode (V1 must be lower t han

2.9V in all cases in order to keep the hardware watchdog timer enabled). For proper debugging or loading code into the

71M6511 mounted on a PCB, it is necessary to have a provision like the header shown above R1 in Figure 36. A shorting

jumper on this header pulls V1 up to V3P3, disabling the hardware watchdog timer. C1 helps suppressing ESD.

10kΩ

100pF

10kΩ

100pF

Figure 36: Voltage Divider for V1

Even though a f uncti onal meter will not necessarily need a r eset swit ch, it i s useful to have a reset pushbutt on f or prototyping.

When a circuit is used in an EMI environment, the RESETZ pin should be supported by the external components shown in

Figure 37. R1 should be in the range of 200Ω, R2 should be around 10Ω. The capacit or C1 should be 1nF. R1 and C1 should

be mounted as close as possible to the IC. In cases where the trace from the pushbutton switch to the RESETZ pin poses a

problem, R2 can be re moved.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

RESETZ

71M6511

DGND

V3P3

Pushbutton C

200Ω

1nF

10ΩR

RESETZ

71M6511

DGND

V3P3

Pushbutton C

200Ω

1nF

10Ω

Figure 37: External Components for RESETZ

Fl ash Prog ramming

Operational or test code can be programm ed into the fl ash m emory using either an i n-circuit em ulator or the Flash Download

Board Module (FDBM) available fr om TERIDIAN. The flash programming procedure uses the E_RTS, E_RXTX, and E_TCLK

pins.

MPU Firmware Library

All application-specific MPU functions mentioned above under “Application Information” are available from TERIDIAN as a

standard ANSI C library and as ANSI “ C” source code. The code is avail able as part of the Demonstration Kit for the 71M6511

and 71M6511H ICs. The Demonstration Kits come with the 71M6511 or 71M6511H IC preprogrammed with demo firmware

mounted on a functional sample met er P C B (Demo B oa r d). The Demo Boar ds all ow f or q uic k an d ef f icient evaluation of the I C

without having to wr ite firmware or having to supply an in-cir cuit emula to r (ICE).

A reference guide for firmware development on the 71M6511 and 71M6511H is available as a separate docum en t ( Softwa re

User’s Guide, “SUG”). The User’s Manuals supplied with the Dem o Kits contain MPU address maps for the demo code as well

as other us efu l i nformation, such as sample c alibrat ion proc edures .

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

SPECIFICATIONS

Elect rical Specifications

ABSOLUTE MAXIMUM RATIN GS

Supplies and Ground Pins:

V3P3D, V3P3A −0.5V to 4.6V

| V3P3D - V3 P3A |

0V t o 0.5 V

VLCD -0.5V to 7V

VBAT -0.5V to 4.6V

GNDD -0.5V to +0.5V

Analog Output Pins:

VREF, VBIAS -1mA to 1mA,

-0.5 to V3P3A+0.5V

V2P5 -1mA to 1mA,

-0.5V to 3.0V

Analog Input Pins:

IA, VA, IB -0.5V to V 3P3A+0. 5V

XIN, XOU T -0.5V to 3.0V

RX -0.5V to 3.6V

OPT_RX -1mA to 1mA

-0.5 to V3P3A+0. 5V

Digital Input Pins:

DIO4-11, DIO14-17, E_RXTX, E_RST -0.5 to 6V

TEST, RESETZ -0.5 to V3P3D+0.5V

All Othe r P in s:

Inpu t pins -5mA to 5mA

-0.5V to V3P3D+0.5V

Outp ut pins -30mA to 30mA

-0.5 to V3P3D+0.5V

Temperature:

Operating junction temperature (peak, 100ms) 140 °C

Operating junction temperature (continuo us) 125 °C

St or age t emp era ture −45 °C to 165 °C

Solder te mperature – 10 second duration 250 °C

ESD Stress:

Pins IA, VA, I B, RX, TX, E_RST, E _T CLK, E_RXTX 6kV

All oth er pin s 2kV

Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional

operation at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability. All volt ages are with r espec t to GNDA.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

RECOMMENDED O PERATING CONDITIONS

PARAMETER CONDITION MIN TYP MAX UNIT

3.3V Supply Voltage

(V3P3A, V3P3D) † Normal Operation 3.0 3.3 3.6 V

Battery Backup 0 3.45 V

VLCD 2.9 5.5 V

VBAT No Battery Externally Connec t to V3P3D

Battery Backup 2.0 3.8 V

Operating Tem perature -40 85 ºC

†V3P3A and V3P3D should be shorted together on the circuit board. GNDA and GNDD should also be shorted on the circuit board.

LOGIC LEVELS

PARAMETER CONDITION MIN TYP MAX UNIT

Digi tal high-l evel input v olt age, V IH 2 V3P3D V

Digi tal low-le vel input voltage, VIL −0.3 0.8 V

Digi tal high-level output voltage VOH ILOAD = 1mA V3P3D

–0.4 V3P3D V

ILOAD = 15mA V3P3D-

0.61 V

Digi tal low-level out put v oltage VOL ILOAD = 1mA 0 0.4 V

ILOAD = 15mA 0.8

Input pull-up current, IIL

RESETZ

E_RXTX, E_ RST

Other digital inputs

VIN=0V

-1

100

μA

Input pull down current, IIH

TEST

Other digital inputs

VIN=V3P3D

-1

100

μA

1Guaranteed by design , not subject to test.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

SUPPLY CURRENT

PARAMETER CONDITION MIN TYP MAX UNIT

V3P3A + V3P3D + VLCD current N or mal Operation ,

V3P3A=V3P3D=VLCD=3.3V

CKMPU=614kHz

VBAT=3.6V

No flash memory write

6.4 9.5 mA

V3P3A current 3.7 4.3 mA

V3P3D current 2.5 4.8 mA

VLCD current 0.2 0.4 mA

VBAT current -300 300 nA

V3P3D current

Normal Ope ration,

V3P3A=V3P3D=VLCD=3.3V

VBAT=3. 6V, no flash me mory

write

CKMPU=1,228kHz

CKMPU=2,456kHz

CKMPU=4,912kHz

2.9

3.6

5.1

V3P3A + V3P3D current

Power save/ sleep m ode

V3P3A=V3P3D=VLCD=3.3V,

CE, ADC, E_TCLK, VREF dis-

abled

CKMPU=153.5kHz

CKMPU=38.4kHz

4.9

V3P3D current, Write Flash Norm al Operation as above,

ex cept w rite flash at maximum

rate. 7 mA

VBAT current,

VBAT=3.6V

Battery backup,

≤

25°C

V3P3A=V3P3D=VLCD=0V

fOSC = 32kHz 85°C

2 4 μA

41 121 μA

1Guaranteed by design, not su bject to test.

2.5V VOLTAGE REGULATOR

Unl ess oth erw is e sp ecif ied , l oad = 5mA

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Voltage overhead V3P3-V2P5

Reduce V3P3 until V2P5

drops 200mV

440 mV

PSSR ∆V2P5/∆V3P3

RESETZ=1, iload=0

-3

mV/V

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

VREF, VBIAS

Unl ess oth erw is e sp ecif ied , VREF_DIS=0

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VREF output voltage, VNOM(25)

Ta = 22ºC

1.193

1.195

1.197

VREF chop st ep

VREF output impe dance

VREF_CAL = 1,

LOAD

= 10µA , -10µA

2.5 kΩ

VNOM definitionA

VNOM(T)

= VREF(22) + (T–22) TC1 + (T–22)2TC2

-- If TRIMBGA and TRIMBGB available (6511H) --

VREF temperatur e coef fi cients

TC1 (linear )

TC2 (quadra tic)

TRIMBGA, TRIMBGB, TRIMM[2:0]: See

TRIMSEL, TRIM registers

x(33-0.28y) + 0.33y + 7.9

x(0.02-0.0002y) – 0.46

where x = 0.1TRIMBGB - 0.14(TRIMM[2:0]+0.5),

900

370000_500

7404.4 _−−

=BGATRIM

NOMTEMP

µV/°C

µV/°C2

VREF(T) deviation from VNOM(T)

)40|,22max(| 10)()( 6

−

TVNOM TVNOMTVREF

-10 10 ppm/ºC

-- If TRIMBGA and TRIMBGB not available (6511) --

VREF temperature c oefficients

TC1 (linear )

TC2 (quadra tic)

7.0

-0.341

µV/ºC

µV/°C

VREF(T) deviation from VNOM(T)

)40|,22max(| 10)()( 6

−

TVNOM TVNOMTVREF

Ta = -40 ºC to +85ºC -401 +401 ppm/ºC

VREF aging Ta = 25ºC ±25

ppm/

year

VBIAS output voltage

Ta = 25ºC

Ta = -40 ºC to 85ºC

(-1%)

(-2%)1

1.5

1.51

(+1%)

(+2%)1

VBIAS ou tpu t impe dance

LOAD

= 1mA, -1mA

240

500

1Guaranteed by design, not su bject to test.

A This relationship describes the nominal behav i or of VREF at different t emperatures.

CRYST AL OSCILLATOR

Crystal is disconnecte d. Test load is series 200pF, 100kΩ connected between DGND and XO UT.

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Maximum Output Power to Crystal4

Cry stal c onnected

μW

XIN to XOUT Capacitance

Capacitance to DGND

XIN

XOUT

Watchdog RTC_OK threshold

kHz

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

ADC CONVE RTER, VDD REFERENCED

FIR_LEN=0, VREF_DIS=0, VDDREFZ=0

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Re commende d Inpu t Range

(Vin-V3P3A)

-250 250

peak

Voltage to Current Crosstalk:

)cos(

*10

VcrosstalkVin

Vin

Vcrosstalk ∠−∠

Vin = 200mV peak, 65Hz,

on VA

Vcrosstalk = largest

measurement on IA or IB

-101 101 μV/V

THD (First 10 harmonics)

250mV- peak

20mV- peak

Vin=65Hz,

64kpts FFT, Blackman-

Harris window

-75

-90

Input Impedance

Vin=65Hz

kΩ

Temp erature c oefficient of Input

Impedance

Vin=65Hz 1.7 Ω/°C

LSB size

FIR_LEN

=1 150 nV/LSB

Dig ital Full Scale

2097152

LSB

AD C G ain E r ro r versus

% Pow er S upply V ariation

.3/33100 /357106

APV VnVNout INPK

∆

Vin=200mV peak, 65Hz

V3P3A=3.0v, 3.6V 50 ppm/%

Inp ut Offset (V in-V3P3A)

-10

1Guaranteed by design, not su bject to test.

OPTICAL INTERFACE

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

OPT_TX V

(V3P3D-OPT_TX)

SOURCE

=1mA

0.4

OPT_TX V

SINK

=20mA

0.7

OPT_RX Vin Thresh ol d

(Vin

RISING

+Vin

FALLING

)/2

200 250 300 mV

OPT_RX Vin H yster esis

(Vin

RISING

-Vin

FALLING

)

5 30 mV

OPT_RX input i mpedance

|Vin|≤300mV

MΩ

TEM PERAT URE SE NSOR

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Nomi na l Sens itivity ( Sn)2

=25ºC, T

=75ºC

No minal relationship:

N(T)= Sn*T+Nn

-900

LSB/ºC

Nominal Offset (Nn) 2 400000 LSB

Temperature E rror1

SNTN

TERR ))25()((

)25( −

−−=

TA = -40ºC to +85ºC -31 31 ºC

1 Guaranteed by design, not subject to test.

2This parameter defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that

use t his n ominal r el ations hip as a r efer ence.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

LCD BOOST

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VDRV Frequency

OSC/2

VDRV Si n k Curr ent

Vol=1.5V

1.2

2.75

VD RV S ource Curr ent

Voh=1.5V

1.2

2.6

VLCD Target Voltage

4.5

5.5

VLCD Input Current

VLCD=5.0V, LCD_FS=1F,

LCD_MODE=0,1,2,3

LCD_BSTEN=1

450 μA

LCD DRI V E RS

Appli es t o all COM and S EG pins. Unl ess oth erwise st ated, VL CD= 5. 0V, LCD_FS=1F

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VLC0 Max Voltage (

LCD_FS

=1F) W ith respect t o V LCD -0.2 0 V

VLC0 Min Voltag e (LCD_FS =00)

With resp ect t o VLCD*0. 7

-0.2

0.2

VLC1 Voltage,

1/3 bias

½ bias

With resp ect t o 2* VLC D/3

With resp ect t o VLCD/2

-10

+10

VLC0 Voltage,

1/3 bias

½ bias

With resp ect t o VLCD/3

With resp ect t o VLCD/2

-15

-10

+15

+10

Output Impe dance ∆ILOAD=10µA 30 kΩ

RTC

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Range for date

2000

2255

year

RESETZ

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Reset p ulse width

µs

Reset p ulse f all t ime

µs

1Guaranteed by design, not su bject to test.

COMPARATORS

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Offset Voltage

V1-VBIAS

-20

Hysteres is C urrent

Vin = VBIAS - 100mV

0.8

1.2

μA

Response Time

+100mV o ver drive

μs

WD Di sa ble T hr eshold (V1-V3P3A)

-400

-10

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

RAM AND FLASH MEMORY

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

CE RAM wait states

CKMPU = 4.9MHz

Cycles

CKMPU = 1.25 MHz

Cycles

Flash w r it e cy cles

-40°C to +85°C

20,000

Cycles

Flash dat a retention

85°C

Years

Flash dat a retention

25°C

100

Years

Flash byte writes bet w een pag e or mass

erase operat i ons

2 Cycles

FLA S H MEM OR Y TIMIN G

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Wri te Ti me p er B yte

µs

Page Er ase (5 12 bytes)

Mass Er ase

200

Flash byte writes bet w een page or mas s

erase operat i ons

2 Cycles

EEPROM INT ERFACE

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Wr i te C lock frequency

CKMPU=4.9MHz, Using

interrupts 78 kHz

CKMPU=4.9MHz, “bit -

banging” DIO4/5

150 kHz

Recommen ded External Components

NAME

FROM

FUNCTION

VALUE

UNIT

V3P3A

AGND

Bypass capacitor for 3.3V supply

≥0.1±20%

µF

V3P3D

DGND

Bypass capacitor for 3 .3V supp ly

≥0.1±20%

µF

XTAL XIN XOUT

32.768kHz crystal. Elect rically simil a r to ECS

ECX-3 TA series

32.768 kHz

CXS

XIN

AGND

Load capacitor for crystal (depends on crystal

specs and board parasitics).

22±10%

CXL

XOUT

AGND

22±10%

CBIAS

VBIAS

AGND

Bypass capacitor for VBIAS

≥

1000

20%

CBST1

VDRV

External

Boost charg ing capacitor

20%

C2P5

V2P5

DGND

Bypass capacitor for V2P5

≥0.1±20%

µF

CBST2

VLCD

DGND

Boost bypass capaci tor

≥0.22±20%

µF

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Packaging Informati on

64-Pin LQFP PACKAGE OUT LINE (Bottom View).

NOTE: Controlling di men sio ns are in mm.

11.7

12.3

0.60 Typ.

1.40

1.60

11.7

12.3

0.00

0.20

9.8

10.2

0.50 Typ. 0.14

0.28

PIN No. 1 Indicator

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Pinout (Top View)

TERIDIAN

71M6511-IGT

GNDD

E_RXTX

OPT_TX

TMUXOUT

SEG3/SCLK

VDRV

CKTEST

V3P3D

SEG4/SSDATA

SEG5/SFR

SEG37/DIO17

COM1

COM0

COM2

RESETZ

V2P5

VBAT

SEG31/DIO11

SEG30/DIO10

SEG29/DIO9

SEG28/DIO8

SEG27/DIO7

SEG26/DIO6

SEG25/DIO5

SEG19

SEG24/DIO4

SEG18

SEG17

SEG16

COM3

SEG0

SEG35/DIO15

SEG36/DIO16

SEG6/SRDY

SEG8

SEG1

SEG2

SEG34/DIO14

SEG7/MUX_SYNC

SEG12

SEG10

SEG11

SEG9

SEG15

SEG13

SEG14

E_TCLK

OPT_RX

TEST

GNDA

V3P3A

E_RST

VLCD

XOUT

XIN

GNDA

VBIAS

VREF

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Pin Descri ptions

Power/Ground Pins

Name Pin # Type Description

GNDA 49, 58 P Analog ground: This pin should be connected directly to the ground plane.

GNDD 1 P Di git al ground: This pin should be connected directly to the ground plane.

V3P3A 50 P Analog power supply: A 3.3V power supply should be connected to this pin.

V3P3D 9 P Di git al power s upply: A 3.3V power supply should be connected to this pin.

VBAT 46 P Bat t ery backup power supply. A battery or super-capacitor should be connected between

VBAT and GNDD. If no battery is used, connect VBAT to V3P3D.

V2P5 47 O

Output of the internal 2.5V regulator. A 0.1µF capacitor to GNDA should be connected to this

pin.

VLCD 62 P LCD p ower s uppl y. A DC so urce of 3.3 V to 5.0V s hould b e con nected to thi s pin.

Analog Pins

Name Pin # Type Circuit Description

IA 54 I 6

Line Current Sense Input: This pin is a voltage input to the internal A/D converter.

Typically, it is connected to the output of a current trans forme r or shunt resistor. If

the pin is unused it must be connecte d to V3P3A or tied to the IB pin.

VA 51 I 6

Line Voltage Sense In put: This pin is a voltag e in put to the i nt ernal A/D co nv erter.

Typically, it is connected to the output of a resistor divider. If the pin is unused it

must be tied to V3P3A.

IB 53 I 6

Line Cu r rent S ens e In put: This pin i s a voltage input to the internal A/D convert er.

Typically, it is connected to the output of a current trans forme r or shunt resistor. If

the pin is unused it must be connecte d to V3P3A or tied to the IA pin.

V1 56 I 7

Compara tor Input : Th i s pin is a vol tage input to the internal comparator. The voltage

app l ied t o t he pin i s c omp ared t o an i nternal r eference volt age of 1.5V. If the in put

v oltage is above the r eferen ce, th e compar ator outp ut will be h ig h (1). If th e

comparator output is low, a voltage fault will occur. Se e th e precautions in the

Appli cations Section for terminating this pin.

VREF 55 O 9

Voltage Reference for the ADC. A 0.1µF capacitor to GNDA should be connected to

thi s pin.

VBIAS 52 O 9

This pin outputs the reference vol t age used by the power f ault d etec t ion cir cuit. A

1,000pF capacitor to GND should be connected to this pin.

XIN

XOUT 59

61 I 8

Crystal Inputs: A 32kHz style crystal should be connected across these pins.

Typically, a 20pF capacitor is also connected from each pin to GNDA. It is impo r ta nt

to m i nimize th e ca pacit ance betw een t hese pins. S ee th e cr y st al m anufa cturer

datasheet for details.

VDRV 7 O 4 Voltage boost output.

Pi n ty p es: P = Po wer, O = Output , I = I nput, I/ O = I npu t/Output

The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

Di gital Pins :

Name Pin # Type Circuit Description

COM3,

COM2,

COM1,

COM0

O 5 LCD C ommon O utp uts: T hese 4 pi ns p r ovide th e select signals for the

LCD dis p lay .

SEG19…SEG8,

SEG2…SEG0

See

pinout

O 5 Dedicat ed LCD Segm ent Output pins.

SEG24/DIO4…

SEG31/DIO11,

SEG34/DIO14…

SEG37/DIO17

See

pinout O 3, 4, 5

Multi-use p ins, c onfig ura ble as ei th er L CD SEG dri ver or DIO (D IO 4 =

SCK, DIO5 = SDA when configured as EEPROM interface, WPULSE

= DIO6, VARPULSE = DIO7 when configured as pulse outputs). If

unused, these pins must be confi gured as outputs.

SEG7/

MUX_SYNC 24 O 4, 5

Multi-use-pin LCD Segment Output/ MUX_SYNC is output for

Synchronous serial interface

SEG6/SRDY 23 I/O 2, 5

Multi-use-pin, LCD Segment Outputs/ SRDY input for Synchronous

serial interface. When conf igu red as SRD Y, thi s pin m us t be pulle d

down to GNDD.

SEG5/SFR 11 O 4, 5

Multi-use-pin, LCD Segment Output/ SFR output for Synchronous

serial interface.

SEG4/SDATA 10 O 4, 5

Multi-use-pin, LCD Segment Output/ SDATA output for Synchronous

serial interface.

SEG3/SCLK 6 O 4, 5

Multi-use-pin, LCD Segment Output/ SCLK output for Synchronous

serial interface.

CKTEST

Clock PLL output. Can be enable d and disabled by CKOUT_DIS.

TMUXOUT

Dig it al out put test m ult iplex er. Cont rolled by DMUX[3:0].

OPT_RX 57 I 7

Optical Receive Input: This pin m ay receive a signal from an external

photo-detector used in an IR serial interface. If this pin is u nused it

must be terminated to V3P3D or GNDD.

OPT_TX 3 O 4

Optical LED Tr ansmit Output: This pin is designed to directly drive an

LED for transmitting data in an IR serial interface. Can be tristated with

OPT_TXDIS

to be m ult iplex ed with ot her DIO pins.

RESETZ 48 I 1

This input pin resets the chip into a known state. For normal operation,

thi s pin is s et to 1. To reset the chip, this pin is driven to 0. This pin

has an internal 30μA (nominal) current source pull up. A 0.1µF ca-

pacitor to GNDD should be connecte d to this pin. S ee t he precau-

tions in the Applications Section for termin at ing this p in .

RX 45 I 3

UART i n put. The voltage applied at this input must be below 3. 6V.

If this pin is unused it must be terminated to V3P3D or GNDD.

UART output.

E_RXTX

I/O

1, 4

Emulator ser ial dat a. T his p in h as a n i nternal pul l-up res istor.

E_TCLK

Emulator clo ck.

E_RST 63 I/O 1, 4

Emulator res et. This pin h as a n inter nal pul l-up resistor. See the

precautions in the Applications Section for terminating this pin.

TEST 60 I 7

Enables Produc tion Te st. This pin must be grounded in normal

operation.

Pin types: P = Power, O = Out p ut , I = Inpu t, I/ O = Inpu t/Output

The circuit number denotes the equivalent circuit, as specified on the following page.

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

I/O Equivalent Circuits:

Oscillator Equivalent Circuit

Type 8:

Oscillator I/O

Digital Input Equivalent Circuit

Type 1:

Standard Digital Input or

pin configured as DIO Input

with Internal Pull-Up

GNDD

110K

V3P3D

CMOS

Input

V3P3D

Digital

Input

Digital Input

Type 2:

Pin configured as DIO Input

with Internal Pull-Down

GNDD

110K

GNDD

CMOS

Input

V3P3D

Digital

Input

Digital Input Type 3:

Standard Digital Input or

pin configured as DIO Input

GNDD

CMOS

Input

V3P3D

Digital

Input

CMOS

Output

GNDD

V3P3D

GNDD

V3P3D

Digital Output Equivalent Circuit

Type 4:

Standard Digital Output or

pin configured as DIO Output

Digital

Output

LCD Output Equivalent Circuit

Type 5:

LCD SEG or

pin configured as LCD SEG

LCD

Driver

GNDD

LCD SEG

Output

MUX

GNDA

V3P3A

Analog Input Equivalent Circuit

Typ e 6:

ADC Input

Analog

Input

Comparator Input Equivalent

Circuit Type 7:

Comparator Input

GNDA

V3P3A

Comparator

Input

Oscillator

GNDD

V3P3D

Oscillator

VREF Equivalent Circuit

Type 9:

VREF

from

internal

reference

GNDA

V3P3A

VREF

V2P5 Equi valent Circuit

Type 10:

V2P5

from

internal

reference

GNDD

V3P3D

V2P5

VLCD Equivalent Circuit

Type 11:

VLCD Power

GNDD

LCD

Drivers

VLCD

VBAT Equivalent Circuit

Type 12:

VBAT Power

GNDD

Power

Down

Circuits

VBAT

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

A Maxim In tegrated Produ cts Brand

ORDERING INFORMATION

PART DESCRI P TION ORDERING

NUMBER PACKAGE

MARKING

71M6511

64-pin LQFP, 0.5% accuracy 71M6511-IGT 71M6511-IGT

71M6511

64-pin Le ad-Free LQF P, 0.5% acc ura cy 71M6511-IGT/F 71M6511-IGT

71M6511

64-pin LQFP, 0.5% accuracy, T&R 71M6511-IGTR 71M6511-IGT

71M6511

64-pin Le ad-Free LQF P, 0.5% acc ura cy, T&R 71M6511-IGTR/F 71M6511-IGT

71M6511H

64-pin LQFP, 0.1% accuracy 71M6511H-IGT 71M6511H-IGT

71M6511H

64-pin Le ad-Free LQF P, 0.1% acc ura cy 71M6511H-IGT/F 71M6511H-IGT

71M6511H

64-pin LQFP, 0.1% accuracy, T&R 71M6511H-IGTR 71M6511H-IGT

71M6511H

64-pin Le ad-Free LQF P, 0.1% acc ura cy, T&R 71M6511H-IGTR/F 71M6511H-IGT

71M6511/71M6511H

Single-Phase Energ y Meter IC

DAT A SHEET

NOVEMBER 2010

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent

licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

 201 0 M axim Int eg rat ed Pr oducts Maxim is a r eg is t er ed tr ad em ark of M axi m Integr at ed Prod uc t s .

A Maxim In tegrated Produ cts Brand

REVISION HISTORY

Revision Date Description

2.7 11/10 Added guaranteed by design specifications to the electrical specifications