BQ24157YFFT - Texas Instruments

CVREF

33 nF

CBOOT

PACK–

PACK+

CCSOUT

SCL

SDA

CSOUT

CSIN

PGND

I2C BUS

VAUX

HOST

SCL

SDA

STAT

VREF

STAT

PMID

VBUS

CIN

VBUS

CIN

BOOT

OTG

RSNS

CCSIN

VBAT

1 Fm

4.7 Fm

10 kW

L 1.0 H

CO1

22 Fm

0.1 Fm

1 Fm

bq24157

OTG

10 kW

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

bq24157

SLUSB80E –SEPTEMBER 2012–REVISED JANUARY 2018

bq24157 Fully Integrated Switch-Mode Charger

With USB Compliance and USB-OTG Support

1 Features

1• Power Up System without Battery

• Charge Faster than Linear Chargers

• High-Accuracy Voltage and Current Regulation

– Input Current Regulation Accuracy: ±5% (100

mA and 500 mA)

– Charge Voltage Regulation Accuracy: ±0.5%

(25°C), ±1% (0°C to 125°C)

– Charge Current Regulation Accuracy: ±5%

• Input Voltage Based Dynamic Power

Management (VIN DPM)

• Bad Adaptor Detection and Rejection

• Safety Limit Register for Maximum Charge

Voltage and Current Limiting

• High-Efficiency Mini-USB/AC Battery Charger for

Single-Cell Li-Ion and Li-Polymer Battery Packs

• 20-V Absolute Maximum Input Voltage Rating

• 6.5-V Maximum Operating Input Voltage

• Built-In Input Current Sensing and Limiting

• Integrated Power FETs for Up To 1.55-A Charge

Rate

• Programmable Charge Parameters through I2C™

Compatible Interface (up to 3.4 Mbps):

– Input Current Limit

– VIN DPM Threshold

– Fast-Charge/Termination Current

– Charge Regulation Voltage (3.5 V to 4.44 V)

– Low Charge Current Mode Enable/Disable

– Termination Enable/Disable

• Support up to 1.55A Charge Current using 55 mΩ

Sensing Resistor

• Synchronous Fixed-Frequency PWM Controller

Operating at 3 MHz With 0% to 99.5% Duty Cycle

• Automatic High Impedance Mode for Low Power

Consumption

• Robust Protection

– Reverse Leakage Protection Prevents Battery

Drainage

– Thermal Regulation and Protection

– Input/Output Overvoltage Protection

• Status Output for Charging and Faults

• USB Friendly Boot-Up Sequence

• Automatic Charging

• Boost Mode Operation for USB OTG

– Input Voltage Range (from Battery): 3.2 V to

4.5 V

• 2.1 mm x 2 mm 20-Pin WCSP Package

2 Applications

• Mobile and Smart Phones

• MP3 Players

• Handheld Devices

3 Description

The bq24157 is a compact, flexible, high-efficiency,

USB-friendly switch-mode charge management

device for single-cell Li-ion and Li-polymer batteries

used in a wide range of portable applications. The

charge parameters can be programmed through an

I2C interface. The IC integrates a synchronous PWM

controller, power MOSFETs, input current sensing,

high-accuracy current and voltage regulation, and

charge termination, into a small WCSP package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

bq24157 WCSP (20-Pin) 2.1 mm x 2.0 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application Circuit

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Description (Continued)........................................ 4

6 Device Comparisons ............................................. 4

7 Pin Configuration and Functions......................... 5

8 Specifications......................................................... 6

8.1 Absolute Maximum Ratings ..................................... 6

8.2 ESD Ratings ............................................................ 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 6

8.5 Electrical Characteristics........................................... 7

8.6 Timing Requirements................................................ 9

8.7 Typical Characteristics............................................ 10

9 Detailed Description............................................ 12

9.1 Overview................................................................. 12

9.2 Functional Block Diagrams ..................................... 13

9.3 Operational Flow Chart........................................... 15

9.4 Feature Description................................................. 16

9.5 Device Functional Modes........................................ 18

9.6 Programming .......................................................... 23

9.7 Register Description................................................ 27

10 Application and Implementation........................ 30

10.1 Application Information.......................................... 30

10.2 Typical Performance Curves................................. 34

11 Power Supply Recommendations ..................... 36

11.1 System Load After Sensing Resistor.................... 36

12 Layout................................................................... 38

12.1 Layout Guidelines ................................................. 38

12.2 Layout Example .................................................... 39

13 Device and Documentation Support................. 40

13.1 Documentation Support ....................................... 40

13.2 Receiving Notification of Documentation Updates 40

13.3 Community Resources.......................................... 40

13.4 Trademarks........................................................... 40

13.5 Electrostatic Discharge Caution............................ 40

13.6 Glossary................................................................ 40

14 Mechanical, Packaging, and Orderable

Information........................................................... 40

14.1 Package Summary................................................ 41

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (July 2016) to Revision E Page

• Changed Output voltage (with respect to PGND) - SW MIN value From: –0.7 To: –2 in the Absolute Maximum Ratings... 6

• Deleted graphs "Cycle by Cycle Current Limiting in Charge Mode" and "PWM Charging Waveform" from the Typical

Characteristics...................................................................................................................................................................... 10

• Deleted list item "Default charge current will be 550 mA, if 68-mΩsensing resistor is used, since default LOW_CHG

= 0." following Table 8.......................................................................................................................................................... 28

Changes from Revision B (October 2013) to Revision C Page

• Added ESD Ratings table, Timing Requirements table, Feature Description section, Device Functional Modes,

Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information sections..................................... 1

• Changed Features From: Integrated Power FETs for Up To 1.25-A To: Integrated Power FETs for Up To 1.55-A............. 1

• Changed the ICHARGE(MAX) row of the Device Comparisons table............................................................................................ 4

• Changed capacitor from 10-nF to 33-nF for BOOT pin in the Pin Functions table ............................................................... 5

• Changed Note 1 in the Electrical Characteristics table From: "While in 15-min mode" To: "While in DEFAULT mode"....... 7

• Deleted "t15M, 15 minute safety timer" in the Electrical Characteristics table......................................................................... 7

• Changed Figure 3 "15 Minute Mode" To: "DEFAULT Mode" and "32 S Mode" To" HOST Mode"...................................... 10

• Changed Figure 8 text note From: "32S mode" To: "HOST MODE" .................................................................................. 10

• Changed Figure 14............................................................................................................................................................... 15

• Added Battery Detection at Power Up in DEFAULT Mode ................................................................................................. 18

• Changed section 15-Minute Safety Timer To: DEFAULT Mode ......................................................................................... 18

• Added Figure 26 and Figure 27............................................................................................................................................ 34

• Changed section title From: Design considerations and potential issues: To: Design Requirements and Potential

Issues: .................................................................................................................................................................................. 36

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Changes from Revision A (March 2013) to Revision B Page

• Changed Table 8 Memory location: 05, Bit B5 Function description from "....(default 0)" to ".....(default 1) ....................... 28

Changes from Original (September 2012) to Revision A Page

• Deleted capacitor CO2 from the Typical Application Circuit ................................................................................................... 1

• Deleted capacitor CO2 from Figure 23 ................................................................................................................................. 30

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5 Description (Continued)

The IC charges the battery in three phases: conditioning, constant current and constant voltage. The input

current is automatically limited to the value set by the host. Charge is terminated based on battery voltage and

user-selectable minimum current level. A safety timer with reset control provides a safety backup for I2C

interface. During normal operation, The IC automatically restarts the charge cycle if the battery voltage falls

below an internal threshold and automatically enters sleep mode or high impedance mode when the input supply

is removed. The charge status can be reported to the host using the I2C interface. During the charging process,

the IC monitors its junction temperature (TJ) and reduces the charge current once TJincreases to about 125°C.

To support USB OTG device, bq24157 can provide VBUS (5.05 V) by boosting the battery voltage. The IC is

available in 20-pin WCSP package.

(1) See Application Section for explanation and calculations on using different sense resistors.

6 Device Comparisons

PART NUMBER bq24157

VOVP (V) 6.5

D4 Pin Definition OTG

ICHARGE(MAX) at POR in default mode with R(SNS) = 68 mΩ(55 mΩ) and OTG=High on bq24157(mA) 325 (402)

ICHARGE(MAX) in HOST mode with R(SNS) = 68 mΩ(55 mΩ) and Safety Limit Register increased from default (A)(1) 1.25 (1.55)

Output regulation voltage at POR (V) 3.54

Boost Function Yes

Input Current Limit in Default Mode 100 mA (OTG=LOW);

500 mA (OTG=High)

Battery Detection at Power Up No

I2C Address 6AH

PN1 (bit4 of 03H) 1

PN0 (bit3 of 03H) 0

Safety Timer and WD Timer Disabled

100 ms Power Up Delay No

PMID

PGND

PMID

PGND

PMID

PGND

STAT

SDA

OTG

VBUS

BOOT

SCL

CSIN

VREF

CSOUT

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(Top View)

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7 Pin Configuration and Functions

Pin Layout (20-Bump YFF Package)

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

BOOT A3 I/O Bootstrap capacitor connection for the high-side FET gate driver. Connect a 33-nF ceramic capacitor (voltage rating ≥

10 V) from BOOT pin to SW pin.

CD E2 I Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high impedance to

GND.

CSIN E1 I Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic capacitor

to PGND is required.

CSOUT E4 I Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are

long inductive leads to battery.

OTG D4 I

Boost mode enable control or input current limiting selection pin. When OTG is in active status, the device is forced to

operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR

while in default mode, the OTG pin is used as the input current limiting selection pin. The I2C register is ignored at

startup. When OTG=High, IIN_LIMIT = 500mA and when OTG = Low, IIN_LIMIT = 100mA.

PGND D1, D2, D3 Power ground

PMID B1, B2, B3 I/O Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-μF

capacitor from PMID to PGND.

SCL A4 I I2C interface clock. Connect a 10-kΩpullup resistor to 1.8V rail (VAUX= VCC_HOST)

SDA B4 I/O I2C interface data. Connect a 10-kΩpullup resistor to 1.8V rail (VAUX= VCC_HOST)

STAT C4 O Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs pulse is

sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or

communicate with a host processor.

SW C1, C2, C3 O Internal switch to output inductor connection.

VBUS A1, A2 I/O Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to the

load during boost mode .

VREF E3 O Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on VREF is

not recommended.

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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

(2) Duty cycle for output current should be less than 50% for 10- year life time when output current is above 1.25A.

(3) All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal, if not specified.

Consult Packaging Section of the data sheet for thermal limitations and considerations of packages.

(4) 20 ns duration

8 Specifications

8.1 Absolute Maximum Ratings(1) (2)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Supply voltage (with respect to PGND(3)) VBUS; VPMID ≥VBUS –0.3 V –2 20 V

Input voltage (with respect to PGND(3)) SCL, SDA, OTG, SLRST, CSIN, CSOUT, CD –0.3 7 V

Output voltage (with respect to PGND(3))

PMID, STAT –0.3 20 V

VREF 7 V

BOOT –0.7 20 V

SW –2(4) 20 V

Voltage difference between CSIN and CSOUT inputs (V(CSIN) – V(CSOUT) ) ±7 V

Voltage difference between BOOT and SW inputs (V(BOOT) – V(SW) ) -0.3 7 V

Voltage difference between VBUS and PMID inputs (V(VBUS) – V(PMID) ) –7 0.7 V

Voltage difference between PMID and SW inputs (V(PMID) – V(SW) ) –0.7 20 V

Output sink STAT 10 mA

Output Current (average) SW 1.55(2) A

TAOperating free-air temperature range –30 85 °C

TJJunction temperature –40 125 °C

Tstg Storage temperature range –45 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins(2) ±500

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW pins. A tight

layout minimizes switching noise.

8.3 Recommended Operating Conditions MIN NOM MAX UNIT

VBUS Supply voltage, bq24157 4 6(1) V

TJOperating junction temperature range –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.4 Thermal Information

THERMAL METRIC(1) bq24157 UNIT

YFF (20 Pins)

RθJA Junction-to-ambient thermal resistance 85 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 25 °C/W

RθJB Junction-to-board thermal resistance 55 °C/W

ψJT Junction-to-top characterization parameter 4 °C/W

ψJB Junction-to-board characterization parameter 50 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

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(1) While in DEFAULT mode, if a battery that is charged to a voltage higher than this voltage is inserted, the charger enters Hi-Z mode and

awaits I2C commands.

8.5 Electrical Characteristics

Circuit of Figure 23, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ= –40°C to 125°C, TJ= 25°C for typical

values (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CURRENTS

I(VBUS) VBUS supply current control

VBUS > VBUS(min), PWM switching 10 mA

VBUS > VBUS(min), PWM NOT switching 5

0°C < TJ< 85°C, CD=1 or HZ_MODE=1 15 23 μA

Ilgk Leakage current from battery to VBUS pin 0°C < TJ< 85°C, V(CSOUT) = 4.2 V,

High Impedance mode, VBUS = 0 V 5μA

Battery discharge current in High Impedance

mode, (CSIN, CSOUT, SW pins)

0°C < TJ< 85°C, V(CSOUT) = 4.2 V,

High Impedance mode, V = 0 V, SCL, SDA,

OTG = 0 V or 1.8 V 23 μA

VOLTAGE REGULATION

V(OREG) Output regulation voltage programable range Operating in voltage regulation, programmable 3.5 4.44 V

Voltage regulation accuracy TA= 25°C –0.5% 0.5%

–1% 1%

CURRENT REGULATION (FAST CHARGE)

IO(CHARGE) Output charge current programmable range V(LOWV) ≤V(CSOUT) < V(OREG),

VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG=0,

Programmable 550 1250 mA

Low charge current VLOWV ≤VCSOUT < VOREG, VBUS >VSLP,

RSNS= 68 mΩ, LOW_CHG=1, OTG=High 325 350 mA

Regulation accuracy of the voltage across R(SNS)

(for charge current regulation)

V(IREG) = IO(CHARGE) × R(SNS)

37.4 mV ≤V(IREG)< 44.2mV –3.5% 3.5%

44.2 mV ≤V(IREG) -3% 3%

WEAK BATTERY DETECTION

V(LOWV) Weak battery voltage threshold programmable

range2 (1) Adjustable using I2C control 3.4 3.7 V

Weak battery voltage accuracy –5% 5%

Hysteresis for V(LOWV) Battery voltage falling 100 mV

CD, OTG and SLRST PIN LOGIC LEVEL

VIL Input low threshold level 0.4 V

VIH Input high threshold level 1.3 V

I(bias) Input bias current Voltage on control pin is 5 V 1.0 µA

CHARGE TERMINATION DETECTION

I(TERM) Termination charge current programmable range V(CSOUT) > V(OREG) – V(RCH), VBUS > V(SLP),

R(SNS) = 68 mΩ, Programmable 50 400 mA

Regulation accuracy for termination current

across R(SNS)

V(IREG_TERM) = IO(TERM) × R(SNS)

3.4 mV ≤V(IREG_TERM) ≤6.8 mV –15% 15%

6.8 mV < V(IREG_TERM) ≤17 mV –10% 10%

17 mV < V(IREG_TERM) ≤27.2 mV –5.5% 5.5%

BAD ADAPTOR DETECTION

VIN(min) Input voltage lower limit BAD ADAPTOR DETECTION 3.6 3.8 4 V

Hysteresis for VIN(min) Input voltage rising 100 200 mV

ISHORT Current source to GND During bad adaptor detection 20 30 40 mA

INPUT BASED DYNAMIC POWER MANAGEMENT

VIN_DPM Input Voltage DPM threshold programmable

range 4.2 4.76 V

VIN DPM threshold accuracy –3% 1%

INPUT CURRENT LIMITING

IIN_LIMIT Input current limiting threshold

IIN = 100 mA TJ= 0°C – 125°C 88 93 98 mA

TJ= –40°C –125°C 86 93 98

IIN = 500 mA TJ= 0°C – 125°C 450 475 500 mA

TJ= –40°C –125°C 440 475 500

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Electrical Characteristics (continued)

Circuit of Figure 23, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ= –40°C to 125°C, TJ= 25°C for typical

values (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low.

VREF BIAS REGULATOR

VREF Internal bias regulator voltage VBUS >VIN(min) or V(CSOUT) > VBUS(min),

I(VREF) = 1 mA, C(VREF) = 1 μF2 6.5 V

VREF output short current limit 30 mA

BATTERY RECHARGE THRESHOLD

V(RCH) Recharge threshold voltage Below V(OREG) 100 120 150 mV

STAT OUTPUTS

VOL(STAT) Low-level output saturation voltage, STAT pin IO= 10 mA, sink current 0.55 V

High-level leakage current for STAT Voltage on STAT pin is 5 V 1 μA

I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS

VOL Output low threshold level IO= 10 mA, sink current 0.4 V

VIL Input low threshold level V(pull-up) = 1.8 V, SDA and SCL 0.4 V

VIH Input high threshold level V(pull-up) = 1.8 V, SDA and SCL 1.2 V

I(BIAS) Input bias current V(pull-up) = 1.8 V, SDA and SCL 1 μA

f(SCL) SCL clock frequency 3.4 MHz

BATTERY DETECTION

I(DETECT) Battery detection current before charge done

(sink current) (2) Begins after termination detected,

V(CSOUT) ≤V(BATREG) –0.5 mA

SLEEP COMPARATOR

V(SLP) Sleep-mode entry threshold,

VBUS – VCSOUT 2.3 V ≤V(CSOUT) ≤V(BATREG), VBUS falling 0 40 100 mV

V(SLP_EXIT) Sleep-mode exit hysteresis 2.3 V ≤V(CSOUT) ≤V(BATREG) 140 200 260 mV

UNDERVOLTAGE LOCKOUT (UVLO)

UVLO IC active threshold voltage VBUS rising - Exits UVLO 3.05 3.3 3.55 V

UVLO(HYS) IC active hysteresis VBUS falling below UVLO - Enters UVLO 120 150 mV

PWM

Voltage from BOOT pin to SW pin During charge or boost operation 6.5 V

Internal top reverse blocking MOSFET on-

resistance IIN(LIMIT) = 500 mA, Measured from VBUS to PMID 180 250

mΩ

Internal top N-channel Switching MOSFET on-

resistance Measured from PMID to SW,

VBOOT – VSW= 4V 120 250

Internal bottom N-channel MOSFET on-

resistance Measured from SW to PGND 110 210

f(OSC) Oscillator frequency 3.0 MHz

Frequency accuracy –10% 10%

D(MAX) Maximum duty cycle 99.5%

D(MIN) Minimum duty cycle 0

Synchronous mode to non-synchronous mode

transition current threshold(2) Low-side MOSFET cycle-by-cycle current sensing 100 mA

CHARGE MODE PROTECTION

VOVP_IN_USB Input VBUS OVP threshold voltage VBUS threshold to turn off converter during charge 6.3 6.5 6.7 V

VOVP Output OVP threshold voltage V(CSOUT) threshold over V(OREG) to turn off charger

during charge 110 117 121 %V OREG

V(OVP) hysteresis Lower limit for V(CSOUT) falling from above V(OVP) 11

ILIMIT Cycle-by-cycle current limit for charge Charge mode operation 1.8 2.4 3.0 A

VSHORT Trickle to fast charge threshold V(CSOUT) rising 2.0 2.1 2.2 V

VSHORT hysteresis V(CSOUT) falling below VSHORT 100 mV

ISHORT Trickle charge charging current V(CSOUT) ≤VSHORT) 20 30 40 mA

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Electrical Characteristics (continued)

Circuit of Figure 23, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ= –40°C to 125°C, TJ= 25°C for typical

values (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0)

VBUS_B Boost output voltage (to VBUS pin) 2.5V < V(CSOUT) < 4.5 V 5.05 V

Boost output voltage accuracy Including line and load regulation –3% 3%

IBO Maximum output current for boost VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V,

TJ= 0°C – 125°C 200 mA

IBLIMIT Cycle by cycle current limit for boost VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V 1.0 A

VBUSOVP

Overvoltage protection threshold for boost (VBUS

pin) Threshold over VBUS to turn off converter during

boost 5.8 6.0 6.2 V

VBUSOVP hysteresis VBUS falling from above VBUSOVP 162 mV

VBATMAX Maximum battery voltage for boost (CSOUT pin) V(CSOUT) rising edge during boost 4.75 4.9 5.05 V

VBATMAX hysteresis V(CSOUT) falling from above VBATMAX 200 mV

VBATMIN Minimum battery voltage for boost (CSOUT pin) During boosting 2.5 V

Before boost starts 2.9 3.05 V

Boost output resistance at high-impedance mode

(From VBUS to PGND) CD = 1 or HZ_MODE = 1 217 kΩ

PROTECTION

TSHTDWN) Thermal trip 165

°CThermal hysteresis 10

TCF Thermal regulation threshold Charge current begins to reduce 120

8.6 Timing Requirements MIN NOM MAX UNIT

WEAK BATTERY DETECTION

Deglitch time for weak battery

threshold Rising voltage, 2-mV over drive,

tRISE = 100 ns 30 ms

CHARGE TERMINATION DETECTION

Deglitch time for charge termination Both rising and falling, 2-mV

overdrive,

tRISE, tFALL = 100 ns 30 ms

BAD ADAPTOR DETECTION

Deglitch time for VBUS rising above

VIN(min) Rising voltage, 2-mV overdrive, tRISE

= 100 ns 30 ms

tINT Detection Interval Input power source detection 2 s

BATTERY RECHARGE THRESHOLD

Deglitch time V(CSOUT) decreasing below

threshold,

tFALL = 100 ns, 10-mV overdrive 130 ms

BATTERY DETECTION

tDETECT Battery detection time 262 ms

SLEEP COMPARATOR

Deglitch time for VBUS rising above

V(SLP) + V(SLP_EXIT) Rising voltage, 2-mV overdrive,

tRISE = 100 ns 30 ms

UNDERVOLTAGE LOCKOUT (UVLO)

Power up delay 140 ms

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

ChargeCurrent- A

Vbat=3.6V

Vbat=4.2V

Vbat=3V

Efficiency-%

VBUS

2V/div

VSW

5V/div

0.2 A/div

BUS

5mS/div

VPMID

200mV/div,

5.02VOffset

VBUS

1V/div

IBUS

0.2 A/div

0.5mS/div

0.1 A/div

BAT

OTG

2 V/div

Write Command

DEFAULT Mode HOST Mode

1 S/div

500mS/div

VSW

5V/div

200mA/div

BAT

VBUS

2 V/div

VSW

2 V/div

20 mA/div

BUS

10 ms/div

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8.7 Typical Characteristics

Using circuit shown in Figure 23, TA= 25°C, unless otherwise specified.

VBUS = 5 V at 8 mA, VBAT = 3.2V, Iin_limit = 100 mA,

ICHG = 550 mA

Figure 1. Poor Source Detection

Vin = 5 V, VBAT = 3. 2V, No Input Current Limit,

ICHG = 1550mA

Figure 2. Charge Current Ramp Up

VBUS = 5 V, VBAT = 3.1V, Iin_limit = 100/500mA (OTG Control,

DEFAULT Mode), Iin_limit = 100 mA (I2C Control, HOST Mode)

Figure 3. Input Current Control

VBUS = 5 V at 500 mA, VBAT = 3.5V, ICHG = 1550 mA,

VIN_DPM = 4.52 V

Figure 4. VIN Based DPM

Figure 5. Charger Efficiency

VBUS = 5.05 V VBAT = 3.5 V

RLOAD (at VBUS) = 1 kΩto 0.5 Ω

Figure 6. VBUS Overload Waveforms (BOOST Mode)

0 50 100 150 200

Load Current at VBUS (mA)

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

5.09

VBUS

VBAT = 2.7 V

VBAT = 3.6 V

VBAT = 4.2 V

0 50 100 150 200

Efficiency (%)

Load Current at VBUS (mA)

VBAT = 2.7 V

VBAT = 3.6 V

VBAT = 4.2 V

5.02

5.03

5.04

5.05

5.06

5.07

5.08

5.09

VBUS - V

5.01

2.8 3 3.2 3.4 3.6 3.8 44.22.6

VBAT - V

IBUS = 50 mA

IBUS = 100 mA

IBUS = 200 mA

VBUS

100mV/div,

5.05VOffset

VSW

5V/div

0.1 A/div

BAT

100 S/divm

VBAT

0.2V/div,

3.5VOffset

VBUS

0.5V/div,

4.5VOffset

0.5 A/div

OTG

2V/div

10mS/div

VSW

5V/div

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Typical Characteristics (continued)

VBUS = 5.05 V VBAT = 3.5 V IBUS = 217 mA

Figure 7. Load Step Down Response (BOOST Mode)

VBUS = 4.5 V (Charge Mode)/5.1 V (Boost Mode), VBAT = 3.5V,

IIN_LIM = 500 mA, (HOST Mode)

Figure 8. BOOST to Charge Mode Transition (OTG Control)

Figure 9. BOOST Efficiency Figure 10. Line Regulation for BOOST

Figure 11. Load Regulation for BOOST

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9 Detailed Description

9.1 Overview

For a current restricted power source, such as a USB host or hub, a high efficiency converter is critical to fully

use the input power capacity for quickly charging the battery. Due to the high efficiency for a wide range of input

voltages and battery voltages, the switch mode charger is a good choice for high speed charging with less power

loss and better thermal management than a linear charger.

The bq24157 are highly integrated synchronous switch-mode chargers, featuring integrated FETs and small

external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or Li-

polymer battery pack. Furthermore, bq24157 also has bi-directional operation to achieve boost function for USB

OTG support.

The bq24157 have three operation modes: charge mode, boost mode, and high impedance mode. In charge

mode, the IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost

mode, the IC boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode,

the IC stops charging or boosting and operates in a mode with very low current from VBUS or battery, to

effectively reduce the power consumption when the portable device is in standby mode. Through I2C

communication with a host, referred to as "HOST" control/mode, the IC achieves smooth transition among the

different operation modes. Even when no I2C communication is available, the IC starts in default mode. During

default mode operation, the charger will still charge the battery but using each register's default values.

bq24157

CHARGE CONTROL

TIMER and DISPLAY

LOGIC

*Sleep

CSOUT

CSIN

STAT

PGND

PGND SCL

NMOS NMOS

NMOS

PMID

SDA

( I 2 C Control )

Decoder

DAC

Q2 Q 3

VREF

PMID

Q 1

BOOT

REFERNCES

& BIAS

PMID

VBUS SW

VPMID

PGND

VBUS

VPMID

OTG (bq 24153 /8)

ISHORT

VREF

LINEAR _CHG

TCF

IOCHARGE

VOREG

VREF

Charge

Pump

VREF 1

IIN _ LIMIT

OSC

VOVP_IN

VBUS

VUVLO

VBUS

VIN(MIN)

VBUS

TSHTDWN

CBC

Current

Limiting

PWM

Controller

ILIMIT

VBAT

VBUS

VOUT

V CSIN

*Battery OVP

VOUT

VOVP

VBUS UVLO

Poor Input

Source

VBUS OVP

Thermal

Shutdown

*Recharge+

VOUT

VOREG - VRCH

*Signal Deglitched

VCSIN

ITERM *

Termination

PWM _ CHG

*PWM Charge

Mode

VBAT

SHORT

VIN _ DPM

SLRST(bq24156)

VOUT

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9.2 Functional Block Diagrams

Figure 12. Function Block Diagram of bq2415x in Charge Mode

bq24157

CHARGE CONTROL,

TIMER and DISPLAY

LOGIC

*Low Battery

CSOUT

CSIN

STAT

PGND

SCL

NMOS NMOS

NMOS

PMID

SDA

(I2 C Control)

Decoder

DAC

VREF

PMID

BOOT

REFERNCES

& BIAS

PMID

VBUS SW

VPMID

PGND

VBUS

VPMID

OTG

VBUS_B VREF

Charge

Pump

VREF 1

IBO

OSC

VBUSOVP

VBUS

TSHTDWN

CBC

Current

Limiting

PWM

Controller

IBLIMIT

VBAT

VBATMIN

VOUT

*Battery OVP

VOUT

VBATMAX

VBUS OVP

Thermal

Shutdown

*Signal Deglitched

PWM _BOOST

-75 mA

PFM Mode

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Functional Block Diagrams (continued)

Figure 13. Function Block Diagram of bq2415x in Boost Mode

VCSOPUT <V SHORT ? Yes

Enable I SHORT

Indicate Charge- In -

Progress

Regulate

Input Current , Charge

Current or Voltage

High Impedance Mode or Host

Controlled Operation Mode

Termination Enabled

ITERM detected

and V

CSOUT >V OREG -V RCH

VCSOUT < V OREG -

VRCH ?

CSOUT < V SHORT ?

Yes

Indicate Short

Circuit condition

Yes

Indicate DONE

Charge Complete

VBUS < V IN ( MIN ) ?

Yes

Indicate Power

not Good

Disable Charge

Wait Mode

Delay TINT

VBUS < V IN ( MIN ) ?

Yes

VCSOUT < VOREG -

VRCH ?

Enable I DETECT for

tDETECT

Turn Off Charge

Reset Charge

Parameters

Battery Removed

Wait Mode

Delay TINT

Yes

VCSOUT < V LOWV

Power Up

VBUS > V UVLO

Yes

Any Charge State/CE = HIGH

Charge Configure

Mode

Disable Charge

/CE = LOW

POR

Load I2C Registers

with Default Value

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9.3 Operational Flow Chart

Figure 14. Operational Flow Chart of bq2415x in Charge Mode

AdaptorDetectionControl

VBUS

START

Adpator

VBUS

GND

PGND

ISHORT

(30mA)

Deglitch

30ms

VIN(MIN)

VIN_GOOD

VIN_POOR

Delay

TINT

VIN

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9.4 Feature Description

9.4.1 Input Voltage Protection

9.4.1.1 Input Overvoltage Protection

The IC provides a built-in input overvoltage protection to protect the device and other components against

damage if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition is

detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT

pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge process

resumes.

9.4.1.2 Bad Adaptor Detection/Rejection

Although not shown in Figure 14, at power-on-reset (POR) of VBUS, the IC performs the bad adaptor detection

by applying a current sink to VBUS. If the VBUS is higher than VIN(MIN) for 30ms, the adaptor is good and the

charge process begins. Otherwise, if the VBUS drops below VIN(MIN), a bad adaptor is detected. Then, the IC

disables the current sink, sends a send fault pulse in FAULT pin and sets the bad adaptor flag (B2 - B0 = 011 for

Figure 16.

Figure 15. Bad Adaptor Detection Circuit

Charge Command

(HostControlorVBUS

RampsUp)

Bad AdaptorDetected

PulsingSTAT Pin

SetBad AdaptorFlag

VBUS>VIN(MIN)?

Yes

Enable AdaptorDetection

Start 30ms Timer

EnableInputCurrentSink

(30mA, toGND)

30ms Timer

Expired?

Yes

Delay TINT

(2 Seconds)

Good AdaptorDetected

Disable AdaptorDetection

ChargeStart

EnableVIN BasedDPM

Delay 10mS

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Feature Description (continued)

Figure 16. Bad Adaptor Detection Scheme Flow Chart

9.4.1.3 Sleep Mode

The IC enters the low-power sleep mode if the VBUS pin voltage falls below the sleep-mode entry threshold,

VCSOUT+VSLP, and VBUS is higher than the bad adaptor detection threshold, VIN(MIN). This feature prevents

draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch Q1 and

PWM are turned off.

9.4.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)

During the charging process, if the input power source is not able to support the programmed or default charging

current, the VBUS voltage will decrease. Once the VBUS drops to VIN_DPM (default 4.52V), the charge current

begins to taper down to prevent any further drop of VBUS. When the IC enters this mode, the charge current is

lower than the set value and the special charger bit is set (B4 in Register 05H). This feature makes the IC

compatible with adapters having different current capabilities.

9.4.2 Battery Protection

9.4.2.1 Output Overvoltage Protection

The IC provides a built-in overvoltage protection to protect the device and other components against damage if

the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is

detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT

pin. Once V(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and charge process

resumes.

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Feature Description (continued)

9.4.2.2 Battery Detection at Power Up in DEFAULT Mode

bq24157 also has a unique battery detection scheme during the start up of the charger. At VBUS power up,

bq24157 starts a 262-ms timer when exiting from short circuit mode to PWM charge mode. If the battery voltage

is charged above the recharge threshold (VOREG-VRCH) when the 262-ms timer expired, bq2157 will not consider

the battery present; then stop charging, and go to high impedance mode immediately. However, if the battery

voltage is still below the recharge threshold when the 262-ms timer expires, the charging process will continue as

normal battery charging process.

9.4.2.3 Battery Short Protection

During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the

charger operates in short circuit mode with a lower charge rate of ISHORT.

9.4.2.4 Battery Detection in Host Mode

For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably

detect insertion or removal of battery packs.

During the normal charging process with host control, once the voltage at the CSOUT pin is above the battery

recharge threshold, VOREG - VRCH, and the termination charge current is detected, the IC turns off the PWM

charge and enables a discharge current, IDETECT, for a period of tDETECT, (262 ms typical) then checks the battery

voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery is present. On the

other hand, if the battery voltage is below the battery recharge threshold, the battery is absent. Under this

condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes

after a delay of TINT. This function ensures that the charge parameters are reset whenever the battery is

replaced.

9.4.3 DEFAULT Mode

The bq24157 stays in default mode indefinitely until I2C communication begins.

9.4.4 USB Friendly Power Up

The default control bits set the charging current and regulation voltage low as a safety feature to avoid violating

USB spec and over-charging any of the Li-Ion chemistries, while the host has lost communication. The input

current limiting is described below.

9.4.5 Input Current Limiting At Power Up

The input current sensing circuit and control loop are integrated into the IC. When operating in default mode, the

OTG pin logic level sets the input current limit to 100mA for a logic low and 500mA for a logic high. In host mode,

the input current limit is set by the programmed control bits in register 01H.

9.5 Device Functional Modes

9.5.1 Charge Mode Operation

9.5.1.1 Charge Profile

Once a good battery with voltage below the recharge threshold has been inserted and a good adapter is

attached, the bq24157 enters charge mode. In charge mode, the IC has five control loops to regulate input

voltage, input current, charge current, charge voltage and device junction temperature. During the charging

process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion

or Li-polymer charging system for single-cell applications. Figure 17 (a) indicates a typical charge profile without

input current regulation loop. It is the traditional CC/CV charge curve, while Figure 17(b) shows a typical charge

profile when input current limiting loop is dominant during the constant current mode. In this case, the charge

current is higher than the input current so the charge process is faster than the linear chargers. The input voltage

threshold for DPM loop, input current limits, charge current, termination current, and charge voltage are all

programmable using I2C interface.

Precharge

(LinearCharge)

FastCharge

(PWMCharge)

ISHORT

Termination

VSHORT

Regulation

Current

Regulation

Voltage

Precharge

Phase

CurrentRegulation

Phase

VoltageRegulation

Phase

ChargeCurrent

ChargeVoltage

Precharge

(LinearCharge)

FastCharge

(PWMCharge)

ISHORT

Termination

VSHORT

Regulation

voltage

Precharge

Phase

CurrentRegulation

Phase

VoltageRegulation

Phase

ChargeCurrent

ChargeVoltage

(a)

(b)

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Device Functional Modes (continued)

Figure 17. Typical Charging Profile for (a) without Input Current Limit, and (b) with Input Current Limit

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Device Functional Modes (continued)

9.5.2 PWM Controller in Charge Mode

The IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate charge current or

voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation

network used for both continuous and discontinuous current conduction operation. The voltage and current loops

are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable

operation, allowing the use of small ceramic capacitors with a low ESR. The device operates between 0% to

99.5% duty cycles.

The IC has back to back common-drain N-channel FETs at the high side and one N-channel FET at low side.

The input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET

(Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap

circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2.

Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4-

A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM Controller will operate in

synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel

FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used

when the current of the low-side FET is greater than 100mA to minimize power losses.

9.5.3 Battery Charging Process

At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit

current, I(SHORT), to the battery. When the battery voltage is above VSHORT and below VOREG, the charge current

ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT.

The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient.

Both the input current limit, IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. Once the battery

voltage reaches the regulation voltage, VOREG, the charge current is tapered down as shown in Figure 17. The

voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins.

In HOST mode, the regulation voltage is adjustable (3.5V to 4.44V) and is programmed through I2C interface. In

15-minute mode, the regulation voltage is fixed at 3.54V.

The IC monitors the charging current during the voltage regulation phase. If termination is enabled, during the

normal charging process with HOST control, once the voltage at the CSOUT pin is above the battery recharge

threshold, VOREG - VRCH for the 32-ms (typical) deglitch period, and the termination charge current ITERM is

detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT (262-

ms typical), then checks the battery voltage. If the battery voltage is still above the recharge threshold after

tDETECT, the battery charging is complete. The battery detection routine is used to ensure termination did not

occur because the battery was removed. After 40ms (typical) for synchronization purposes of the EOC state and

the counter, the status bit and pin are updated to indicate charging has completed. The termination current level

is programmable. To disable the charge current termination, the host can set the charge termination bit (I_Term)

of charge control register to 0, refer to I2C section for detail.

A new charge cycle is initiated when one of the following conditions is detected:

• The battery voltage falls below the V(OREG) – V(RCH) threshold.

• VBUS Power-on reset (POR), if battery voltage is below the V(LOWV) threshold.

• CE bit toggle or RESET bit is set (Host controlled)

9.5.4 Thermal Regulation and Protection

To prevent overheating of the chip during the charging process, the IC monitors the junction temperature, TJ, of

the die and begins to taper down the charge current once TJreaches the thermal regulation threshold, TCF. The

charge current is reduced to zero when the junction temperature increases approximately 10°C above TCF. In

any state, if TJexceeds TSHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and

all timers are frozen. Charging resumes when TJfalls below TSHTDWN by approximately 10°C.

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Device Functional Modes (continued)

9.5.5 Charge Status Output, STAT Pin

The STAT pin is used to indicate operation conditions. STAT is pulled low during charging when EN_STAT bit in

control register (00H) is set to “1”. Under other conditions, STAT pin behaves as a high impedance (open-drain)

output. Under fault conditions, a 128-µs pulse will be sent out to notify the host. The status of STAT pin at

different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED or

communicate to the host processor.

Table 1. STAT Pin Summary

CHARGE STATE STAT

Charge in progress and EN_STAT=1 Low

Other normal conditions Open-drain

Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source,

VBUS UVLO, no battery, thermal shutdown 128-μs pulse, then open-drain

Boost mode faults: Timer fault, over load, VBUS or battery overvoltage, low battery voltage, thermal

shutdown 128-μs pulse, then open-drain

9.5.6 Control Bits in Charge Mode

9.5.6.1 CE Bit (Charge Mode)

The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit

enables the charge and a high logic level (1) disables the charge.

9.5.6.2 RESET Bit

The RESET bit in the control register is used to reset all the charge parameters. Writing ‘1” to the RESET bit will

reset all the charge parameters to default values except the safety limit register, and RESET bit is automatically

cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge

starts and it is not recommended to set the RESET bit while charging or boosting are in progress.

9.5.6.3 OPA_Mode Bit

OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if

HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in

boost mode.

Table 2. Operation Mode Summary

OPA_MODE HZ_MODE OPERATION MODE

0 0 Charge (no fault)

Charge configure (fault, Vbus > UVLO)

High impedance (Vbus < UVLO)

1 0 Boost (no faults)

Any fault go to charge configure mode

X 1 High impedance

9.5.7 Control Pins in Charge Mode

9.5.7.1 CD Pin (Charge Disable)

The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD

pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode.

9.5.8 BOOST Mode Operation

In host mode, when OTG pin is high (and OTG_EN bit is high thereby enabling OTG functionality) or the

operation mode bit (OPA_MODE) is set to 1, the device operates in boost mode and delivers the power to VBUS

from the battery. In normal boost mode converts the battery voltage to VBUS-B (about 5.05V) and delivers a

current as much as IBO (about 200mA) to support other USB OTG devices connected to the USB connector.

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9.5.8.1 PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3 MHz frequency voltage-

mode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally

compensated using a Type-III compensation scheme that provides enough phase margin for stable operation

with a wide load range and battery voltage range.

In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle

current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is

set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses.

9.5.8.2 Boost Start Up

To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start

up.

9.5.8.3 PFM Mode at Light Load

In boost mode, under light load conditions, the IC operates in pulse skipping mode (PFM mode) to reduce the

power loss and improve the converter efficiency. During boosting, the PWM converter is turned off once the

inductor current is less than 75mA; and the PWM is turned back on only when the voltage at PMID pin drops to

about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between

PWM and PFM mode.

9.5.8.4 Protection in Boost Mode

9.5.8.4.1 Output Overvoltage Protection

The IC provides a built-in over-voltage protection to protect the device and other components against damage if

the VBUS voltage goes too high. When an over-voltage condition is detected, the IC turns off the PWM

converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. Once

VBUS drops to the normal level, the boost starts after host sets OPA_MODE to “1” or OTG pin stays in active

status.

9.5.8.4.2 Output Overload Protection

The IC provides a built-in over-load protection to prevent the device and battery from damage when VBUS is

over loaded. Once the over load condition is detected, Q1 operates in linear mode to limit the output current. If

the over load condition lasts for more than 30ms, the over-load fault is detected. When an over-load condition is

detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out

fault pulse in STAT pin. The boost will not start until the host clears the fault register.

9.5.8.4.3 Battery Overvoltage Protection

During boosting, when the battery voltage is above the battery over voltage threshold, VBATMAX, or below the

minimum battery voltage threshold, VBATMIN, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets

fault status bits and sends out fault pulse in STAT pin. Once the battery voltage goes above VBATMIN, the boost

will start after the host sets OPA_MODE to “1” or OTG pin stays in active status.

9.5.8.5 STAT Pin in Boost Mode

During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault

conditions, a 128-μs pulse is sent out to notify the host.

9.5.9 High Impedance (Hi-Z) Mode

In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the

CD pin high causes the charger to enter Hi-Z mode. When in default mode and the CD pin is low, the charger

automatically enters Hi-Z mode if

1. VBUS > UVLO and a battery with VBAT > VLOWV is inserted, or

2. VBUS falls below UVLO.

When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is

set to “1” and OTG pin is not in active status.

STARTCondition

DATA

CLK

STOP Condition

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In order to exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO and the HOST must write

a "0" to the HZ-MODE control bit.

9.6 Programming

9.6.1 Serial Interface Description

I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The IC works as a slave and is compatible with the following data transfer modes, as defined in the I2C-Bus

Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write

mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements. Register contents remain intact as long as

supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The

device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that

SDA changes while SCL is LOW.

The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode

in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-

mode. The bq24157B device supports 7-bit addressing only. The device 7-bit address is defined as ‘1101010’

(6AH).

9.6.1.1 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 18. All I2C-compatible devices should

recognize a start condition.

Figure 18. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 19). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 19) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

DataOutput

byTransmitter

DataOutput

byReceiver

SCL From

Master

Not Acknowledge

Acknowledge

ClockPulsefor

Acknowledgement

1 2 89

START

Condition

DATA

CLK

DataLine

Stable;

DataValid

Change

ofData

Allowed

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Programming (continued)

Figure 19. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see Figure 21). This releases the bus and stops the communication

link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a

stop condition, all devices know that the bus is released, and they wait for a start condition followed by a

matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to

prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not

listed in this section will result in FFh being read out.

Figure 20. Acknowledge on the I2C Bus™

SDA

SCL

RecognizeSTARTor

REPEATEDSTART

Condition

RecognizeSTOP or

REPEATEDSTART

Condition

Generate ACKNOWLEDGE

Signal

Acknowledgement

SignalFromSlave

MSB

Address

R/W

ACK

ClockLineHeldLowWhile

InterruptsareServiced

ACK

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Programming (continued)

Figure 21. Bus Protocol

9.6.1.2 H/S Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS

master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission

speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of

the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be

used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a

STOP condition to prevent the slave I2C logic from getting stuck in a bad state.

Attempting to read data from register addresses not listed in this section results in FFh being read out.

9.6.1.3 I2C Update Sequence

The IC requires a start condition, a valid I2C address, a register address byte, and a data byte for a single

update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of

a single clock pulse. A valid I2C address selects the IC. The IC performs an update on the falling edge of the

acknowledge signal that follows the LSB byte.

For the first update, the IC requires a start condition, a valid I2C address, a register address byte, a data byte.

For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is

received, the IC releases the I2C bus, and awaits a new start conditions.

S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P

Data Transferred

‘0’ (Write) (n Bytes+ Acknowledge)

Frommasterto IC A = Acknowledge(SDA LOW)

A = Notacknowledge(SDA

HIGH)

From ICto master S =STARTcondition

Sr =RepeatedSTARTcondition

P =STOP condition

(a) F/S-Mode

F/S-Mode HS-Mode

S HS-MASTERCODE ASr SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P

Data Transferred

‘0’ (write) (n Bytes+ Acknowledge)

Sr Slave A.

(b)HS- Mode

F/S-Mode

HS-Mode

Continues

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Programming (continued)

Figure 22. Data Transfer Format in F/S Mode and H/S Mode

9.6.1.4 Slave Address Byte

MSB LSB

X1101011

The slave address byte is the first byte received following the START condition from the master device.

9.6.1.5 Register Address Byte

MSB LSB

0 0 0 0 0 D2 D1 D0

Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which

contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a

bidirectional I2C-bus interface. Among them, four internal registers have read and write access; and one has only

read access.

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9.7 Register Description

Table 3. Status/Control Register (Read/Write)

Memory Location: 00, Reset State: x1xx 0xxx

BIT NAME READ/WRITE FUNCTION

B7 (MSB) TMR_RST/OTG Read/Write Write: TMR_RST function, write "1" to reset the safety timer (auto clear)

Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level

B6 EN_STAT Read/Write 0-Disable STAT pin function, 1-Enable STAT pin function (default 1)

B5 STAT2 Read Only 00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault

B4 STAT1 Read Only

B3 BOOST Read Only 1-Boost mode, 0-Not in boost mode

B2 FAULT_3 Read Only Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or

VBUS<VUVLO,

100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No battery

Boost mode: 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage is too low,

100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA

B1 FAULT_2 Read Only

B0 (LSB) FAULT_1 Read Only

(1) The range of the weak battery voltage threshold (V(LOWV)) is 3.4 V to 3.7 V with an offset of 3.4 V and steps of 100 mV (default 3.7 V,

using bits B4-B5).

Table 4. Control Register (Read/Write)

Memory Location: 01, Reset State: 0011 0000

BIT NAME READ/WRITE FUNCTION

B7 (MSB) Iin_Limit_2 Read/Write 00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-

USB host/charger with 800-mA current limit, 11-No input current limit

B6 Iin_Limit_1 Read/Write

B5 V(LOWV_2) (1) Read/Write Weak battery voltage threshold: 200mV step (default 1)

B4 V(LOWV_1) (1) Read/Write Weak battery voltage threshold: 100mV step (default 1)

B3 TE Read/Write 1-Enable charge current termination, 0-Disable charge current termination (default 0)

B2 CE Read/Write 1-Charger is disabled, 0-Charger enabled (default 0)

B1 HZ_MODE Read/Write 1-High impedance mode, 0-Not high impedance mode (default 0)

B0 (LSB) OPA_MODE Read/Write 1-Boost mode, 0-Charger mode (default 0)

Table 5. Control/Battery Voltage Register (Read/Write)

Memory Location: 02, Reset State: 0000 1010

BIT NAME READ/WRITE FUNCTION

B7 (MSB) VO(REG5) Read/Write Battery Regulation Voltage: 640 mV step (default 0)

B6 VO(REG4) Read/Write Battery Regulation Voltage: 320 mV step (default 0)

B5 VO(REG3) Read/Write Battery Regulation Voltage: 160 mV step (default 0)

B4 VO(REG2) Read/Write Battery Regulation Voltage: 80 mV step (default 0)

B3 VO(REG1) Read/Write Battery Regulation Voltage: 40 mV step (default 1)

B2 VO(REG0) Read/Write Battery Regulation Voltage: 20 mV step (default 0)

B1 OTG_PL Read/Write 1-OTG Boost Enable with High level, 0-OTG Boost Enable with Low level (default 1);

not applicable to OTG pin control of current limit at POR in default mode

B0 (LSB) OTG_EN Read/Write 1-Enable OTG Pin in HOST mode, 0-Disable OTG pin in HOST mode (default 0), not

applicable to OTG pin control of current limit at POR in default mode

• Charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and steps of 20 mV (default 3.54 V), using

bits B2-B7.

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Table 6. Vender/Part/Revision Register (Read only)

Memory Location: 03, Reset State: 0101 000x

BIT NAME READ/WRITE FUNCTION

B7 (MSB) Vender2 Read Only Vender Code: bit 2 (default 0)

B6 Vender1 Read Only Vender Code: bit 1 (default 1)

B5 Vender0 Read Only Vender Code: bit 0 (default 0)

B4 PN1 Read Only For I2C Address 6AH: 01–NA, 10–bq24157, 11–NA.

B3 PN0 Read Only

B2 Revision2 Read Only 011: Revision 1.0;

001: Revision 1.1;

100-111: Future Revisions

B1 Revision1 Read Only

B0 (LSB) Revision0 Read Only

(1) See Table 12

(2) See Table 11

Table 7. Battery Termination/Fast Charge Current Register (Read/Write)

Memory Location: 04, Reset State: 0000 0001

BIT NAME READ/WRITE FUNCTION

B7 (MSB) Reset Read/Write Write: 1-Charger in reset mode, 0-No effect, Read: always get "0"

B6 VI(CHRG3) (1) Read/Write Charge current sense voltage: 27.2 mV step

B5 VI(CHRG2) (1) Read/Write Charge current sense voltage: 13.6 mV step

B4 VI(CHRG1) (1) Read/Write Charge current sense voltage: 6.8 mV step

B3 VI(CHRG0) (1) Read/Write NA

B2 VI(TERM2) (2) Read/Write Termination current sense voltage: 13.6 mV step (default 0)

B1 VI(TERM1) (2) Read/Write Termination current sense voltage: 6.8 mV step (default 0)

B0 (LSB) VI(TERM0) (2) Read/Write Termination current sense voltage: 3.4 mV step (default 1)

• Charge current sense voltage offset is 37.4 mV and default charge current is 550 mA, if 68-mΩsensing

resistor is used and LOW_CHG=0.

Table 8. Special Charger Voltage/Enable Pin Status Register

Memory location: 05, Reset state: 000X X100

BIT NAME READ/WRITE FUNCTION

B7 (MSB) NA Read/Write NA

B6 NA Read/Write NA

B5 LOW_CHG Read/Write 0 – Normal charge current sense voltage at 04H (default 1),

1 – Low charge current sense voltage of 22.1 mV

B4 DPM_STATUS Read Only 0 – DPM mode is not active,

1 – DPM mode is active

B3 CD_STATUS Read Only 0 – CD pin at LOW level,

1 – CD pin at HIGH level

B2 VSREG2 Read/Write Special charger voltage: 320 mV step (default 1)

B1 VSREG1 Read/Write Special charger voltage: 160 mV step (default 0)

B0 (LSB) VSREG0 Read/Write Special charger voltage: 80 mV step (default 0)

• Special charger voltage offset is 4.2 V and default special charger voltage is 4.52 V.

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(1) Refer to Table 12

Table 9. Safety Limit Register (READ/WRITE, Write only once after reset!)

Memory location: 06, Reset state: 01000000

BIT NAME READ/WRITE FUNCTION

B7 (MSB) VMCHRG3 (1) Read/Write Maximum charge current sense voltage: 54.4 mV step (default 0) (2)

B6 VMCHRG2 (1) Read/Write Maximum charge current sense voltage: 27.2 mV step (default 1)

B5 VMCHRG1 (1) Read/Write Maximum charge current sense voltage: 13.6 mV step (default 0)

B4 VMCHRG0 (1) Read/Write Maximum charge current sense voltage: 6.8 mV step (default 0)

B3 VMREG3 Read/Write Maximum battery regulation voltage: 160 mV step (default 0)

B2 VMREG2 Read/Write Maximum battery regulation voltage: 80 mV step (default 0)

B1 VMREG1 Read/Write Maximum battery regulation voltage: 40 mV step (default 0)

B0 (LSB) VMREG0 Read/Write Maximum battery regulation voltage: 20 mV step (default 0)

• Maximum charge current sense voltage offset is 37.4 mV (550 mA), default at 64.6 mV (950 mA) and the

maximum charge current option is 1.55 A (105.4 mV), if 55-mΩsensing resistor is used.

• Maximum battery regulation voltage offset is 4.2V (default at 4.2 V) and maximum battery regulation voltage

option is 4.44V.

• Memory location 06H resets only when V(CSOUT) drops below either 1) V(SHORT) threshold (typ. 2.05 V) if

VBUS > V(UVLO) or 2) the digital reset threshold of 2.4 V typical if VBUS < V(UVLO). Programmed values in the

safety limit register exclude higher values from memory locations 02 (battery regulation voltage), and from

memory location 04 (fast charge current) from being successfully written.

• If host accesses (write command) to some other register before Safety limit register, the safety default values

are used.

CVREF

33 nF

CBOOT

PACK–

PACK+

CCSOUT

SCL

SDA

CSOUT

CSIN

PGND

I2C BUS

VAUX

HOST

SCL

SDA

STAT

VREF

STAT

PMID

VBUS

CIN

VBUS

CIN

BOOT

RSNS

CCSIN

VBAT

1 Fm

4.7 Fm

10 kW

L 1.0 H

CO1

22 Fm

0.1 Fm

1 Fm

bq24157

SLRST

10 kWCD

SLRST

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The bq24157 is a compact, flexible, high-efficiency, USB-friendly, switch-mode charge management solution for

single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The bq24157 integrates

a synchronous PWM controller, power MOSFETs, input current sensing, high-accuracy current and voltage

regulation, and charge termination, into a small DSBGA package. The charge parameters can be programmed

through an I2C interface.

10.1.1 Typical Application

VBUS =5V,ICHARGE = 1250 mA, VBAT = 3.5 to 4.44 V (adjustable).

Figure 23. I2C Controlled 1-Cell USB Charger Application Circuit with USB OTG Support.

10.1.1.1 Design Requirements

Use the following typical application design procedure to select external components values for the bq24157

device.

Specification Test Condition MIN TYP MAX UNIT

Input DC voltage, VIN Input voltage from AC adapter input 4 5 6 V

Input current Maximum input current from AC adapter input 0.1 0.1 to 0.5 1.5 A

Charge current Battery charge current 0.325 0.7 1.55 A

Output regulation voltage Voltage applied at VBAT 0 3 to 4.2 4.44 V

Operating junction temperature range, TJ0 125 °C

2 3 2 -6

OUT

4 (40 10 ) (1 10 )

p ´ ´ ´ ´

2 2

OUT

4 L

p ´ ´

OUT OUT

o2 L C

p ´ ´

LPK

0.42

I 1.25

= +

LPK OUT

I I

= +

L-6

2.5 (5 - 2.5)

I = 6

5 (3 10 ) (1 10 )

´ ´ ´ ´

´ ´

LOUT

VBAT (VBUS - VBAT)

I = VBUS Lf

OUT 6

2.5 (5 - 2.5)

L =

5 (3 10 ) 1.25 0.3

´ ´ ´ ´

´ ´ D

OUT L

VBAT (VBUS - VBAT)

L = VBUS If

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(1) See Third-Party Products Disclaimer

10.1.1.2 Detailed Design Procedure

Systems Design Specifications:

• VBUS = 5 V

• VBAT = 4.2 V (1-Cell)

• I(charge) = 1.25 A

• Inductor ripple current = 30% of fast charge current

1. Determine the inductor value (LOUT) for the specified charge current ripple:

, the worst case is when battery voltage is as close as to half of the input

voltage.

(1)

LOUT = 1.11 μH

Select the output inductor to standard 1 μH. Calculate the total ripple current with using the 1-μH inductor:

(2)

(3)

ΔIL= 0.42 A

Calculate the maximum output current:

(4)

(5)

ILPK = 1.46 A

Select 2.5mm by 2mm 1-μH 1.5-A surface mount multi-layer inductor. The suggested inductor part numbers

are shown as following.

Table 10. Inductor Part Numbers(1)

PART NUMBER INDUCTANCE SIZE MANUFACTURER

LQM2HPN1R0MJ0 1 μH 2.5 x 2.0 mm Murata

MIPS2520D1R0 1 μH 2.5 x 2.0 mm FDK

MDT2520-CN1R0M 1 μH 2.5 x 2.0 mm TOKO

CP1008 1 μH 2.5 x 2.0 mm Inter-Technical

spacer

2. Determine the output capacitor value (COUT) using 40 kHz as the resonant frequency:

(6)

(7)

(8)

100

200

300

400

500

600

700

800

Loss (mW)

Battery Charge Efficiency Battery Charge Loss

500 600 700 800 900 1000 1100 1200 1300

Efficiency (%)

Charge Current (mA)

FDK

TOKO

Inter-Technical

muRata

500 600 700 800 900 1000 1100 1200 1300

Charge Current (mA)

FDK

TOKO

Inter-Technical

muRata

T = 25°C

VBUS = 5 V

VBAT = 3 V

AT = 25°C

VBUS = 5 V

VBAT = 3 V

(SNS)

85mV

R1.25A

(RSNS)

(SNS) (CHARGE)

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COUT = 15.8 μF

Select two 0603 X5R 6.3V 10-μF ceramic capacitors in parallel i.e., Murata GRM188R60J106M.

3. Determine the sense resistor using the following equation:

(9)

The maximum sense voltage across the sense resistor is 85 mV. In order to get a better current regulation

accuracy, V(RSNS) should equal 85mV, and calculate the value for the sense resistor.

(10)

R(SNS) = 68 mΩ

This is a standard value. If it is not a standard value, then choose the next close value and calculate the real

charge current. Calculate the power dissipation on the sense resistor:

P(RSNS) = I(CHARGE) 2× R(SNS)

P(RSNS) = 1.252× 0.068

P(RSNS) = 0.106 W

Select 0402 0.125-W 68-mΩ2% sense resistor, i.e. Panasonic ERJ2BWGR068.

4. Measured efficiency and total power loss with different inductors are shown in Figure 24. SW node and

inductor current waveform are shown in Figure 34.

Figure 24. Measured Efficiency and Power Loss

OUT OUT

o2 L C

p ´ ´

I(CHRG0)

O(CHARGE_STEP) (SNS)

I = R

I(TERM0)

O(TERM_STEP) (SNS)

I = R

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10.1.2 Charge Current Sensing Resistor Selection Guidelines

Both the termination current range and charge current range depend on the sensing resistor (RSNS). The

termination current step (IOTERM_STEP) can be calculated using Equation 11:

(11)

Table 11 shows the termination current settings for three sensing resistors.

Table 11. Termination Current Settings for 55-mΩ, 68-mΩ, 100-mΩSense Resistors

BIT VI(TERM) (mV) I(TERM) (mA)

R(SNS) = 55mΩI(TERM) (mA)

R(SNS) = 68mΩI(TERM) (mA)

R(SNS) = 100mΩ

VI(TERM2) 13.6 247 200 136

VI(TERM1) 6.8 124 100 68

VI(TERM0) 3.4 62 50 34

Offset 3.4 62 50 34

For example, with a 68-mΩsense resistor, V(ITERM2) = 1, V(ITERM1) = 0, and V(ITERM0) = 1, ITERM = [ (13.6 mV x 1) +

(6.8 mV x 0) + (3.4 mV x 1) + 3.4 mV ] / 68 mΩ=200mA+0+50mA+50mA=300mA.

The charge current step (IO(CHARGE_STEP)) is calculated using Equation 12:

(12)

Table 12 shows the charge current settings for three sensing resistors.

Table 12. Charge Current Settings for 55-mΩ, 68-mΩand 100-mΩSense Resistors

BIT VI(REG) (mV) IO(CHARGE) (mA)

R(SNS) = 55mΩIO(CHARGE) (mA)

R(SNS) = 68mΩIO(CHARGE) (mA)

R(SNS) = 100mΩ

VI(CHRG3) 27.2 495 400 272

VI(CHRG2) 13.6 247 200 136

VI(CHRG1) 6.8 124 100 68

VI(CHRG0) N/A N/A N/A N/A

Offset 37.4 680 550 374

For example, with a 68-mΩsense resistor, V(CHRG3) = 1, V(CHRG2) = 1, V(ICHRG1) = 1, ICHRG = [ (27.2 mV x 1) +

(13.6 mV x 1) + (6.8 mV x 1) + 37.4 mV ] / 68 mΩ= 400 mA + 200 + 100 + 550 mA = 1250 mA.

10.1.3 Output Inductor and Capacitance Selection Guidelines

The IC provides internal loop compensation. With the internal loop compensation, the highest stability occurs

when the LC resonant frequency, fo, is approximately 40 kHz (20 kHz to 80 kHz). Equation 13 can be used to

calculate the value of the output inductor, LOUT, and output capacitor, COUT.

(13)

To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 μF and 47 μF is

recommended for COUT, see the application section for components selection.

VBUS =5V,ICHARGE = 1250 mA, VBAT = 3.5 V to 4.44 V (Adjustable).

VBUS

100mV/div,

5.05VOffset

VSW

2V/div

5 S/divm

VBAT

100mV/div,

3.5VOffset

0.2 A/div

100 s/divμ

VBUS

200 mV/div,

5.05 V Offset

VSW

5 V/div

500 mV/div

BAT

VBAT

200 mV/div,

3.5 V Offset

VBUS

10mV/div,

5.05VOffset

100mA/div

100nS/div

VBAT

10mV/div,

3.5VOffset

VSW

2V/div

VBAT

2V/div

VBUS

5V/div

50mA/div

BUS

100mS/div

VBAT

2V/div

VSW

5V/div

0.5 A/div

BAT

1S/div

BatteryInserted

BatteryRemoved

VBUS

2V/div

VSW

5V/div

0.5 A/div

BAT

10ms/div

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10.2 Typical Performance Curves

Using circuit shown in Figure 23, TA= 25°C, unless otherwise specified.

VBUS = 0-5V, Iin_limit = 500mA, Voreg = 4.2V

VBAT = 3.5V, ICHG = 550mA, 32S mode

Figure 25. Adapter Insertion

VBUS = 5 V VBAT = 3.4 V Iin_limit = 500 mA

Figure 26. Battery Insertion/Removal (HOST Mode)

VBUS = 5 V No Battery

Connected

Figure 27. Battery Detection at Power Up

VBUS = 5.05 V, VBAT = 3.5V, IBUS = 217 mA

Figure 28. BOOST Waveform (PWM Mode)

VBUS = 5.05 V, VBAT = 3.5V, IBUS = 42 mA

Figure 29. BOOST Waveform (PFM Mode)

VBUS = 5.05, VBAT = 3.5V, IBUS = 0-360 mA

Figure 30. Load Step Up Response (BOOST Mode)

100 s/divμ

VBUS

100 mV/div

5.05 V Offset

VSW

5 V/div

0.1 A/div

BAT

VBAT

0.2 V/div

3.5 V Offset

VBUS

200 mV/div,

5.05 V Offset

VSW

5 V/div

500 mV/div

BAT

100 S/divm

VBAT

200 mV/div,

3.5 V Offset

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Typical Performance Curves (continued)

VBUS = 5.05 V, VBAT = 3.5V, IBUS = 0-217 mA

Figure 31. Load Step Up Response (BOOST Mode)

VBUS = 5.05, VBAT = 3.5V, IBUS = 360-0 mA

Figure 32. Load Step Down Response (BOOST Mode)

VIN +

PMID

VBUS SW

PGND

bq2415x

Isns

Rsns

Ichg

BAT

Isys

System

Load

bq24157

SLUSB80E –SEPTEMBER 2012–REVISED JANUARY 2018

www.ti.com

Product Folder Links: bq24157

11 Power Supply Recommendations

11.1 System Load After Sensing Resistor

One of the simpler high-efficiency topologies connects the system load directly across the battery pack, as

shown in Figure 33. The input voltage has been converted to a usable system voltage with good efficiency from

the input. When the input power is on, it supplies the system load and charges the battery pack at the same time.

When the input power is off, the battery pack powers the system directly.

Figure 33. System Load After Sensing Resistor

11.1.1 The Advantages:

1. When the AC adapter is disconnected, the battery pack powers the system load with minimum power

dissipation. Consequently, the time that the system runs on the battery pack can be maximized.

2. It reduces the number of external path selection components and offers a low-cost solution.

3. Dynamic power management (DPM) can be achieved. The total of the charge current and the system current

can be limited to a desired value by setting the charge current value. When the system current increases, the

charge current drops by the same amount. As a result, no potential over-current or over-heating issues are

caused by excessive system load demand.

4. The total input current can be limited to a desired value by setting the input current limit value. USB

specifications can be met easily.

5. The supply voltage variation range for the system can be minimized.

6. The input current soft-start can be achieved by the generic soft-start feature of the IC.

11.1.2 Design Requirements and Potential Issues:

1. If the system always demands a high current (but lower than the regulation current), the battery charging

never terminates. Thus, the battery is always charged, and its lifetime may be reduced.

2. Because the total current regulation threshold is fixed and the system always demands some current, the

battery may not be charged with a full-charge rate and thus may lead to a longer charge time.

3. If the system load current is large after the charger has been terminated, the IR drop across the battery

impedance may cause the battery voltage to drop below the refresh threshold and start a new charge cycle.

The charger would then terminate due to low charge current. Therefore, the charger would cycle between

charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold,

resulting in a much slower cycling.

4. In a charger system, the charge current is typically limited to about 30mA, if the sensed battery voltage is

below 2V short circuit protection threshold. This results in low power availability at the system bus. If an

external supply is connected and the battery is deeply discharged, below the short circuit protection

threshold, the charge current is clamped to the short circuit current limit. This then is the current available to

the system during the power-up phase. Most systems cannot function with such limited supply current, and

the battery supplements the additional power required by the system. Note that the battery pack is already at

the depleted condition, and it discharges further until the battery protector opens, resulting in a system

shutdown.

5. If the battery is below the short circuit threshold and the system requires a bias current budget lower than the

bq24157

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SLUSB80E –SEPTEMBER 2012–REVISED JANUARY 2018

Product Folder Links: bq24157

System Load After Sensing Resistor (continued)

short circuit current limit, the end-equipment will be operational, but the charging process can be affected

depending on the current left to charge the battery pack. Under extreme conditions, the system current is

close to the short circuit current levels and the battery may not reach the fast-charge region in a timely

manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process.

Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the

application possible.

6. If the battery pack voltage is too low, highly depleted, totally dead or even shorted, the system voltage is

clamped by the battery and it cannot operate even if the input power is on.

High

Frequency

Current

Path

L1 R1

VBUS

PMID

PGND

SW VBAT

BAT

VIN

bq24157

SLUSB80E –SEPTEMBER 2012–REVISED JANUARY 2018

www.ti.com

Product Folder Links: bq24157

12 Layout

12.1 Layout Guidelines

It is important to pay special attention to the PCB layout. The following provides some guidelines:

• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed

as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor

connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area

from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation

problems, proper layout to minimize high frequency current path loop is critical. (See Figure 34.) The sense

resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads

connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other

on adjacent layers (do not route the sense leads through a high-current path). (See Figure 35.)

• Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components

such that routing interrupts power stage currents). All small control signals should be routed away from the

high current paths.

• The PCB should have a ground plane (return) connected directly to the return of all components through vias

(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for small-

signal components). A star ground design approach is typically used to keep circuit block currents isolated

(high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single

ground plane for this design gives good results. With this small layout and a single ground plane, there is no

ground-bounce issue, and having the components segregated minimizes coupling between signals.

• The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the

maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be

connected to the ground plane to return current through the internal low-side FET.

• Place 4.7μF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current

loop area as small as possible. Place 1μF input capacitor as close to VBUS pin and PGND pin as possible to

make high frequency current loop area as small as possible (see Figure 36).

Figure 34. High Frequency Current Path

VBUS

PMID

PGND

4.7µF

1µF

Vin+

Vin–

ChargeCurrentDirection

ToCSINandCSOUTpin

RSNS

ToInductor ToCapacitorandbattery

CurrentSensingDirection

bq24157

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SLUSB80E –SEPTEMBER 2012–REVISED JANUARY 2018

Product Folder Links: bq24157

12.2 Layout Example

Figure 35. Sensing Resistor PCB Layout

Figure 36. Input Capacitor Position and PCB Layout Example

bq24157

SLUSB80E –SEPTEMBER 2012–REVISED JANUARY 2018

www.ti.com

Product Folder Links: bq24157

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.4 Trademarks

E2E, NanoFree are trademarks of Texas Instruments.

I2C is a trademark of NXP B.V. Corporation.

13.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

A1 A2 A3 A4

E1 E2 E3 E4

WCSP PACKAGE

(Top View)

CHIP SCALE PACKAGE

(Top Side Symbol For bq24157)

TIYMLLLLS

bq24157A

0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code, LLLL-Lot Trace Code, S-Assembly Site Code

bq24157

www.ti.com

SLUSB80E –SEPTEMBER 2012–REVISED JANUARY 2018

Product Folder Links: bq24157

14.1 Package Summary

14.1.1 Chip Scale Packaging Dimensions

The bq24157 device is available in a 20-bump chip scale package (YFF, NanoFree™).

The package dimensions are:

D E

Max = 2.17mm Max = 2.03 mm

Min = 2.11 mm Min = 1.97 mm

PACKAGE OPTION ADDENDUM

www.ti.com 18-Dec-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

BQ24157YFFR ACTIVE DSBGA YFF 20 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM BQ24157A

BQ24157YFFT ACTIVE DSBGA YFF 20 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM BQ24157A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Dec-2017

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

BQ24157YFFR DSBGA YFF 20 3000 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1

BQ24157YFFT DSBGA YFF 20 250 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Dec-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ24157YFFR DSBGA YFF 20 3000 182.0 182.0 20.0

BQ24157YFFT DSBGA YFF 20 250 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Dec-2017

Pack Materials-Page 2

D: Max =

E: Max =

2.172 mm, Min =

2.03 mm, Min =

2.112 mm

1.97 mm

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Authorized Distributor

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