April 2016
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This is information on a product in full production.
www.st.com
STBCFG01
Switch mode single cell Li+ battery charger with OTG boost,
voltage mode fuel gauge and LDO
Datasheet - production data
Features
High efficiency switching battery charger
2 MHz or 3 MHz switching frequency
1.2 A max. charging current
20 V tolerant input with OVP
Programmable input current limitation
and dynamic input current limit
Battery overvoltage protection
Auto-recharge
Integrated current sensing resistor
USB compatible
Voltage mode fuel gauge
External sensing resistor is not needed
Battery swap detection through ID
resistor
Low battery voltage and low SOC
programmable alarms
50 mA LDO for system boot in dead battery
condition
USB OTG VBUS generation (500 mA)
USB overvoltage protection
Programmable battery overcurrent
protection
Automatic 60 mA input pre-bias
I²C compatible control interface
Interrupt output pin
Flip Chip package, 25 bumps (2.3 x 2.2 mm)
Applications
Mobile phones
Smart phones
Description
The STBCFG01 is a switching battery charger
integrating the necessary functions to charge
single cell Li-Ion batteries, monitor the battery
charge and generate 5 V to supply USB OTG bus
powered devices.
The IC also integrates the LDO regulator to
support system boot in dead battery conditions.
The battery charger features a smart input
current limit: the maximum input current can be
selected through I²C and if the input voltage
drops below a programmable threshold, the input
current is reduced even if the selected maximum
current limit has not been reached yet. The
dynamic input current limit can be disabled.
An automatic input pre-bias load makes the
device suitable for applications using voltage
sources with a minimum external load for the
right regulation.
The STBCFG01 also integrates a voltage mode
fuel gauge to provide the state of charge
evaluation without the current sensing resistor.
Contents
STBCFG01
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Contents
1 Application schematic .................................................................... 5
2 Pin configuration ............................................................................. 6
3 Maximum ratings ............................................................................. 8
4 Electrical characteristics ................................................................ 9
5 Operation description ................................................................... 15
5.1 Battery charger ................................................................................ 15
5.1.1 Input current limit .............................................................................. 16
5.1.2 Dynamic input current limit (DICL) ................................................... 16
5.1.3 Automatic recharge .......................................................................... 17
5.1.4 Battery detection ............................................................................... 17
5.1.5 Battery overvoltage protection .......................................................... 18
5.2 OTG boost....................................................................................... 18
5.3 LDO regulator .................................................................................. 19
5.4 Pre-bias ........................................................................................... 19
5.5 Fuel gauge ...................................................................................... 20
5.5.1 Operating mode ................................................................................ 20
5.5.2 Battery connection ............................................................................ 20
5.5.3 Low battery alarm ............................................................................. 20
5.5.4 Battery swap ..................................................................................... 21
5.6 Thermal shutdown ........................................................................... 21
5.7 Shutdown mode .............................................................................. 22
5.8 Watchdog ........................................................................................ 22
5.9 Alarms ............................................................................................. 22
6 I²C compatible interface registers ................................................ 23
6.1 Fuel gauge registers ....................................................................... 24
6.2 Charger/OTG/LDO registers ........................................................... 26
7 Package information ..................................................................... 33
7.1 Flip Chip 25 (2.3x2.2 mm) option H package information ............... 33
8 Ordering information ..................................................................... 35
9 Revision history ............................................................................ 36
STBCFG01
List of tables
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List of tables
Table 1: Typical bill of material (BOM) ........................................................................................................ 5
Table 2: Pin description .............................................................................................................................. 6
Table 3: Absolute maximum ratings ........................................................................................................... 8
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Electrical characteristics ............................................................................................................... 9
Table 6: Register map............................................................................................................................... 23
Table 7: Fuel gauge mode register (address: 00h) .................................................................................. 24
Table 8: FG_CTRL register (address: 01h) .............................................................................................. 24
Table 9: SOC register LSB (register address: 02h) .................................................................................. 25
Table 10: SOC register MSB (register address: 03h) ............................................................................... 25
Table 11: VBAT register LSB (register address: 08h) .............................................................................. 25
Table 12: VBAT register MSB (register address: 09h) ............................................................................. 25
Table 13: OCV register LSB (register address: 0Dh) ............................................................................... 25
Table 14: OCV register MSB (register address: 0Eh) .............................................................................. 25
Table 15: VM_CNF register LSB (register address: 11h) ......................................................................... 25
Table 16: ALARM_SOC register (address: 13h) ...................................................................................... 26
Table 17: ALARM_Voltage register (address: 14h) .................................................................................. 26
Table 18: CHG_Cfg1 register ................................................................................................................... 26
Table 19: CHG_Cfg2 register (address: 91h) ........................................................................................... 26
Table 20: CHG_Cfg3 register (address: 92h) ........................................................................................... 27
Table 21: CHG_Cfg4 register format (register address: 93h)................................................................... 28
Table 22: CHG_Cfg5_OTG_Status register format (register address: 94h) ............................................ 28
Table 23: CHG_Status1 register format (register address: 95h) .............................................................. 29
Table 24: CHG_Status2 register format (register address: 96h) .............................................................. 30
Table 25: Int_Enable_1 register format (register address: 97h) ............................................................... 30
Table 26: Int_Enable_2 register format (register address: 98h) ............................................................... 30
Table 27: Int_Latch_1 register format (register address: 99h) ................................................................. 31
Table 28: Int_Latch_2 register format (register address: 9Ah) ................................................................. 32
Table 29: Flip Chip 25 (2.3 x 2.2 mm) option H package mechanical data .............................................. 34
Table 30: Ordering information ................................................................................................................. 35
Table 31: Document revision history ........................................................................................................ 36
List of figures
STBCFG01
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List of figures
Figure 1: STBCFG01 application schematic .............................................................................................. 5
Figure 2: Pin connections (top view) ........................................................................................................... 6
Figure 3: Simplified charger architecture .................................................................................................. 15
Figure 4: CC/CV charging cycle ............................................................................................................... 16
Figure 5: DICL activation .......................................................................................................................... 17
Figure 6: DICL enable strategy ................................................................................................................. 17
Figure 7: Battery charger flowchart ........................................................................................................... 18
Figure 8: Pre-bias enable strategy ............................................................................................................ 19
Figure 9: Battery swap detection .............................................................................................................. 21
Figure 10: Flip Chip 25 (2.3x 2.2 mm) option H package outline ............................................................. 33
Figure 11: Flip Chip 25 (2.3 x2.2 mm) option H recommended footprint ................................................. 34
STBCFG01
Application schematic
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1 Application schematic
Figure 1: STBCFG01 application schematic
Table 1: Typical bill of material (BOM)
Component name
Size
Value
Supplier
Part number
C1
0603
10 µF, 16 V
MURATA
GRM188R61C106MA73D
C2
0603
4.7 µF, 25 V
TDK
C1608X5R1E475K080AC
C3
0402
1 µF, 16 V
MURATA
GRM155R61C105KA12D
C4
0603
4.7 µF, 25 V
TDK
C1608X5R1E475K080AC
C5
0603
1 µF, 16 V
MURATA
GRM185R61C105KE44
C6
0603
10 µF, 16 V
MURATA
GRM188R61C106MA73D
C7
0603
100 nF, 25 V
MURATA
GRM188R71H104KA93
C8
0603
1 µF, 16 V
MURATA
GRM185R61C105KE44
C9
0603
1 µF, 16 V
MURATA
GRM185R61C105KE44
L1
2.5 x 2.2 mm
1 µH, 2.2 A
TDK
VLS252012ET-1R0N
Pin configuration
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2 Pin configuration
Figure 2: Pin connections (top view)
Table 2: Pin description
Symbol
Ball
Pin function
Description
PMID
A1, B1
Power I/O
Reverse blocking MOSFET to high-side connection node
DCIN
A2, A3
Power I/O
Input supply voltage/OTG output
AGND
A4
Analog ground
Analog ground
VCELL-
A5
Analog input
Battery pack negative terminal sense input
CENn
B2
Digital input
Charger enable, active low. Internal 200 kΩ pull-down to
GND
SHDN
B3
Digital input
Shutdown input, active high. Internal 200 kΩ pull-down to
GND
RID
B4
Analog input
Battery identification resistor connection (for battery
detection). An external bias has to be applied
VCELL+
B5
Analog input
Battery pack positive terminal sense input
LX
C1, D1
Power I/O
Switch mode, inductor connection
IRQn
C2
Digital input
Open drain interrupt output, active low
DGND
C3
Digital ground
Digital ground
1V8
C4
Analog out
1.8 V internal regulator bypass pin. Bypass this pin to GND
with a capacitor of 220 nF. Do not connect any load
VREF
C5
Analog out
Reference voltage bypass pin. Do not connect any load
LDO
D2
Analog out
4.85 V LDO output
SDA
D3
Digital I/O
I²C data pin to the baseband, I²C master peripheral
SCL
D4
Digital input
I²C clock pin to the baseband, I²C master peripheral
R_SNS_N
D5, E5
Power I/O
Internal sense resistor, negative terminal
STBCFG01
Pin configuration
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Symbol
Ball
Pin function
Description
PGND
E1, E2
Power ground
Power ground
R_SNS_P
E3, E4
Power I/O
Internal sense resistor, positive terminal
Maximum ratings
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3 Maximum ratings
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDCIN, VPMID
Charger input voltage
-1.5 to +20
V
VLX
Switch mode voltage
-0.3 to +8
V
VCELL+, R_SNS_N, R_SNS_P
Battery pin
-0.3 to +6
V
VVREF, VV1V8, VCENn, VSHDN
Low voltage pins
-0.3 to +2.1
V
VAMR
All other input voltage pins
-0.3 to +5.5
V
ESD
Human body model
±2000
V
Charged device model
±250
V
TAMB
Operating ambient temperature
-30 to +85
°C
TJ
Maximum junction temperature
+125
°C
TSTG
Storage temperature
-65 to +150
°C
Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied.
Table 4: Thermal data
Symbol
Parameter
Value
Unit
Rth(JC)
Thermal resistance junction-case
TBD
°C/W
Rth(JA)
Thermal resistance junction-ambient
TBD
°C/W
STBCFG01
Electrical characteristics
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4 Electrical characteristics
TJ = -30 °C to +85 °C, VBAT = 3.6 V, VDCIN = 5 V unless otherwise specified.
Table 5: Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
General information
VIN
DCIN input voltage
range
3.78
5.95
V
fSW
Switching frequency
FSW bit = 0
2
MHz
FSW bit = 1
3
TSD
Thermal shutdown
threshold
165
°C
Hysteresis
20
tTSD
Thermal shutdown
deglitch time
50
µs
Battery charger
IIN
Current consumption
from DCIN
Charger enabled,
switching,
VBUS_CON = 5 V
14
mA
Shutdown, LDO
disabled
290
400
µA
Shutdown, LDO
enabled
500
800
µA
IBAT
Current consumption
from BAT(including
fuel gauge)
On battery power
VBUS_CON = 0 V
GG_RUN = 0
10
25
µA
On battery power
VBUS_CON = 0 V
GG_RUN = 1
32
100
µA
VINOVP
DCIN overvoltage
protection
VDCIN rising
6.05
6.3
6.62
V
VDCIN falling
5.95
6.2
6.51
VINOVP_PB
Pre-bias overvoltage
protection
VDCIN rising
7.0
V
VDCIN falling
6.9
V
Pre-bias OVP
accuracy
-5
+5
%
VINUVLO
DCIN undervoltage
lockout
VDCIN rising
3.6
V
VDCIN falling
3.5
DCIN UVLO accuracy
-5
+5
%
IPREB
Pre-bias current
60
mA
tPBD
Pre-bias current
enable deglitch time
VDCIN rising over VINOVP
but below VINOVP_PB
5
ms
tHDO
Hold-off time
Valid DCIN connection
to charging start
200
ms
Electrical characteristics
STBCFG01
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VASD
Automatic shutdown
threshold
VASD = VDCIN-VBAT,
VDCIN rising
130
mV
VASD = VDCIN-VBAT,
VDCIN falling
0
36
mV
tASD
Automatic shutdown
threshold deglitch
time
50
µs
IINLIM
DCIN current limit
ILIM configurable by I2C
90
mA
476
760
1140
VDICL
Dynamic input current
limit threshold
DICL configurable by
I2C (4.0 V, 4.25 V, 4.5
V, 4.75 V)
4.0
4.75
V
DICL accuracy
-3
+3
%
tDICL
DICL activation
deglitch time
100
ms
VFLOAT
CV regulation voltage
VBUS_CON = 5 V
3.52
4.78
V
CV regulation voltage
accuracy
VBUS_CON = 5 V
-1
+1
%
VFLD
CC to CV threshold
deglitch time
170
ms
VRCHG
Auto-recharge
threshold voltage
ARCHG bit = 1
VFLOAT-0.12
V
Auto-recharge
threshold accuracy
ARCHG bit = 1
-17
+17
%
tRCHG
Auto-recharge
threshold deglitch
time
ARCHG bit = 1
170
ms
VBATOVP
Battery overvoltage
protection
This is got by
increasing the battery
voltage until BATOVP
status register turns on
VFLOAT+0.1
V
Battery OVP accuracy
-10
+10
%
tBOVP
Battery OVP deglitch
time
170
ms
ITRK
Trickle charge current
VBAT<VTRK
45
mA
Trickle charge current
accuracy
-20
+20
%
IPRE
Pre-charge current
VTRK< VBAT<VPRE
450
mA
Pre-charge current
accuracy
-10
+10
%
IFAST
Fast charge current
VBAT> VPRE
550
1250
mA
STBCFG01
Electrical characteristics
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Fast charge current
accuracy
-10
10
%
ITERM
Termination current
50
300
mA
Termination current
accuracy
-30
30
%
tTERM
Charge termination
deglitch time
170
ms
VTRK
Trickle charge to pre-
charge battery voltage
threshold
2
V
VTRK accuracy
-5
+5
%
tTPD
Trickle charge to pre-
charge threshold
deglitch time
100
ms
VPRE
Pre-charge to fast
charge battery voltage
threshold
3
V
VPRE accuracy
-5
+5
%
tPFD
Pre-charge to fast
charge threshold
deglitch time
170
ms
VDETH
Battery detection high
threshold
3
V
VDETL
Battery detection low
threshold
2
V
IDETSNK
Sink detection current
-5
mA
tDETSRC
Current source
detection time
340
ms
tDETSNK
Current sink detection
time
200
ms
RON_HI
High-side MOSFET
on- resistance
(including reverse
blocking MOFET)
300
mΩ
RON_LOW
Low-side MOSFET
on- resistance
125
mΩ
RSNS
Internal sensing
resistor
35
68
mΩ
tMAXPRE
Maximum pre-charge
time
Including trickle charge
45
min.
tMAXCHG
Maximum fast charge
time
Including taper charge
360
min.
OTG boost regulator
IBQ
Boost quiescent
current
VBAT = 3.7 V, no load
4
mA
Electrical characteristics
STBCFG01
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VBUS
Output voltage at
VBUS_CON
4.75
5
5.25
V
IVBUS
Output current
capability
VBUS ≥ 4.75 V
500
mA
VBATUVLO
Battery undervoltage
lockout
Falling edge
3
V
Accuracy
-5
+5
%
VBUSOVP
Output overvoltage
protection
6
V
Accuracy
-5
+5
%
tVBUSOVP
VBUSOVP deglitch time
30
ms
IBATLIM
Battery average
current limitation
350
950
mA
Accuracy
-10
+10
%
ILMAX
Cycle-by-cycle
limitation
1.2
A
Z0
Output impedance in
OFF mode
100
kΩ
LDO output
VLDO
LDO output voltage
ILDO = 50 mA, VDCIN-
VLDO>300 mV
4.85
V
Accuracy
-4
+4
%
ILDO
LDO output current
VDCIN- VLDO > 300 mV
50
mA
ISC
LDO short-circuit
current
VLDO ≤ 4 V
75
mA
Accuracy
-27
+27
%
VDO
LDO dropout voltage
ILDO = 50 mA
150
300
mV
VINMIN
LDO input
undervoltage lockout
VDCIN rising
3.6
V
VDCIN falling
3.5
VINMIN accuracy
-5
+5
%
VINMAX
LDO input
overvoltage lockout
VDCIN rising
6.3
V
VDCIN falling
6.2
VINMAX accuracy
-5
+5
%
Fuel gauge
IFGQ
Fuel gauge quiescent
current
GG_RUN = 1
25
µA
GG_RUN = 0
2
UVLO
Fuel gauge
undervoltage lockout
Rising edge
2.0
2.6
2.7
V
Hysteresis
100
mV
fOSC
Internal time base
frequency
512
kHz
Time base accuracy
1
%
STBCFG01
Electrical characteristics
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tSTRB
ADC conversion
strobe
4
s
tSWAP
Battery swap deglitch
time
1
s
VBATERR
VBAT measurement
error
-0.5
+0.5
%
VBATRES
VBAT measurement
resolution
OCV reading
2.69
mV
VBATRNG
VBAT measurement
range
2.5
5.5
V
VRIDTH
RID threshold
1.2
1.25
1.3
V
Hysteresis
0.130
V
I²C compatible interface
VIH
High level input
voltage
1.3
V
VIL
Low level input
voltage
0.6
V
VOL
Low level output
voltage at 10 mA sink
current for open drain
I/O
0.3
V
CIO
I/O pin capacitance
10
pF
fSCL
SCL clock frequency
400
kHz
tLOW
Minimum clock low
period
1.3
µs
tHIGH
Minimum clock high
period
600
ns
tF
SDA and SCL fall
time
300
ns
tHOLD_STA
Start condition hold
time
600
ns
tSU_STA
Start condition set-up
time
600
ns
tSU_DAT
Data set-up time
100
ns
tHOLD_DAT
Data hold time
0
µs
tSU_STO
Stop condition set-up
time
600
ns
tBUF
Minimum delay
between operations
1.3
µs
Digital interface
VIH
Input high threshold
1.3
V
VIL
Input low threshold
0.6
V
VOL
Output low threshold
0.3
V
Electrical characteristics
STBCFG01
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IIN_IO
I/O pin input current
-10
+10
µA
Dropout voltage is the input-to-output voltage difference at which the output
voltage is 100 mV below its nominal value.
STBCFG01
Operation description
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5 Operation description
5.1 Battery charger
The STBCFG01 integrates a high efficiency battery charger of 1.2 A implementing the
CC/CV charging algorithm for single cell Li-Ion battery powered applications. The switching
frequency can be either 2 MHz or 3 MHz, according to platform noise requirements, and
the inductor value is 1 μH. The charging current sensing resistor is integrated.
Figure 3: Simplified charger architecture
Operation description
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When the battery is deeply discharged (VCELL+ < VTRK, VTRK = 2 V) the device is in trickle
charge mode and charges the battery in linear mode with a low current (ITRK = 45 mA) up to
the trickle charge threshold.
As soon as the battery voltage enters the pre-charge range (VTRK < VCELL+ < VPRE, VPRE = 3
V) the device starts the switch mode charging and increases the charging current up to the
pre-charge current level (IPRE) to make the system voltage rise quickly up to a level which
allows the system to wake up.
The typical value for the pre-charge current is 450 mA but this value can be decreased to
100 mA through the I²C compatible interface.
A 45 minute (typ.) safety timer is active during both trickle charge and pre-charge.
When the battery voltage is above the pre-charge threshold, the STBCFG01 enters fast
charge mode and increases the charging current up to IFAST value. The fast charge
current can be programmed through the I²C compatible interface between 550 mA and 1.2
A in 100 mA steps.
A soft-start function makes the battery current increase smoothly when the charging current
changes.
The constant voltage mode enters when the battery voltage reaches the programmable
floating voltage threshold (VFLOAT, 3.60 V to 4.70 V in 20 mV steps).
In constant voltage mode, the charging current tapers down the termination current
threshold and then the charging process stops. The termination current is programmable
from 50 mA to 300 mA in 25 mA steps.
A 360 minute (typ.) safety timer is active when the fast charge starts.
The charger can be disabled pulling high the charger enable input (CENn) and is
automatically stopped in automatic shutdown conditions (ASD, VDCIN - VBAT < VASD).
Figure 4: CC/CV charging cycle
5.1.1 Input current limit
The STBCFG01 implements a programmable input current limitation to prevent the battery
charger from exceeding DCIN voltage source current capability. The current limit can be
programmed through I²C to the following maximum values: 100 mA, 500 mA, 800 mA, 1.2
A. A “no limit” option is also available.
5.1.2 Dynamic input current limit (DICL)
Independently from the chosen input current limit, a dynamic input current limit loop can
also be enabled through the I²C compatible interface (DICL_en bit). When DICL is active,
an analog loop limits the input current when the input voltage drops to a programmable
threshold (VDICL = 4.0 V to 4.75 V in 250 mV steps).
STBCFG01
Operation description
DocID026474 Rev 3
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Figure 5: DICL activation
When a valid input source is connected to DCIN, DICL is enabled only if the input voltage is
higher than VDICL for a deglitch time (tDICL = 100 ms). The user can check the enabling
status of DICL function reading DICL status bit. Once DICL is enabled it can be disabled
through DICL_en bit.
Figure 6: DICL enable strategy
5.1.3 Automatic recharge
When the charging cycle is over, the device keeps monitoring the battery voltage: if the
voltage drops below the auto-recharge threshold (VRCHG = VFLOAT - 120 mV), a new
charging cycle starts to keep the battery at maximum capacity. The automatic recharge
function can be disabled through I²C.
5.1.4 Battery detection
The battery charger IC features a battery detection function to check if a battery is inserted
before starting the charging cycle and to make sure that charging termination is not
triggered because of a battery disconnection. If the battery is not detected when the input
voltage is valid, the device keeps running the detection sequence until a battery is inserted.
The battery detection result is reported by DET_ok bit. If the battery detection function or
RID comparator detects a battery disconnection, BAT_Fail interrupt is generated. See the
battery detection algorithm flowchart for more details.
Operation description
STBCFG01
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Figure 7: Battery charger flowchart
5.1.5 Battery overvoltage protection
If the battery voltage exceeds the battery overvoltage protection threshold (VBATOVP = VFLOAT
+ 100 mV) for more than tBOVP, the charging cycle stops and an alarm is generated. The
battery overvoltage protection is active only when the charger is enabled. The charger
automatically restarts when the battery voltage falls below the battery overvoltage
protection threshold.
5.2 OTG boost
The STBCFG01's internal bridge can be used in boost configuration to generate USB OTG
VBUS voltage (5 V, 500 mA).
OTG boost generator can be enabled setting the dedicated I²C enable bit (OTG_en)
according to the following conditions:
VDCIN < VINUVLO
CENn = high
VCELL+ > VBATUVLO
OTG boost operation is automatically stopped if the battery voltage falls below VBATUVLO
or if CENn is pulled low during operation.
STBCFG01
Operation description
DocID026474 Rev 3
19/37
The device also features an output overvoltage protection which turns off OTG boost if the
output voltage rises above VBUSOVP. If the overvoltage lasts for more than tVBUSOVP, OTG
boost is disabled and an alarm is generated.
Together with the standard cycle-by-cycle current limit for the inductor peak current, the
STBCFG01 also implements an average battery current limitation to avoid excessive
battery voltage drop during peaks in system current consumption. When the average boost
input current reaches the programmed limit (IBATLIM = 350 mA, 450 mA, 550 mA, 950 mA),
OTG boost is disabled and an alarm is generated.
5.3 LDO regulator
The STBCFG01 integrates a 4.85 V, 50 mA LDO regulator which is active when DCIN
voltage is higher than VINMIN and lower then VINMAX. LDO is also active when the battery is
not connected and in OTG mode, while it is turned off in automatic shutdown conditions
(VDCIN - VCELL+ < VASD). LDO function can be disabled through I²C and its output is
protected against short-circuit.
5.4 Pre-bias
In order to allow proper functionality with input sources not integrating the necessary
minimum load to provide a valid voltage, the STBCFG01 integrates an automatic pre-bias
circuit: if the input voltage (VDCIN) is above the input OVP threshold but lower than the pre-
bias OVP threshold (VINOVP < VDCIN < VINOVP_PB) a pre-bias current is applied to DCIN to
attempt reducing the input voltage down to a valid level. During the charging cycle, if the
pre-bias current has been activated, it is kept on only during trickle charge and taper
charge. The pre-bias current is also turned off in automatic shutdown conditions (ASD).
The pre-bias current is active only if the input voltage is in the activation range for at least
tPBD (5 ms typ.). The pre-bias function can be disabled through I²C.
Figure 8: Pre-bias enable strategy
Operation description
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5.5 Fuel gauge
The voltage mode fuel gauge provides the accurate information about the state of the
Lithium-Ion battery. Battery voltage is constantly monitored to evaluate the state of charge
of battery and open circuit voltage.
At power-up, the fuel gauge algorithm uses the voltage reading to provide a first evaluation
of SOC based on battery modeling data. The evolution of voltage is then used to track the
changes of SOC of battery while cycling. The external software driver performs the
temperature compensation.
Initial accuracy depends on the state of the battery. When the fuel gauge is active the
battery is supposed to be in fully relaxed state. If the battery is not fully relaxed the initial
error in the evaluation of the state of charge is high but converges to lower values while the
battery is being used.
The fuel gauge block can be adapted to different batteries. Programmable parameters are
used to tailor the algorithm to each battery model.
In order to keep the optimal performance and avoid losing information learned during
battery cycling, the user is supposed to save data contained in the device's volatile memory
when power is removed. The same data has to be restored at power-up.
The STBCFG01 also provides programmable alarms to notify low battery voltage and low
SOC conditions.
5.5.1 Operating mode
At start-up and when the battery voltage is below UVLO threshold, the fuel gauge is in
standby mode. This block is active when the battery voltage is above UVLO and GG_RUN
bit has been set through I²C. When the fuel gauge is in standby mode, all register values
are frozen and the algorithm does not run. In active mode, a voltage reading is acquired
every 4 seconds (tSTRB).
5.5.2 Battery connection
When a battery is connected, the device wakes up and attempts reading the battery
voltage before high current loads can change the open circuit voltage. The charging
process is inhibited until the battery voltage reading is completed. If the battery voltage is
too low, the charger is not inhibited to allow the battery to be charged up to a stable voltage
and avoid oscillations.
5.5.3 Low battery alarm
The voltage mode fuel gauge provides low SOC and low battery voltage alarms, which are
notified to the host through the active low open drain interrupt register (IRQn). Both of
alarms can be disabled clearing ALRM_en bit in FG_Mode register.
Low battery voltage threshold and low SOC threshold can be changed writing
ALARM_Voltage and ALARM_SOC registers. The default thresholds are 3.00 V battery
voltage and 1% SOC.
When a low battery voltage condition or a low SOC condition is detected and alarms are
enabled, the corresponding bit in FG_CTRL register is set (ALRM_VBAT or ALRM_SOC)
and IRQn output is pulled low.
ALRM_VBAT and ALRM_SOC bits have to be cleared by the host to release the interrupt
pin (if no other interrupt is active in the device).
STBCFG01
Operation description
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If the alarm is cleared while the alarm condition is still true, the device does not generate
another interrupt: the alarm condition has to disappear and be detected again in order to
generate another interrupt.
At power-up or when the fuel gauge is reset, fuel gauge alarms are enabled and alarms are
generated after the first OCV reading and SOC estimation (if the alarm condition is true).
5.5.4 Battery swap
When the battery is removed from the system, the fuel gauge is reset to avoid providing
wrong battery information if a different battery is inserted.
In order to detect battery disconnection, the STBCFG01 monitors both the battery voltage
(VCELL+) and the voltage on RID pin connected to the battery identification resistor.
All volatile memory information is always lost when the battery voltage falls below POR
threshold.
Figure 9: Battery swap detection
5.6 Thermal shutdown
In any working condition, if the die temperature reaches the thermal shutdown threshold
(TSD = 165 °C typ.) the device enters shutdown mode: the bridge and LDO output turn off.
The fuel gauge keeps working normally. The operation is automatically restored when the
temperature falls back into the valid range. Safety timers are reset when a thermal
shutdown is triggered.
Operation description
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5.7 Shutdown mode
When SHDN pin is tied high the device enters shutdown mode. In this mode, the switching
converter turns off and it cannot be used neither in charging mode nor OTG boost mode.
LDO and fuel gauge functionality are not affected by SHDN pin.
5.8 Watchdog
A watchdog timer function can be enabled to reset the programmable register values to
power-on reset values if no I²C acknowledgments are generated for more than 45 seconds.
This function is normally disabled.
5.9 Alarms
The STBCFG01 provides an open drain active low interrupt output (IRQn) to notify the
application processor about abnormal operating conditions or generic events. The following
register types check the status of alarms and control the device:
Interrupt enable
Interrupt latch
The interrupt enable registers enable the propagation of alarms to the interrupt pin (IRQn).
The interrupt is generated (IRQn pulled low) on a rising edge of the interrupt latch bits
(assuming that the corresponding enable bit has been set).
The interrupt latch registers show the alarm conditions, which generate the interrupt.
Although the alarm condition is no longer active, once each latch register bit is set, it stays
high until the register is updated. Interrupt latch registers are updated by writing 0 to their
bits: if the alarm condition is still active the bit is kept to 1 (new interrupt is not generated); if
the alarm condition is no more active the bit is cleared. This update method assures that no
further rising edge on the latch bit is generated for alarms which have already been
signaled before the update operation. In order to release IRQn line after an interrupt
generated by the charger/OTG, the host processor has to write 0 to IRQ_CLR bit in
CHG_Cfg2 register and then back 1. The fuel gauge generated alarms share the same
enable bit (ALRM_en).
The following conditions generate an interrupt signal:
DCIN UVLO
DCIN OVP
ASD condition
Pre-charge timer expiration
Fast charge timer expiration
Watchdog timer expiration
Battery overvoltage protection (charger)
End of charge
Battery undervoltage lockout (OTG boost)
VBUS overvoltage protection (OTG boost)
Average current limit reached (OTG boost, IBATLIM)
OTG output short-circuit; thermal shutdown
Low battery voltage (fuel gauge)
Low SOC (fuel gauge)
STBCFG01
I²C compatible interface registers
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6 I²C compatible interface registers
The STBCFG01 can be monitored and controlled using the I²C compatible communication
interface. The 7-bit device slave address is 1110001BIN. The table below shows the register
map.
Table 6: Register map
Name
Address
POR value
R/W
Fuel gauge
FG_Mode
00h
19h
R/W
FG_CTRL
01h
15h
R/W
SOC
02h-03h
0000h
R/W
VBAT
08h-09h
0000h
R
OCV
0Dh-0Eh
0000h
R
VM_CNF
11h-12h
0141h
R/W
ALARM_SOC
13h
02h
R/W
ALARM_Voltage
14h
AAh
R/W
REG_ID
18h
14h
R
RAM0…RAM15
20h…2Fh
-
R/W
OCV_ADJ
30h…3Fh
-
R/W
LUT
5Dh…8Ch
-
R/W
Charger/OTG
CHG_Cfg1
90h
00h
R/W
CHG_Cfg2
91h
62h
R/W
CHG_Cfg3
92h
61h
R/W
CHG_Cfg4
93h
4Fh
R/W
CHG_Cfg5_OTG_Status
94h
06h
R/W
CHG_Status1
95h
00h
R
CHG_Status2
96h
C0h
R
Int_Enable_1
97h
00h
R/W
Int_Enable_2
98h
00h
R/W
Int_Latch_1
99h
00h
R/W
Int_Latch_2
9Ah
00h
R/W
I²C compatible interface registers
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6.1 Fuel gauge registers
Table 7: Fuel gauge mode register (address: 00h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
-
OTG_en
LPM_dis
GG_RUN
ALRM_en
-
-
-
19h
R/W
ALRM_en: fuel gauge alarm enable
0: disabled
1: enabled (default)
GG_RUN: fuel gauge operative mode
0: standby (default). Registers are frozen, fuel gauge in standby
1: running
LPM_dis: low power mode disable (set this bit to program battery charger/OTG
configuration registers and enable OTG function when USB input is not plugged and
GG_RUN = 0)
0: low power mode enabled (default)
1: low power mode disabled
OTG_en: OTG boost enable bit
0: disabled (default)
1: enabled
Table 8: FG_CTRL register (address: 01h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
-
ALRM_VBAT
ALRM_SOC
POR_Det
BAT_Fail
-
IODATA
15h
R/W
IODATA: IRQn pin status
Read:
0: IRQn pin is low
1: IRQn pin is high
Write:
0: forces IRQn pin low
1: IRQn pin is driven by interrupt logic
BAT_Fail: battery removal or battery UVLO detection bit. Write 0 to clear
0: battery connected
1: battery removed or UVLO
POR_Det: power-on reset detection bit. Write 1 to force a soft reset (self-clearing)
0: no POR event occurred
1: POR event occurred
ALRM_SOC: low SOC alarm
0: SOC OK
1: low SOC
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I²C compatible interface registers
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Write this bit to 0 to clear the alarm. If the alarm condition is still active a new
alarm is triggered only on the following rising edge of the alarm condition (the
alarm condition has to disappear and then appear again).
ALRM_VBAT: low battery voltage alarm
0: battery voltage above threshold
1: low battery voltage
Write this bit to 0 to clear the alarm. If the alarm condition is still active a new
alarm is triggered only on the following rising edge of the alarm condition (the
alarm condition has to disappear and then appear again).
Table 9: SOC register LSB (register address: 02h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
SOC[7:0]
00h
R/W
Table 10: SOC register MSB (register address: 03h)
b15
B14
b13
b12
b11
b10
b9
b8
POR
R/W
SOC[15:8]
00h
R/W
SOC register LSb: 1/512% SOC
Table 11: VBAT register LSB (register address: 08h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
VBAT[7:0]
00h
R
Table 12: VBAT register MSB (register address: 09h)
b15
B14
b13
b12
b11
b10
b9
b8
POR
R/W
Reserved
VBAT[10:8]
00h
R
VBAT register LSb: 2.69 mV
Table 13: OCV register LSB (register address: 0Dh)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
OCV[7:0]
00h
R
Table 14: OCV register MSB (register address: 0Eh)
b15
B14
b13
b12
b11
b10
b9
b8
POR
R/W
Reserved
OCV[12:8]
00h
R
OCV register LSb: 0.67 mV
Table 15: VM_CNF register LSB (register address: 11h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
VM_CNF[7:0]
41h
R/W
I²C compatible interface registers
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Table 16: ALARM_SOC register (address: 13h)
b15
B14
b13
b12
b11
b10
b9
b8
POR
R/W
VM_CNF[15:8]
01h
R
ALARM_SOC register LSb: 0.5%
Table 17: ALARM_Voltage register (address: 14h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
ALARM_Voltage
AAh
R/W
ALARM_Voltage register LSb: 21.49 mV
6.2 Charger/OTG/LDO registers
Table 18: CHG_Cfg1 register
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
ITERM
IPRE
ifast
40h
R/W
IFAST: fast charge current
Offset: 550 mA
LSb: 100 mA
Range: 550 mA to 1250 mA
Default: 550 mA (000)
IPRE: pre-charge current
0: 450 mA (default)
1: 100 mA
ITERM: termination current
Offset: 50 mA
LSb: 25 mA
Range: 50 mA to 300 mA
Default: 150 mA (0100)
Values 1011 through 1111: reserved
Table 19: CHG_Cfg2 register (address: 91h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
IRQ_CLR
ARCHG
VFLOAT
C0h
R/W
VFLOAT: floating voltage
Offset: 3.52 V
LSb: 20 mV
Range: 3.52 V to 4.78 V
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Default: 3.52 V (000000)
ARCHG: automatic recharge enable
0: disabled
1: enabled (default)
IRQ_CLR: clear interrupt latch
0: clear interrupt latch
1: propagate interrupt (default)
Table 20: CHG_Cfg3 register (address: 92h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
IBATLIM
VDICL
DICL_en
Iin_lim
61h
R/W
Iin_lim: input current limit (DCIN)
000: max.100 mA
001: max.
500 mA (default)
010: max. 800 mA
011: max. 1.2 A
100: no limit
Values 101 through 111: reserved
DICL_en: dynamic input current limit enable
0: disabled (default)
1: enabled
VDICL: dynamic input current limit threshold
00: 4.00 V
01: 4.25 V
10: 4.50 V (default)
11: 4.75 V
IBATLIM: OTG average battery current limit
00: 350 mA
01: 450 mA (default)
10: 550 mA
11: 950 mA
I²C compatible interface registers
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Table 21: CHG_Cfg4 register format (register address: 93h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
RID_STAT
LDO_en
LDO_UVLO_th
WD
PreB_en
THRML
TFAST
TPRE
4Fh
R/W
TPRE: pre-charge timer enable
0: disabled
1: enabled (default)
TFAST: fast charge timer enable
0: disabled
1: enabled (default)
THRML: thermal loop enable (this bit can be masked through OTP)
0: disabled
1: enabled (default)
PreB_en: pre-bias function enable
0: disabled
1:enabled (default)
WD: watchdog timer function enable
0: disabled (default)
1: enabled
LDO_UVLO_th: LDO UVLO threshold
0:3.6 V rising, 3.5 V falling (default)
1: 4.75 V rising, 4.65 V falling
LDO_en: LDO output enable
0: LDO output disabled
1:LDO output enabled (default)
RID_STAT: RID status (read only)
0: RID connected
1: RID disconnected
Table 22: CHG_Cfg5_OTG_Status register format (register address: 94h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
BST_SH
BST_status
-
DICHG_adj
FSW
CHG_rst
06h
R/W
b0, b1, b2 are R/W; b4, b5, b6, b7 are read status bit only.
CHG_rst: charger reset, all charger registers to POR value. Self-clearing.
0: no action (default)
1: reset charger
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I²C compatible interface registers
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FSW: switching frequency. The switching frequency can be changed only when the device
doesn’t switch. SHDN input should be pulled high before modifying this setting.
0: 2 MHz
1: 3 MHz (default)
DICHG_adj: dynamic charging current adjustment enable (for soft-current transitions)
0: disabled
1: enabled (default)
BST_status: OTG boost status
000: idle
001: wait soft-start
010: linear soft-start
011: switching soft-start
100: frequency ramp-up
101: OTG_run
110: PMOS-off
111: shutdown
BST_SH: OTG boost output short at beginning
0: no short detected (default)
1: short detected
Table 23: CHG_Status1 register format (register address: 95h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
CHG_status
PreB_st
PreB
Alarm
00h
R
Alarm: alarm state
0: no alarm is active
1: alarm condition detected
PreB: pre-bias current activation
0: pre-bias current has not been activated
1: pre-bias current has been activated (VINOVP < VDCIN < VINOVP_PB for more than tPBD)
PreB_st: pre-bias current sink status
0: pre-bias current sink is currently off
1: pre-bias current sink is currently on
CHG_status: charger status
00000: idle
00001: trickle charge
00010: pre-charge
00011: fast charge
00100: taper charge (constant voltage)
00101: charge done (termination)
00110: boost on
00111: shutdown
01000: battery detection running
I²C compatible interface registers
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Table 24: CHG_Status2 register format (register address: 96h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
-
-
-
-
-
DET_ok
DET_run
DICL
C0h
R
DICL: dynamic input current limit activation
0: not active
1: active
DET_run: charger battery detection status
0: battery detection does not run
1: battery detection runs
DET_Fail: charger battery detection result
0: battery connected
1: battery not connected
Table 25: Int_Enable_1 register format (register address: 97h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
EOC
Bat_OVP
WD
Fast_TMR
Pre_TMR
ASD
IN_OVP
IN_UVLO
00h
R
For all bits
Write 1 to propagate the event to IRQn
Write 0 to mask the event (default)
IN_UVLO: charger input voltage UVLO
IN_OVP: charger input voltage OVP
ASD: automatic shutdown condition
Pre_TMR: pre-charge timer expiration
Fast_TMR: fast charge timer expiration
WD: watchdog timer expiration
Bat_OVP: battery overvoltage protection
EOC: end-of-charge (termination current reached)
Table 26: Int_Enable_2 register format (register address: 98h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
BAT_Fail
CHG_ON
-
OTG_short
Ibat_Lim
VBus_OVP
TSHDN
Bat_UVLO
00h
R/W
For all bits:
Write 1 to propagate the event to IRQn
Write 0 to mask the event (default)
Bat_UVLO: battery UVLO (OTG)
TSHDN: thermal shutdown
VBus_OVP: OTG boost output OVP
Ibat_Lim: OTG battery average current limit
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I²C compatible interface registers
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OTG_short: OTG output short-circuit
CHG_ON: charging started
BAT_Fail: battery fail
Table 27: Int_Latch_1 register format (register address: 99h)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
EOC
Bat_OVP
WD
Fast_TMR
Pre_TMR
ASD
IN_OVP
IN_UVLO
00h
R/W
This register is cleared upon read operation.
IN_UVLO: charger input voltage UVLO
0: charger input voltage is above UVLO
1: charger input voltage is below UVLO
IN_OVP: charger input voltage OVP
0: charger input voltage is below OVP
1: charger input voltage is above OVP
ASD: automatic shutdown condition
0: charger input voltage above the automatic shutdown threshold
1: charger input voltage below the automatic shutdown threshold
Pre_TMR: pre-charge timer expiration (has to be cleared by the host)
0: pre-charge timer running
1: pre-charge timer expired
Fast_TMR: fast charge timer expiration (has to be cleared by the host)
0: fast charge timer running
1: fast charge timer expired
WD: watchdog timer expiration (has to be cleared by the host)
0: watchdog timer running
1: watchdog timer expired
Bat_OVP: battery overvoltage protection
0: battery voltage below OVP threshold during charging
1: battery voltage above OVP threshold during charging
EOC: end-of-charge (termination current reached)
0: termination current not reached
1: termination current reached
I²C compatible interface registers
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Table 28: Int_Latch_2 register format (register address: 9Ah)
b7
b6
b5
b4
b3
b2
b1
b0
POR
R/W
BAT_Fail
CHG_ON
TSHDN_LDO
OTG_short
Ibat_Lim
VBus_OVP
TSHDN
Bat_UVLO
00h
R/W
Write 0 to update these register bits.
Bat_UVLO: battery UVLO (OTG)
0: battery voltage above UVLO threshold during boost operation
1: battery voltage below UVLO threshold during boost operation
TSHDN: thermal shutdown
0: device in normal operation conditions
1: device in thermal shutdown
VBus_OVP: OTG boost output OVP
0: OTG boost output voltage below OVP threshold
1: OTG boost output voltage above OVP threshold
Ibat_Lim: OTG battery average current limit (has to be cleared by the host)
0: average battery current limit not reached during OTG boost operation
1: average battery current limit reached during OTG boost operation
OTG_short: OTG output short-circuit
0: OTG output short-circuit condition not detected
1: OTG output short-circuit condition detected
TSHDN_LDO: LDO thermal shutdown
0: LDO in normal operation conditions
1: LDO in thermal shutdown
CHG_ON: charger cycle start
0: charging cycle not active
1: charging cycle started
BAT_Fail: battery status (from state machine or RID)
0: battery connected/good battery
1: battery disconnected/not good
STBCFG01
Package information
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7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 Flip Chip 25 (2.3x2.2 mm) option H package information
Figure 10: Flip Chip 25 (2.3x 2.2 mm) option H package outline
Package information
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Table 29: Flip Chip 25 (2.3 x 2.2 mm) option H package mechanical data
Dim.
mm
Min.
Typ.
Max.
A
0.495
0.55
0.605
A1
0.17
0.20
0.23
A2
0.275
0.30
0.325
b
0.23
0.26
0.29
D
2.25
2.28
2.31
D1
1.6
E
2.16
2.19
2.22
E1
1.6
e
0.4
fD
0.33
0.34
0.35
fE
0.285
0.295
0.305
ccc
0.075
$
0.05
Figure 11: Flip Chip 25 (2.3 x2.2 mm) option H recommended footprint
STBCFG01
Ordering information
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8 Ordering information
Table 30: Ordering information
Order code
Package
Packing
STBCFG01JR
Flip Chip 25
(2.3 x 2.2 mm)
Tape and reel
Revision history
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9 Revision history
Table 31: Document revision history
Date
Revision
Changes
10-Jun-2014
1
Initial release.
09-Dec-2014
2
Added the table titled "Typical external components".
28-Apr-2016
3
Modified Table 10: "SOC register MSB (register
address: 03h)".
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