
www.irf.com 1
8/5/05
IRF6645
DirectFET Power MOSFET
DirectFET ISOMETRIC
SJ
PD - 97006
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
Fig 1. Typical On-Resistance vs. Gate Voltage
Typical values (unless otherwise specified)
Description
The IRF6645 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the
lowest on-state resistance in a package that has the footprint of an Micro8 and only 0.7 mm profile. The DirectFET package is compatible with
existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques,
when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided
cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6645 is optimized for primary side bridge topologies in isolated DC-DC applications, for wide range universal input Telecom applications
(36V - 75V), and for secondary side synchronous rectification in regulated DC-DC topologies. The reduced total losses in the device coupled
with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliability improvements,
and makes this device ideal for high performance isolated DC-DC converters.
l RoHs Compliant Containing No Lead and Bromide
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Ultra Low Package Inductance
l Optimized for High Frequency Switching
lIdeal for High Performance Isolated Converter
Primary Switch Socket
l Optimized for Synchronous Rectification
l Low Conduction Losses
l Compatible with existing Surface Mount Techniques
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 5.0mH, RG = 25Ω, IAS = 3.4A.
Notes:
Fig 2. Typical Total Gate Charge vs. Gate-to-Source Voltage
Absolute Maximum Ratin
s
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V
e
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V
e
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
f
IDM Pulsed Drain Current
g
EAS Single Pulse Avalanche Energy
h
mJ
IAR Avalanche Current
g
A
29
Max.
4.5
25
45
±20
100
5.7
3.4
4 6 8 10 12 14 16
VGS, Gate-to-Source Voltage (V)
20
30
40
50
60
70
80
Typical RDS(on) (
mΩ)
TJ = 25°C
TJ = 125°C
ID = 3.4A
0481216
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 80V
VDS= 50V
ID= 3.4A
VDSS VGS RDS(on)
100V max ±20V max 28mΩ@ 10V
Qg tot Qgd Vgs(th)
14nC 4.8nC 4.0V
SH SJ SP MZ MN