www.irf.com 1
8/5/05
IRF6645
DirectFET Power MOSFET
DirectFET ISOMETRIC
SJ
PD - 97006
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
Fig 1. Typical On-Resistance vs. Gate Voltage
Typical values (unless otherwise specified)
Description
The IRF6645 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the
lowest on-state resistance in a package that has the footprint of an Micro8 and only 0.7 mm profile. The DirectFET package is compatible with
existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques,
when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided
cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6645 is optimized for primary side bridge topologies in isolated DC-DC applications, for wide range universal input Telecom applications
(36V - 75V), and for secondary side synchronous rectification in regulated DC-DC topologies. The reduced total losses in the device coupled
with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliability improvements,
and makes this device ideal for high performance isolated DC-DC converters.
l RoHs Compliant Containing No Lead and Bromide
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Ultra Low Package Inductance
l Optimized for High Frequency Switching
lIdeal for High Performance Isolated Converter
Primary Switch Socket
l Optimized for Synchronous Rectification
l Low Conduction Losses
l Compatible with existing Surface Mount Techniques
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 5.0mH, RG = 25, IAS = 3.4A.
Notes:
Fig 2. Typical Total Gate Charge vs. Gate-to-Source Voltage
Absolute Maximum Ratin
g
s
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V
e
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V
e
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
f
IDM Pulsed Drain Current
g
EAS Single Pulse Avalanche Energy
h
mJ
IAR Avalanche Current
g
A
29
Max.
4.5
25
45
±20
100
5.7
3.4
4 6 8 10 12 14 16
VGS, Gate-to-Source Voltage (V)
20
30
40
50
60
70
80
Typical RDS(on) (
m)
TJ = 25°C
TJ = 125°C
ID = 3.4A
0481216
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 80V
VDS= 50V
ID= 3.4A
VDSS VGS RDS(on)
100V max ±20V max 28m@ 10V
Qg tot Qgd Vgs(th)
14nC 4.8nC 4.0V
SH SJ SP MZ MN
IRF6645
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Notes:
Pulse width 400µs; duty cycle 2%.
Repetitive rating; pulse width limited by max. junction temperature.
S
D
G
Electrical Characteristic @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 100 ––– ––– V
∆ΒVDSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.12 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 28 35 m
VGS(th) Gate Threshold Voltage 3.0 ––– 4.9 V
VGS(th)/TJGate Threshold Voltage Coefficient ––– -12 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 7.4 ––– ––– S
QgTotal Gate Charge ––– 14 20
Qgs1 Pre-Vth Gate-to-Source Charge ––– 3.1 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.8 ––– nC
Qgd Gate-to-Drain Charge ––– 4.8 7.2
Qgodr Gate Charge Overdrive ––– 5.3 ––– See Fig. 15
Qsw Switch Charge (Qgs2 + Qgd)––– 5.6 –––
Qoss Output Charge ––– 7.2 ––– nC
RGGate Resistance ––– 1.0 –––
td(on) Turn-On Delay Time ––– 9.2 –––
trRise Time ––– 5.0 –––
td(off) Turn-Off Delay Time ––– 18 ––– ns
tfFall Time ––– 5.1 –––
Ciss Input Capacitance ––– 890 –––
Coss Output Capacitance ––– 180 ––– pF
Crss Reverse Transfer Capacitance ––– 40 –––
Coss Output Capacitance ––– 870 –––
Coss Output Capacitance ––– 100 –––
Diode Characteristics
Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 25
(Body Diode) A
ISM Pulsed Source Current ––– ––– 45
(Body Diode)d
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 31 47 ns
Qrr Reverse Recovery Charge ––– 40 60 nC
ID = 3.4A
VDS = 80V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VGS = 10V
VDS = 10V, ID = 3.4A
VDS = 50V
TJ = 25°C, IF = 3.4A, VDD = 50V
di/dt = 100A/µs c
TJ = 25°C, IS = 3.4A, VGS = 0V c
showing the
integral reverse
p-n junction diode.
VDS = VGS, ID = 50µA
VDS = 100V, VGS = 0V
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 5.7A c
VDS = 16V, VGS = 0V
VDD = 50V, VGS = 10Vc
VGS = 0V
ƒ = 1.0MHz
ID = 3.4A
MOSFET symbol
RG=6.2
VDS = 25V
Conditions
VGS = 0V, VDS = 80V, f=1.0MHz
VGS = 0V, VDS = 1.0V, f=1.0MHz
IRF6645
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1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
Thermal Response ( Z
thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = Pdm x Zthja + Ta
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Surface mounted on 1 in. square Cu
board (still air).
Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
Mounted to a PCB with
small clip heatsink (still air)
Surface mounted on 1 in. square Cu, steady state.
Used double sided cooling , mounting pad.
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
Notes:
TC measured with thermocouple incontact with top (Drain) of part.
Rθ is measured at TJ of approximately 90°C.
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci= τi/Ri
Ci= τi/Ri
τ4
τ4
R4
R4
τC
τC
τ5
τ5
R5
R5
Ri (°C/W) τi (sec)
0.6677 0.000066
1.0463 0.000896
1.5612 0.004386
29.2822 0.686180
25.4550 32
A
Absolute Maximum Ratin
g
s
Parameter Units
PD @TA = 25°C Power Dissipation
c
W
PD @TA = 70°C Power Dissipation
c
PD @TC = 25°C Power Dissipation
f
TP Peak Soldering Temperature °C
TJ Operating Junction and
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJA Junction-to-Ambient
cg
––– 58
RθJA Junction-to-Ambient
dg
12.5 –––
RθJA Junction-to-Ambient
eg
20 ––– °C/W
RθJC Junction-to-Case
fg
––– 3.0
RθJ-PCB Junction-to-PCB Mounted 1.0 –––
270
-40 to + 150
Max.
42
3.0
1.4
IRF6645
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Fig 5. Typical Output Characteristics
Fig 4. Typical Output Characteristics
Fig 6. Typical Transfer Characteristics Fig 7. Normalized On-Resistance vs. Temperature
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage Fig 9. Typical On-Resistance vs. Drain Current
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 25°C
6.0V
VGS
TOP 15V
10V
8.0V
7.0V
BOTTOM 6.0V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 150°C
6.0V
VGS
TOP 15V
10V
8.0V
7.0V
BOTTOM 6.0V
4.0 5.0 6.0 7.0 8.0
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current
(Α)
TJ = 150°C
TJ = 25°C
TJ = -40°C
VDS = 10V
60µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
Typical RDS(on) (Normalized)
ID = 5.7A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
010 20 30 40 50
ID, Drain Current (A)
20
30
40
50
60
Typical RDS(on) (m)
TA= 25°C
VGS = 7.0V
VGS = 8.0V
VGS = 10V
VGS = 15V
IRF6645
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Fig 13. Typical Threshold Voltage vs.
Junction Temperature
Fig 12. Maximum Drain Current vs. Ambient Temperature
Fig 10. Typical Source-Drain Diode Forward Voltage Fig11. Maximum Safe Operating Area
Fig 14. Maximum Avalanche Energy vs. Drain Current
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VSD, Source-to-Drain Voltage (V)
0.1
1.0
10.0
100.0
ISD, Reverse Drain Current (A)
VGS = 0V
TJ = 150°C
TJ = 25°C
TJ = -40°C
25 50 75 100 125 150
Starting TJ, Junction Temperature (°C)
0
20
40
60
80
100
120
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 1.5A
2.4A
BOTTOM 3.4A
0.1 1.0 10.0 100.0 1000.0
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TA = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
25 50 75 100 125 150
TJ , Ambient Temperature (°C)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
ID , Drain Current (A)
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
ID = 1.0mA
ID = 250µA
ID = 50µA
IRF6645
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D.U.T. VDS
ID
IG
3mA
VGS
.3µF
50K
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 15a. Gate Charge Test Circuit Fig 15b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 16c. Unclamped Inductive Waveforms
tp
V
(BR)DSS
I
AS
Fig 16b. Unclamped Inductive Test Circuit
Fig 17b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
Fig 17a. Switching Time Test Circuit
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VDS
Pulse Width 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
VGS
IRF6645
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DirectFET Substrate and PCB Layout, SJ Outline
(Small Size Can, J-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
Fig 18. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
Inductor Current
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
di/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
+
-
+
+
+
-
-
-
RGVDD
D.U.T
G = GATE
D = DRAIN
S = SOURCE
G
S
D
D
D
D
S
IRF6645
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DirectFET Outline Dimension, SJ Outline
(Small Size Can, J-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DirectFET Part Marking
MIN
0.187
0.146
0.108
0.014
0.023
0.023
0.027
0.027
0.039
0.090
0.019
0.001
0.003
MAX
4.85
3.95
2.85
0.45
0.62
0.62
0.72
0.72
1.02
2.32
0.58
0.08
0.17
MIN
4.75
3.70
2.75
0.35
0.58
0.58
0.68
0.68
0.98
2.28
0.48
0.03
0.08
CODE
A
B
C
D
E
F
G
H
K
L
M
N
P
MAX
0.191
0.156
0.112
0.018
0.024
0.024
0.028
0.028
0.040
0.091
0.023
0.003
0.007
DIMENSIONS
METRIC IMPERIAL
IRF6645
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DirectFET Tape & Reel Dimension (Showing component orientation).
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/05
REEL DIMENSIONS
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6645). For 1000 parts on 7" reel,
order IRF6645TR1
STANDARD OPTION (QTY 4800)
MIN
330.0
20.2
12.8
1.5
100.0
N.C
12.4
11.9
CODE
A
B
C
D
E
F
G
H
MAX
N.C
N.C
13.2
N.C
N.C
18.4
14.4
15.4
MIN
12.992
0.795
0.504
0.059
3.937
N.C
0.488
0.469
MAX
N.C
N.C
0.520
N.C
N.C
0.724
0.567
0.606
METRIC IMPERIAL
TR1 OPTION (QTY 1000)
IMPERIAL
MIN
6.9
0.75
0.53
0.059
2.31
N.C
0.47
0.47
MAX
N.C
N.C
12.8
N.C
N.C
13.50
12.01
12.01
MIN
177.77
19.06
13.5
1.5
58.72
N.C
11.9
11.9
METRIC
MAX
N.C
N.C
0.50
N.C
N.C
0.53
N.C
N.C
MIN
7.90
3.90
11.90
5.45
4.00
5.00
1.50
1.50
NOTE: CONTROLLING
DIMENSIONS IN MM MAX
8.10
4.10
12.30
5.55
4.20
5.20
N.C
1.60
MAX
0.319
0.161
0.484
0.219
0.165
0.205
N.C
0.063
DIMENSIONS
METRIC IMPERIAL
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/