FQD1N60 - Fairchild Semiconductor

April 2000

Rev. A, April 2000

FQD1N60 / FQU1N60

QFET

QFETQFET

QFETTM

FQD1N60 / FQU1N60

600V N-Ch annel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for high efficiency switch mode power supply.

Features

• 1.0A, 600V, RDS(on) = 11.5Ω @VGS = 10 V

• Low gate charge ( typical 5.0 nC)

• Low Crss ( typical 3.0 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratin gs TC = 25°C unless otherwise noted

Thermal Characteri stics

Symbol Parameter FQD1N60 / FQU1N60 Units

VDSS Drain-Source Voltage 600 V

IDDrain Current - Continuous (TC = 25°C) 1.0 A

- Continuous (TC = 100°C) 0.63 A

IDM Drain Current - Pulsed (Note 1) 4.0 A

VGSS Gate-Source Voltage ±30 V

EAS Single Pulsed Avalanche Energy (Note 2) 50 mJ

IAR Avalanche Current (Note 1) 1.0 A

EAR Repetitive Avalanche Energy (Note 1) 3.0 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns

PDPower Dissipation (TA = 25°C) * 2.5 W

Power Dissipation (TC = 25°C) 30 W

- Derate above 25°C 0.24 W/°C

TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C

TLMaximum lead temperature for soldering purposes,

1/8from case for 5 seconds 300 °C

Symbol Parameter Typ Max Units

RθJC Thermal Resistance, Junction-to-Case -- 4.17 °CW

RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °CW

RθJA Thermal Resistance, Junction-to-Ambient -- 110 °CW

* When mounted on the minimum pad size recommended (PCB Mount)

I-PAK

FQU Series

D-P AK

FQD Series GS

FQD1N60 / FQU1N60

(Note 4)

(Note 4, 5)

(Note 4)

Rev. A, April 2000

Electrical CharacteristicsTC = 25°C unless otherwise noted

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 92mH, IAS = 1.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD  1.2A, di/dt  200A/µs, VDD  BVDSS, Starting TJ = 25°C

4. Pulse Test : Pulse width 300µs, Duty cycle 2%

5. Essentially independent of operating temperature

Symbol Parame ter Test Condit i ons Min Typ Max Units

Off Characteristics

BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA600 -- -- V

∆BVDSS

/ ∆TJ

Breakdown Vo ltage Temperature

Coefficient ID = 250 µA, Referenced to 25°C -- 0.4 -- V/°C

IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V -- -- 10 µA

VDS = 480 V, TC = 125°C -- -- 100 µA

IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA

IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteri st ics

VGS(th) Gate Threshold Volt age VDS = VGS, ID = 250 µA3.0 -- 5.0 V

RDS(on) Static Drain-Source

On-Resistance VGS = 10 V , ID = 0.5 A -- 9.3 11.5 Ω

gFS Forward Transconductance VDS = 50 V, ID = 0.5 A -- 0.83 -- S

Dynamic Characteristics

Ciss Input Capacitance VDS = 25 V, VGS = 0 V,

f = 1.0 MHz

-- 120 150 pF

Coss Output Capacitance -- 20 25 pF

Crss Reverse Transfer Capacit ance -- 3 4 pF

Switching Characteristics

td(on) Turn-On Delay T ime VDD = 300 V, ID = 1.2 A,

RG = 25 Ω

-- 5 20 ns

trTurn-On Rise Time -- 25 60 ns

td(off) Turn-Off De l a y Time -- 7 25 ns

tfTurn -Off Fall Time -- 2 5 60 ns

QgTotal Gate Ch arge VDS = 480 V, ID = 1.2 A,

VGS = 10 V

-- 5 6 nC

Qgs Gate-Source Charge -- 1 -- nC

Qgd Gate-Drain Charge -- 2.6 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

ISMaximum Continuous Drain-Source Diode Forward Current -- -- 1.0 A

ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 4.0 A

VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.0 A -- -- 1.4 V

trr Reverse Recovery Time VGS = 0 V, I S = 1.2 A,

dIF / dt = 100 A/µs -- 160 -- ns

Qrr Reverse Recovery Charge -- 0.3 -- µC

FQD1N60 / FQU1N60

Rev. A, April 2000

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

10-1

100

25

150

 No te s :

1. V GS = 0 V

2. 250

s Pulse Test

IDR , Re verse Drain Cu rrent [A]

VSD , Source-Drain Voltage [V]

246810

10-1

100



Notes :

1. V DS = 50V

2. 2 5 0 

s Pulse Te st

-55

150

25

ID , Drain Current [A]

VGS , Gate-Source Voltage [V]

10-1 100101

10-2

10-1

100

VGS

T op : 1 5 .0 V

10 .0 V

8.0 V

7.0 V

6.5 V

6.0 V

B otto m : 5.5 V



N o te s :

1. 250

s Pulse Test

2. T C = 25

ID, D ra in C u rre n t [A ]

VDS, Drain-Source Voltage [V]

012345

VDS = 300V

VDS = 120V

VDS = 480V

 No te : I D = 1.2 A

VGS, Gate-Source Voltage [V]

QG, To ta l G a te C h a rge [n C]

10-1 100101

100

150

200 Ciss = C gs + C gd (C ds = shorted)

Coss = Cds + Cgd

Crss = Cgd

 No te s :

1. V GS = 0 V

2. f = 1 MHz

Crss

Coss

Ciss

Capacitance [pF]

VDS, Drain-Source Voltage [V]

0.0 0.5 1.0 1.5 2.0 2.5

VGS = 20V

VGS = 10V

 No te : T J = 25

RDS(ON) [],

Drain-Source On-R esistance

ID, Drain Current [A]

Typical Characteristics

Figure 5. Capacitanc e Ch a racteristics Figure 6. Gate Charge C haracteris tics

Figu re 3. On-R esistan ce Variation vs.

Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage

Variation vs. Source Current

and Temperature

Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character i st ics

FQD1N60 / FQU1N60

Rev. A, April 2000

10-5 10-4 10-3 10-2 10-1 100101

10-1

100 Note s :

1 . Z JC(t) = 4.17 /W Max .

2 . D u ty F a c to r, D = t1/t2

3 . T JM - T C = PDM * Z JC(t)

single p ulse

D=0.5

0.02

0.2

0.05

0.1

0.01

ZJC

(t), Therm al Response

t1, S qu a re W a ve P u lse D u ra tio n [se c]

25 50 75 100 125 150

0.00

0.25

0.50

0.75

1.00

ID, Drain Current [A]

TC, Case Temperature [

]

100101102103

10-2

10-1

100

101

DC 10 ms

1 ms 100 µs

Operation in This Area

is Limited by R DS(on)

 Notes :

1. TC = 25 oC

2. TJ = 150 oC

3. Single Pulse

ID, Dra in Cur re nt [A ]

VDS, Drain-Source Voltage [V]

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0



Notes :

1. V GS = 10 V

2. ID = 0.6 A

RDS(ON) , (Normalized)

Drain-Source O n-Resistance

TJ, Junction Tem perature [oC]

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2



N o te s :

1. V GS = 0 V

2. ID = 250 

BV DSS , (No r ma liz e d )

D rain-Source Breakdo wn V oltage

TJ, Junction Te m perature [oC]

Typical Characteristics (Continued)

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

Figu re 7. Breakdown Voltag e Variat i on

vs. Temperature Figure 8. On-Resistance Variation

vs. Temperature

Figure 11. Tr ansient Thermal Response Curve

PDM

FQD1N60 / FQU1N60

Rev. A, April 2000

Gate Charge Test Circuit & Waveform

Resist iv e Sw itc h ing Tes t Ci rcuit & Waveforms

Unclamped Inductive Switching Test Circuit & Waveforms

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K

200nF

12V

Same Type

as DUT

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K

200nF

12V

Same Type

as DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

EAS =LI

AS2

----

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

FQD1N60 / FQU1N60

Rev. A, April 2000

Peak Diode Recove ry dv/dt Test Circuit & Waveforms

DUT

VDS

Driver

RGSame Typ e

as DUT

VGS • dv/dt controlled by RG

•I

SD controlled by pulse period

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

DUT

VDS

Driver

RGSame Typ e

as DUT

VGS • dv/dt controlled by RG

•I

SD controlled by pulse period

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

FQD1N60 / FQU1N60

Rev. A, April 2000

Package Dimensions

6.60

±0.20

2.30

±0.10

0.50

±0.10

5.34

±0.30

0.70

±0.20

0.60

±0.20

0.80

±0.20

9.50

±0.30

6.10

±0.20

2.70

±0.20

9.50

±0.30

6.10

±0.20

2.70

±0.20

MIN0.55

0.76

±0.10

0.50

±0.10

1.02

±0.20

2.30

±0.20

6.60

±0.20

0.76

±0.10

(5.34)

(1.50)

(2XR0.25)

(5.04)

0.89

±0.10

(0.10) (3.05)

(1.00)

(0.90)

(0.70)

0.91

±0.10

2.30TYP

[2.30±0.20]

2.30TYP

[2.30±0.20]

MAX0.96

(4.34)(0.50) (0.50)

DPAK

FQD1N60 / FQU1N60

Rev. A, April 2000

Package Dimensions (Continued)

6.60 ±0.20

0.76 ±0.10

MAX0.96

2.30TYP

[2.30±0.20] 2.30TYP

[2.30±0.20]

0.60 ±0.20

0.80 ±0.10

1.80 ±0.20

9.30 ±0.30

16.10 ±0.30

6.10 ±0.20

0.70 ±0.20

5.34 ±0.20

0.50 ±0.10

2.30 ±0.20

(0.50) (0.50)(4.34)

IPAK

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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY A NY LICENSE UNDER ITS PATENT RIGHTS, N OR THE RIGHTS OF OTHERS.

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INTERNATIONAL.

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which, (a) ar e intended for surgical implant into the body,

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when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later dat e.

Fairchild Semiconduct or reserv es the right to make

changes at any time without notice in order to improve

design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconduct or reserv es the right to make changes at

any time without notice in order to improve design.

Obsolete Not In Production This dat asheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.