2014 Microchip Technology Inc. DS20005304A-page 1
MCP45HVX1
Features:
• High-Voltage Analog Support:
- +36V Terminal Voltage Range (DGND = V-)
- ±18V Terminal Voltage Range
(DGND = V- + 18V)
• Wide Operating Voltage:
- Analog: 10V to 36V (specified performance)
- Digital: 2.7V to 5.5V
1.8V to 5.5V (VL V- + 2.7V)
• Single-Resistor Network
• Resistor Network Resolution
- 7-bit: 127 Resistors (128 Taps)
- 8-bit: 255 Resistors (256 Taps)
•R
AB Resistance Options:
-5k10 k
-50k100 k
• High Terminal/Wiper Current (IW) Support:
- 25mA (for 5k)
- 12.5 mA (for 10 k)
- 6.5 mA (for 50 k and 100 k)
• Zero-Scale to Full-Scale Wiper Operation
• Low Wiper Resistance: 75 (typical)
•Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to +70°C)
- Ratiometric (Potentiometer): 15 ppm typical
•I
2C Serial Interface:
- 100 kHz, 400 kHz, 1.7 MHz,
and 3.4 MHz support
• Resistor Network Terminal Disconnect Via:
- Shutdown Pin (SHDN)
- Terminal Control (TCON) Register
• Write Latch (WLAT) Pin to Control Update of
Volatile Wiper Register (such as Zero Crossing)
• Power-On Reset/Brown-Out Reset for Both:
- Digital supply (VL/DGND); 1.5V typical
- Analog supply (V+/V-); 3.5V typical
• Serial Interface Inactive Current (3 µA typical)
• 500 kHz Typical Bandwidth (-4dB) Operation
(5.0 k Device)
• Extended Temperature Range (-40°C to +125°C)
• Package Types: TSSOP-14 and QFN-20 (5x5)
Package Types (Top View)
Description:
The MCP45HVX1 family of devices have dual power
rails (analog and digital). The analog power rail allows
high voltage on the resistor network terminal pins. The
analog voltage range is determined by the V+ and V–
voltages. The maximum analog voltage is +36V, while
the operating analog output minimum specifications
are specified from either 10V or 20V. As the analog
supply voltage becomes smaller, the analog switch
resistances increase, which affect certain performance
specifications. The system can be implemented as dual
rail (±18V) relative to the digital logic ground (DGND).
The device also has a Write Latch (WLAT) function,
which will inhibit the volatile Wiper register from being
updated (latched) with the received data, until the
WLAT pin is Low. This allows the application to specify
a condition where the volatile Wiper register is updated
(such as zero crossing).
MCP45HVX1 Single Potentiometer
1
2
3
4
14
15
17
18
NC (2)
NC (2)
6789
12
13 P0B
P0W
V-
NC (2)
NC (2)
SHDN
SDA
VL
A1
SCL
19
20
WLAT
NC (2)
NC (2)
P0A
5
A0
10
NC (2)
11 DGND
16
V+
21 EP(1)
Note 1: Exposed Pad (EP)
2: NC = Not Internally Connected
TSSOP (ST)
QFN 5x5 (MQ)
1
2
3
411
12
13
14
V—
PB0
DGND
PW0
5
6
78
9
10
V+
SHDN
PA0
SCL
VL
NC
WLAT
A1
A0
SDA
7/8-Bit Single, +36V (±18V) Digital POT
with I2C™ Serial Interface and Volatile Memory
MCP45HVX1
DS20005304A-page 2 2014 Microchip Technology Inc.
Device Block Diagram
Device Features
Device
# of POTs
Wiper
Configuration
Control
Interface
POR Wiper
Setting
Resistance (Typical) Number
of: Specified Operating
Range
RAB Options
(k)Wiper -
RW ()
RS
Taps
VL (2)V+ (3)
MCP45HV31 1 Potentiometer
(1) I2C™ 3Fh 5.0, 10.0,
50.0, 100.0 75 127 128 1.8V to
5.5V
10V (4) to 36V
MCP45HV51 1 Potentiometer
(1) I
2C7Fh 5.0, 10.0,
50.0, 100.0 75 255 256 1.8V to
5.5V
10V (4) to 36V
MCP41HV31(5)1Potentiometer SPI 3Fh 5.0, 10.0,
50.0, 100.0 75 127 128 1.8V to
5.5V
10V (4) to 36V
MCP41HV51(5) 1 Potentiometer
(5) SPI 7Fh 5.0, 10.0,
50.0, 100.0 75 255 256 1.8V to
5.5V
10V (4) to 36V
Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
2: This is relative to the DGND signal. There is a separate requirement for the V+/V- voltages.
VL V- + 2.7V.
3: Relative to V-, the VL and DGND signals must be between (inclusive) V- and V+.
4: Analog operation will continue while the V+ voltage is above the device’s analog Power-On Reset (POR)/
Brown-out Reset (BOR) voltage. Operational characteristics may exceed specified limits while the V+
voltage is below the specified minimum voltage.
5: For additional information on these devices, refer to DS20005207.
Power-Up/
Brown-Out
Control
VL
DGND
I2C™ Serial
Interface
Module and
Control
Logic Resistor
Network 0
(Pot 0)
Wiper 0
and TCON
Register
SCL
SDA
SHDN
Memory (2x8)
Wiper0 (V)
TCON
P0A
P0W
P0B
V+ V–
WLAT
Power-Up/
Brown-Out
Control
(Analog)
(Digital)
A0
A1
2014 Microchip Technology Inc. DS20005304A-page 3
MCP45HVX1
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings †
Voltage on V- with respect to DGND ......................................................................................... DGND + 0.6V to -40.0V
Voltage on V+ with respect to DGND ........................................................................................... DGND - 0.3V to 40.0V
Voltage on V+ with respect to V- .................................................................................................. DGND - 0.3V to 40.0V
Voltage on VL with respect to V+ ............................................................................................................ -0.6V to -40.0V
Voltage on VL with respect to V- ............................................................................................................. -0.6V to +40.0V
Voltage on VL with respect to DGND ....................................................................................................... -0.6V to +7.0V
Voltage on SCL, SDA, A0, A1, WLAT, and SHDN with respect to DGND .......................................... -0.6V to VL + 0.6V
Voltage on all other pins (PxA, PxW, and PxB) with respect to V- ......................................................-0.3V to V+ + 0.3V
Input clamp current, IIK (VI < 0, VI > VL, VI > VPP on HV pins) ............................................................................ ±20 mA
Output clamp current, IOK (VO < 0 or VO > VL) ................................................................................................... ±20 mA
Maximum current out of DGND pin...................................................................................................................... 100 mA
Maximum current into VL pin................................................................................................................................ 100 mA
Maximum current out of V- pin ............................................................................................................................. 100 mA
Maximum current into V+ pin ................................................................................................................................100 mA
Maximum current into PXA, PXW, and PXB pins (Continuous)
RAB = 5 k ............................................................................................................................. ±25 mA
RAB = 10 k ........................................................................................................................ ±12.5 mA
RAB = 50 k .......................................................................................................................... ±6.5mA
RAB = 100 k ........................................................................................................................ ±6.5 mA
Maximum current into PXA, PXW, and PXB pins (Pulsed)
F
PULSE > 10 kHz ......................................................................................................... (Max IContinuous) / (Duty Cycle)
FPULSE 10 kHz ...................................................................................................... (Max IContinuous) / (Duty Cycle)
Maximum output current sunk by any Output pin .................................................................................................. 25 mA
Maximum output current sourced by any Output pin ............................................................................................ 25 mA
Package Power Dissipation (TA = + 50°C, TJ = +150°C)
TSSOP-14 ............................................................................................................................................. 1000 mW
QFN-20 (5 x 5) ...................................................................................................................................... 2800 mW
Soldering temperature of leads (10 seconds) ..................................................................................................... +300°C
ESD protection on all pins
Human Body Model (HBM) ...................................................................................................................... ±5 kV
Machine Model (MM)  ±400V
Maximum Junction Temperature (TJ)..................................................................................................................... 150°C
Storage temperature ............................................................................................................................. -65°C to +150°C
Ambient temperature with power applied .............................................................................................. -40°C to +125°C
† Not ice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
MCP45HVX1
DS20005304A-page 4 2014 Microchip Technology Inc.
AC/DC CHARACTERISTICS
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Digital Positive
Supply Voltage (VL)
VL2.7 — 5.5 V With respect to DGND (Note 4)
1.8 — 5.5 V VL V- + 2.7V
(Note 1, Note 4)
— — 0 V With respect to V+
Analog Positive
Supply Voltage (V+)
V+ VL (16) — 36.0 V With respect to V- (Note 4)
Digital Ground
Voltage (DGND)
VDGND V- — V+ - VL V With respect to V- (Note 4, Note 5)
Analog Negative
Supply Voltage (V-)
V- -36.0 + VL — 0 V With respect to DGND and with VL = 1.8V
Resistor Network
Supply Voltage
VRN — — 36.0 V Delta voltage between V+ and V- (Note 4)
VL Start Voltage to
ensure Wiper Reset
VDPOR — — 1.8 V With respect to DGND, V+ > 6.0V
RAM retention voltage (VRAM) < VDBOR
V+ Voltage to ensure
Wiper Reset
VAPOR — — 6.0 V With respect to V-, VL = 0V
RAM retention voltage (VRAM) < VBOR
Digital to Analog
Level Shifter
Operational Voltage
VLS ——2.3 VV
L to V- voltage.
DGND = V-
Power Rail Voltages
during Power-Up
(Note 1)
VLPOR — — 5.5 V Digital Powers (VL/DGND) up 1st:
V+ and V- floating
or
as V+/V- powers-up
(V+ must be to DGND) (Note 18)
V+POR — — 36 V Analog Powers (V+/V-) up 1st:
VL and DGND floating
or
as VL/DGND powers-up
(DGND must be between V- and V+)
(Note 18)
VL Rise Rate to
ensure Power-On
Reset
VLRR (Note 6) V/ms With respect to DGND
Note 1: This specification by design.
Note 4: V+ voltage is dependent on V- voltage. The maximum delta voltage between V+ and V- is 36V. The digital
logic DGND potential can be anywhere between V+ and V-, the VL potential must be  DGND and  V+.
Note 5: Minimum value determined by maximum V- to V+ potential equals 36V and minimum VL = 1.8V for opera-
tion. So 36V - 1.8V = 34.2V.
Note 6: POR/BOR is not rate dependent.
Note 16: For specified analog performance, V+ must be 20V or greater (unless otherwise noted).
Note 18: During the power-up sequence, to ensure expected analog POR operation, the two power systems (analog
and digital) should have a common reference to ensure that the driven DGND voltage is not at a higher
potential than the driven V+ voltage.
2014 Microchip Technology Inc. DS20005304A-page 5
MCP45HVX1
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Delay after
device exits the
Reset state
(VL > VBOR)
TBORD —10 20µs
Supply Current
(Note 7)IDDD — 45 650 µA Serial Interface Active,
Write all 0’s to Volatile Wiper 0 (address 0h)
VL = 5.5V, FSCL = 3.4 MHz,
V- = DGND
— 4 7 µA Serial Interface Inactive,
VL = 5.5V, SCL = VIH, Wiper = 0,
V- = DGND
IDDA — — 5 µA Current V+ to V-, PxA = PxB = PxW,
DGND = V- +(V+/2)
Resistance
(± 20%)(Note 8)
RAB 4.0 5 6.0 k -502 devices, V+/V- = 10V to 36V
8.0 10 12.0 k -103 devices, V+/V- = 10V to 36V
40.0 50 60.0 k -503 devices, V+/V- = 10V to 36V
80.0 100 120.0 k -104 devices, V+/V- = 10V to 36V
RAB Current IAB — — 9.00 mA -502 devices 36V / RAB(MIN),
V- = -18V, V+ = +18V,
(Note 9)
— — 4.50 mA -103 devices
— — 0.90 mA -503 devices
— — 0.45 mA -104 devices
Resolution N 256 Taps 8-bit No Missing Codes
128 Taps 7-bit No Missing Codes
Step Resistance
(see Appendix
B.4)
RS —R
AB/(255) — 8-bit Note 1
—R
AB/(127) — 7-bit Note 1
Note 1: This specification by design.
Note 7: Supply current (IDDD and IDDA) is independent of current through the resistor network.
Note 8: Resistance (RAB) is defined as the resistance between Terminal A to Terminal B.
Note 9: Ensured by the RAB specification and Ohm’s Law.
MCP45HVX1
DS20005304A-page 6 2014 Microchip Technology Inc.
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Wiper Resistance
(see Appen dix B.5)
RW — 75 170 IW = 1 mA V+ = +18V, V- = -18V,
code = 00h, PxA = floating,
PxB = V-.
— 145 200 IW = 1 mA V+ = +5.0V, V- = -5.0V,
code = 00h, PxA = floating,
PxB = V-. (Note 2)
Nominal Resistance
Te m pco
(see Appen dix B.23)
RAB/T—50 —ppm/°CT
A = -40°C to +85°C
— 100 — ppm/°C TA = -40°C to +125°C
Ratiometeric Tempco
(see Appen dix B.22)
VBW/T — 15 — ppm/°C Code = Mid scale (7Fh or 3Fh)
Resistor Terminal Input
Voltage Range
(Terminals A, B and W)
VA,VW,VBV- — V+ V Note 1, Note 11
Current through
Te r min al s
(A, B, and Wiper)
(Note 1)
IT
, IW — — 25 mA -502 devices IBW(W ≠ ZS) and IAW(W ≠ FS)
— — 12.5 mA -103 devices IBW(W ≠ ZS) and IAW(W ≠ FS)
— — 6.5 mA -503 devices IBW(W ≠ ZS) and IAW(W ≠ FS)
— — 6.5 mA -104 devices IBW(W ≠ ZS) and IAW(W ≠ FS)
——36 mAI
BW(W = ZS), or IAW(W = FS)
Leakage current into A,
W or B
ITL — 5 — nA A = W = B = V-
Note 1: This specification by design.
Note 2: This parameter is not tested, but specified by characterization.
Note 11: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
2014 Microchip Technology Inc. DS20005304A-page 7
MCP45HVX1
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Full Scale Error
(Potentiometer)
(8-bit code = FFh,
7-bit code = 7Fh)
(Note 10, Note 17)
(VA = V+, VB = V- )
(see Appendix
B.10)
VWFSE -10.5 — — LSb 5 k
8-bit
VAB = 20V to 36V
-8.5 — — LSb VAB = 20V to 36V
–40°C TA +85°C (Note 2)
-14.0 — — LSb VAB = 10V to 36V
-5.5 — — LSb
7-bit
VAB = 20V to 36V
-4.5 — — LSb VAB = 20V to 36V
–40°C TA +85°C (Note 2)
-7.5 — — LSb VAB = 10V to 36V
-4.5 — — LSb 10 k 8-bit VAB = 20V to 36V
-6.0 — — LSb VAB = 10V to 36V
-2.65 — — LSb
7-bit
VAB = 20V to 36V
-2.25 — — LSb VAB = 20V to 36V
–40°C TA +85°C (Note 2)
-3.5 — — LSb VAB = 10V to 36V
-1.0 — — LSb 50 k 8-bit VAB = 20V to 36V
-1.4 — — LSb VAB = 10V to 36V
-1.0 — — LSb 7-bit VAB = 20V to 36V
-1.2 — — LSb VAB = 10V to 36V
-0.7 — — LSb 100 k 8-bit VAB = 20V to 36V
-0.95 — — LSb VAB = 10V to 36V
-0.85 — — LSb 7-bit VAB = 20V to 36V
-0.975 — — LSb VAB = 10V to 36V
Note 2: This parameter is not tested, but specified by characterization.
Note 10: Measured at VW with VA = V+ and VB = V-.
Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage.
MCP45HVX1
DS20005304A-page 8 2014 Microchip Technology Inc.
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Zero Scale Error
(Potentiometer)
(8-bit code = 00h,
7-bit code = 00h)
(Note 10, Note 17)
(VA = V+, VB = V- )
(see Appendix
B.11)
VWZSE ——+9.5LSb5k
8-bit
VAB = 20V to 36V
— — +8.5 LSb VAB = 20V to 36V
–40°C TA +85°C (Note 2)
— — +14.5 LSb VAB = 10V to 36V
——+4.5LSb 7-bit VAB = 20V to 36V
— — +7.0 LSb VAB = 10V to 36V
——+4.25LSb10k 8-bit VAB = 20V to 36V
— — +6.5 LSb VAB = 10V to 36V
— — +2.125 LSb 7-bit VAB = 20V to 36V
— — +3.25 LSb VAB = 10V to 36V
——+0.9LSb50k 8-bit VAB = 20V to 36V
— — +1.3 LSb VAB = 10V to 36V
——+0.5LSb 7-bit VAB = 20V to 36V
— — +0.7 LSb VAB = 10V to 36V
——+0.6LSb100k 8-bit VAB = 20V to 36V
— — +0.95 LSb VAB = 10V to 36V
——+0.3LSb 7-bit VAB = 20V to 36V
— — +0.475 LSb VAB = 10V to 36V
Note 2: This parameter is not tested, but specified by characterization.
Note 10: Measured at VW with VA = V+ and VB = V-.
Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage.
2014 Microchip Technology Inc. DS20005304A-page 9
MCP45HVX1
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Potentiometer
Integral
Nonlinearity
(Note 10,
Note 17)
(see Appendix
B.12)
P-INL -1 ±0.5 +1 LSb 5 k 8-bit
VAB = 10V to 36V
-0.5 ±0.25 +0.5 LSb 7-bit VAB = 10V to 36V
-1 ±0.5 +1 LSb 10 k 8-bit
VAB = 10V to 36V
-0.5 ±0.25 +0.5 LSb 7-bit VAB = 10V to 36V
-1.1 ±0.5 +1.1 LSb 50 k 8-bit
VAB = 10V to 36V
-1 ±0.5 +1 LSb VAB = 20V to 36V, (Note 2)
-1 ±0.5 +1 LSb VAB = 10V to 36V,
–40°C TA +85°C (Note 2)
-0.6 ±0.25 +0.6 LSb 7-bit VAB = 10V to 36V
-1.85 ±0.5 +1.85 LSb 100 k 8-bit VAB = 10V to 36V
-1.2 ±0.5 +1.2 LSb VAB = 20V to 36V, (Note 2)
-1 ±0.5 +1 LSb VAB = 10V to 36V,
–40°C TA +85°C (Note 2)
-1 ±0.5 +1 LSb 7-bit VAB = 10V to 36V
Potentiometer
Differential
Nonlinearity
(Note 10,
Note 17)
(see Appendix
B.13)
P-DNL -0.7 ±0.25 +0.7 LSb 5 k 8-bit
VAB = 10V to 36V
-0.5 ±0.25 +0.5 LSb VAB = 20V to 36V (Note 2)
-0.25 ±0.125 +0.25 LSb 7-bit VAB = 10V to 36V
-0.375 ±0.125 +0.375 LSb 10 k 8-bit
VAB = 10V to 36V
-0.25 ±0.1 +0.25 LSb 7-bit VAB = 10V to 36V
-0.25 ±0.125 +0.25 LSb 50 k 8-bit
VAB = 10V to 36V
-0.125 ±0.1 +0.125 LSb 7-bit VAB = 10V to 36V
-0.25 ±0.125 +0.25 LSb 100 k 8-bit VAB = 10V to 36V
-0.125 ±0.1 +0.125 LSb 7-bit VAB = 10V to 36V
Note 2: This parameter is not tested, but specified by characterization.
Note 10: Measured at VW with VA = V+ and VB = V-.
Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage.
MCP45HVX1
DS20005304A-page 10 2014 Microchip Technology Inc.
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Bandwidth -3 dB
(load = 30 pF)
BW — 480 — kHz 5 k 8-bit Code = 7Fh
— 480 — kHz 7-bit Code = 3Fh
—240 — kHz10k 8-bit Code = 7Fh
— 240 — kHz 7-bit Code = 3Fh
—48 — kHz50k 8-bit Code = 7Fh
— 48 — kHz 7-bit Code = 3Fh
—24 — kHz100k 8-bit Code = 7Fh
— 24 — kHz 7-bit Code = 3Fh
VW Settling Time
(VA = 10V, VB = 0V,
±1LSb error band,
CL = 50 pF)
(see Appen dix B.17)
tS —1 — µs5kCode = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
—1 — µs10kCode = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
—2.5 — µs50kCode = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
—5 — µs100kCode = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
2014 Microchip Technology Inc. DS20005304A-page 11
MCP45HVX1
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Rheostat Integral
Nonlinearity
(Note 12, Note 13,
Note 14, Note 17)
(see Appendix
B.5)
R-INL -2.0. — +2.0 LSb 5 k8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2)
-2.5 —+2.5 LSb IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
-4.5 —+4.5 LSb IW = 1.7 mA, (V+ - V-) = 10V
-1.0 — +1.0 LSb 7-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2)
-1.5 —+1.5 LSb IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
-2.0 —+2.0 LSb IW = 1.7 mA, (V+ - V-) = 10V
-1.2 — +1.2 LSb 10 k8-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
-1.75 —+1.75 LSb IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
-2.0 —+2.0 LSb IW = 830 µA, (V+ - V-) = 10V
-0.6 — +0.6 LSb 7-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
-0.8 —+0.8 LSb IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
-1.1 —+1.1 LSb IW = 830 µA, (V+ - V-) = 10V
-1.0 — +1.0 LSb 50 k8-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
-1.0 —+1.0 LSb IW = 330 µA, (V+ - V-) = 20V (Note 2)
-1.2 —+1.2 LSb IW = 170 µA, (V+ - V-) = 10V
-0.5 — +0.5 LSb 7-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
-0.5 —+0.5 LSb IW = 330 µA, (V+ - V-) = 20V (Note 2)
-0.6 —+0.6 LSb IW = 170 µA, (V+ - V-) = 10V
-1.0 — +1.0 LSb 100 k8-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
-1.0 —+1.0 LSb IW = 170 µA, (V+ - V-) = 20V(Note 2)
-1.2 —+1.2 LSb IW = 83 µA, (V+ - V-) = 10V
-0.5 — +0.5 LSb 7-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
-0.5 —+0.5 LSb IW = 170 µA, (V+ - V-) = 20V (Note 2)
-0.6 —+0.6 LSb IW = 83 µA, (V+ - V-) = 10V
Note 2: This parameter is not tested, but specified by characterization.
Note 12: Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature.
Note 13: Externally connected to a Rheostat configuration (RBW), and then tested.
Note 14: Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+
and V- (voltages are 36V, 20V, and 10V).
Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage.
MCP45HVX1
DS20005304A-page 12 2014 Microchip Technology Inc.
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Rheostat
Differential
Nonlinearity
(Note 12, Note 13,
Note 14, Note 17)
(see Appendix
B.5)
R-DNL -0.5 — +0.5 LSb 5 k8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2)
-0.5 —+0.5 LSb IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
-0.8 —+0.8 LSb IW = 1.7 mA, (V+ - V-) = 10V
-0.25 — +0.25 LSb 7-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2)
-0.25 —+0.25 LSb IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
-0.4 —+0.4 LSb IW = 1.7 mA, (V+ - V-) = 10V
-0.5 — +0.5 LSb 10 k8-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
-0.5 —+0.5 LSb IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
-0.5 —+0.5 LSb IW = 830 µA, (V+ - V-) = 10V
-0.25 — +0.25 LSb 7-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
-0.25 —+0.25 LSb IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
-0.25 —+0.25 LSb IW = 830 µA, (V+ - V-) = 10V
-0.5 — +0.5 LSb 50 k8-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
-0.5 —+0.5 LSb IW = 330 µA, (V+ - V-) = 20V (Note 2)
-0.5 —+0.5 LSb IW = 170 µA, (V+ - V-) = 10V
-0.25 — +0.25 LSb 7-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
-0.25 —+0.25 LSb IW = 330 µA, (V+ - V-) = 20V (Note 2)
-0.25 —+0.25 LSb IW = 170 µA, (V+ - V-) = 10V
-0.5 — +0.5 LSb 100 k
8-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
-0.5 —+0.5 LSb IW = 170 µA, (V+ - V-) = 20V (Note 2)
-0.5 —+0.5 LSb IW = 83 µA, (V+ - V-) = 10V
-0.25 — +0.25 LSb 7-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
-0.25 —+0.25 LSb IW = 170 µA, (V+ - V-) = 20V (Note 2)
-0.25 —+0.25 LSb IW = 83 µA, (V+ - V-) = 10V
Note 2: This parameter is not tested, but specified by characterization.
Note 12: Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature.
Note 13: Externally connected to a Rheostat configuration (RBW), and then tested.
Note 14: Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+
and V- (voltages are 36V, 20V, and 10V).
Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage.
2014 Microchip Technology Inc. DS20005304A-page 13
MCP45HVX1
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
S tandard Operating Conditi ons (unless otherwise speci fied)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Capacitance (PA)C
A— 75 — pF Measured to V-, f =1 MHz,
Wiper code = Mid Scale
Capacitance (Pw)C
W— 120 — pF Measured to V-, f =1 MHz,
Wiper code = Mid Scale
Capacitance (PB)C
B— 75 — pF Measured to V-, f =1 MHz,
Wiper code = Mid Scale
Common-Mode
Leakage
ICM —5—nAV
A = VB = VW
Digital Interface Pin
Capacitance
CIN,
COUT
—10—pFf
C = 400 kHz
Digital Inputs/Outputs (SDA, SCL, A0, A1, SHDN, WLAT)
Schmitt Trigger High-
Input Threshold
VIH 0.7 VL —V
L + 0.3V V 1.8V VL 5.5V
Schmitt Trigger Low-
Input Threshold
VIL DGND - 0.5V — 0.3 VL V
Hysteresis of Schmitt
Trigger Inputs
VHYS —0.1V
L —V
Output Low
Voltage (SDA)
VOL DGND — 0.2 VL VV
L = 5.5V, IOL = 5 mA
DGND — 0.2 VL VV
L = 1.8V, IOL = 800 µA
Input Leakage
Current
IIL -1 1 uA VIN = VL and VIN = DGND
MCP45HVX1
DS20005304A-page 14 2014 Microchip Technology Inc.
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
RAM (Wiper, TCON) Value
Wiper Value Range N 0h — FFh hex 8-bit
0h — 7Fh hex 7-bit
Wiper POR/BOR Value NPOR/BOR 7Fh hex 8-bit
3Fh hex 7-bit
TCON Value Range N 0h — FFh hex
TCON POR/BOR Value NTCON FF hex All Terminals connected
Power Requireme nts
Power Supply
Sensitivity
(see Appen dix B.20)
PSS — 0.0015 0.0035 %/% 8-bit VL = 2.7V to 5.5V,
V+ = 18V, V- = -18V,
Code = 7Fh
— 0.0015 0.0035 %/% 7-bit VL = 2.7V to 5.5V,
V+ = 18V, V- = -18V,
Code = 3Fh
Power Dissipation PDISS —260 —mW5kVL = 5.5V, V+ = 18V, V- = -18V
(Note 15)
—130 —mW10k
—26 —mW50k
— 13 — mW 100 k
Note 15:P
DISS = I * V, or ( (IDDD * 5.5V) + (IDDA * 36V) + (IAB * 36V) ).
2014 Microchip Technology Inc. DS20005304A-page 15
MCP45HVX1
DC Notes:
1. This specification by design.
2. This parameter is not tested, but specified by characterization.
3. See Absolute Maximum Ratings.
4. V+ voltage is dependent on V- voltage. The maximum delta voltage between V+ and V- is 36V. The digital logic
DGND potential can be anywhere between V+ and V-, the VL potential must be  DGND and  V+.
5. Minimum value determined by maximum V- to V+ potential equals 36V and minimum VL = 1.8V for operation. So
36V - 1.8V = 34.2V.
6. POR/BOR is not rate dependent.
7. Supply current (IDDD and IDDA) is independent of current through the resistor network.
8. Resistance (RAB) is defined as the resistance between Terminal A to Terminal B.
9. Ensured by the RAB specification and Ohm’s Law.
10. Measured at VW with VA = V+ and VB = V-.
11. Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
12. Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature.
13. Externally connected to a Rheostat configuration (RBW), and then tested.
14. Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+ and V-
(voltages are 36V, 20V, and 10V).
15. PDISS = I * V, or ( (IDDD * 5.5V) + (IDDA * 36V) + (IAB * 36V) ).
16. For specified analog performance, V+ must be 20V or greater (unless otherwise noted).
17. Analog switch leakage affects this specification. Higher temperatures increase the switch leakage.
18. During the power-up sequence, to ensure expected analog POR operation, the two power systems (analog and
digital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential than
the driven V+ voltage.
MCP45HVX1
DS20005304A-page 16 2014 Microchip Technology Inc.
1.1 Timing Waveforms and Requirement s
FIGURE 1-1: Settling Time Waveforms.
TABLE 1-1: WIPER SETTLING TIMING
Timing Char acteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
VW Settling Time
(VA = 10V, VB = 0V,
±1LSb error band,
CL = 50 pF )
tS —1—µs5kCode = 00h -> FFh (7Fh); FFh (7Fh) -> 00h
—1—µs10kCode = 00h -> FFh (7Fh); FFh (7Fh) -> 00h
—2.5—µs50kCode = 00h -> FFh (7Fh); FFh (7Fh) -> 00h
— 5 — µs 100 kCode = 00h -> FFh (7Fh); FFh (7Fh) -> 00h
W
± 1 LSb
Old Value
New Value
2014 Microchip Technology Inc. DS20005304A-page 17
MCP45HVX1
FIGURE 1-2: I2C Bus Start/Stop Bits Timing Waveforms.
TABLE 1-2: I2C BUS START/STOP BITS AND WLAT REQUIREMENTS
I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
2.7V VL5.5V; DGND = V- (Note 1)
Param. No. Symbol Characteristic Min. Max. Units Conditions
FSCL Standard mode 0 100 kHz Cb = 400 pF, 1.8V VL5.5V
Fast mode 0 400 kHz Cb = 400 pF, 2.7V VL5.5V
High Speed 1.7 0 1.7 MHz Cb = 400 pF, 4.5V VL5.5V
High Speed 3.4 0 3.4 MHz Cb = 100 pF, 4.5V VL5.5V
D102 Cb Bus capacitive
loading
100 kHz mode — 400 pF
400 kHz mode — 400 pF
1.7 MHz mode — 400 pF
3.4 MHz mode — 100 pF
90 TSU:STA Start condition
Setup time
100 kHz mode 4700 — ns Only relevant for repeated Start
condition
400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
91 THD:STA Start condition
Hold time
100 kHz mode 4000 — ns After this period the first clock
pulse is generated
400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
92 TSU:STO Stop condition
Setup time
100 kHz mode 4000 — ns
400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
93 THD:STO Stop condition
Hold time
100 kHz mode 4000 — ns
400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
94 TWLSU WLAT ↑ to SCL↑ (write data ACK
bit) Setup time
10 — ns Write Data delayed, Note 9
95 TWLHD SCL ↑ to WLAT↑ (write data ACK
bit) Hold time
250 — ns Write Data delayed, Note 9
96 TWLATL WLAT High or Low Time 2 — µs
Note 1: Serial Interface has equal performance when DGND V- + 0.9V.
Note 9: The transition of the WLAT signal between 10 ns before the rising edge (Spec 94) and 200 ns after the rising edge
(Spec 95) of the SCL signal is indeterminant if the Write Data is delayed or not.
91 93
SCL
SDA
START
Condition
STOP
Condition
90 92
WLAT
94
ACK/
ACK
Pulse
96
95
96
MCP45HVX1
DS20005304A-page 18 2014 Microchip Technology Inc.
FIGURE 1-3: I2C Bus Timing W aveforms.
TABLE 1-3: I2C BUS REQUIREMENTS (SLAVE MODE)
I2C™ AC Characteristics S tandard Operating Conditi ons (unle ss othe rwis e speci fied)
Operating Temperature –40C T
A +125C (Extended)
2.7V VL5.5V; DGND = V- (Note 1)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
100 THIGH Clock high time 100 kHz mode 4000 — ns 1.8V-5.5V
400 kHz mode 600 — ns 2.7V-5.5V
1.7 MHz mode 120 — ns 4.5V-5.5V
3.4 MHz mode 60 — ns 4.5V-5.5V
101 TLOW Clock low time 100 kHz mode 4700 — ns 1.8V-5.5V
400 kHz mode 1300 — ns 2.7V-5.5V
1.7 MHz mode 320 — ns 4.5V-5.5V
3.4 MHz mode 160 — ns 4.5V-5.5V
102A (6) TRSCL SCL rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
1.7 MHz mode 20 160 ns After a Repeated Start
condition or an
Acknowledge bit
3.4 MHz mode 10 40 ns
3.4 MHz mode 10 80 ns After a Repeated Start
condition or an
Acknowledge bit
102B (6) TRSDA SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
Note 1: Serial Interface has equal performance when DGND V- + 0.9V.
Note 6: Not tested.
90 91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
2014 Microchip Technology Inc. DS20005304A-page 19
MCP45HVX1
TABLE 1-4: I2C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
2.7V VL5.5V; DGND = V- (Note 1)
Param. No. Sym. Characteristi c Min. Max. Unit s Conditions
103A (5) TFSCL SCL fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
3.4 MHz mode 10 40 ns
103B (5) TFSDA SDA fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb (4) 300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
106 THD:DA
T
Data input hold
time
100 kHz mode 0 — ns 1.8V-5.5V, Note 7
400 kHz mode 0 — ns 2.7V-5.5V, Note 7
1.7 MHz mode 0 — ns 4.5V-5.5V, Note 7
3.4 MHz mode 0 — ns 4.5V-5.5V, Note 7
107 TSU:DAT Data input
setup time
100 kHz mode 250 — ns Note 3
400 kHz mode 100 — ns
1.7 MHz mode 10 — ns
3.4 MHz mode 10 — ns
109 TAA Output valid
from clock
100 kHz mode — 3450 ns Note 2
400 kHz mode — 900 ns
1.7 MHz mode — 150 ns Cb = 100 pF,
Note 2, Note 8
— 310 ns Cb = 400 pF,
Note 2, Note 6
3.4 MHz mode — 150 ns Cb = 100 pF, Note 2
110 TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free
before a new transmission
can start
400 kHz mode 1300 — ns
1.7 MHz mode N.A. — ns
3.4 MHz mode N.A. — ns
TSP Input filter spike
suppression
(SDA and SCL)
100 kHz mode — 50 ns NXP Spec states N.A.
400 kHz mode — 50 ns
1.7 MHz mode — 10 ns Spike suppression
3.4 MHz mode — 10 ns Spike suppression
Note 1:Serial Interface has equal performance when DGND V- + 0.9V.
Note 2:As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
Note 3:A fast-mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the
requirement tSU;DAT  250 ns must then be met. This will automatically be the case if the device does not
stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it
must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification) before the SCL line is released.
Note 6:Not tested.
Note 7:A master transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not
unintentionally create a Start or Stop condition.
Note 8:Ensured by the TAA 3.4 MHz specification test.
MCP45HVX1
DS20005304A-page 20 2014 Microchip Technology Inc.
T imi ng Table Notes:
1. Serial Interface has equal performance when DGND V- + 0.9V.
2. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3. A fast-mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the require-
ment tSU;DAT  250 ns must then be met. This will automatically be the case if the device does not stretch the
Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the
next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL
line is released.
4. The MCP45HVX1 device must provide a data hold time to bridge the undefined part between VIH and VIL of the
falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order
to ensure that the output data will meet the setup and hold specifications for the receiving device.
5. Use Cb in pF for the calculations.
6. Not tested.
7. A master transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not
unintentionally create a Start or Stop condition.
8. Ensured by the TAA 3.4 MHz specification test.
9. The transition of the WLAT signal between 10 ns before the rising edge (Spec 94) and 200 ns after the rising
edge (Spec 95) of the SCL signal is indeterminant if the Write Data is delayed or not.
2014 Microchip Technology Inc. DS20005304A-page 21
MCP45HVX1
TEMPERATURE CHARACTERISTICS
Electrical S pe cifi catio ns: Unless otherwise indicated, VL= +2.7V to +5.5V, V+ = +10V to +36V, V- = DGND = GND.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 14L-TSSOP (ST) JA —100—°C/W
Thermal Resistance, 20L-QFN (MQ) JA —36.1—°C/W
MCP45HVX1
DS20005304A-page 22 2014 Microchip Technology Inc.
2.0 TYPI CAL PERFORMANCE CURVES
Note: The device Performance Curves are available in a separate document. This is done to keep the file size of
this PDF document less than the 10MB file attachment limit of many mail servers.
The MCP45HVX1 Performance Curves document is literature number DS20005307, and can be found on
the Microchip web site. Look at the MCP45HVX1 Product Page under Documentation and Software, in the
Data Sheets category.
2014 Microchip Technology Inc. DS20005304A-page 23
MCP45HVX1
NOTES:
MCP45HVX1
DS20005304A-page 24 2014 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP45HVX1
Pin
FunctionTSSOP QFN Symbol Type Buffer
Type
14L 20L
11 V
LP — Positive Digital Power Supply Input
2 2 SCL I ST I2C™ Serial Clock pin
33 A1ISTI
2C Address 1
4 4 SDA I/O ST I2C Serial Data pin
55 A0 ISTI
2C Address 0
66 WLAT
I ST Wiper Latch Enable
0 = Received I2C Shift Register Buffer (SPBUF) value is
transfered to Wiper register.
1 = Received I2C data value is held in I2C Shift Register
Buffer (SPBUF).
7 8, 9, 10, 17,
18, 19, 20
NC — — Pin not internally connected to die. To reduce noise
coupling, connect pin either to DGND or VL.
87 SHDN ISTShutdown
9 11 DGND P — Ground
10 12 V- P — Analog Negative Potential Supply
11 13 P0B I/O A Potentiometer 0 Terminal B
12 14 P0W I/O A Potentiometer 0 Wiper
Te r min al
13 15 P0A I/O A Potentiometer 0 Terminal A
14 16 V+ P — Analog Positive Potential Supply
— 21 EP P — Exposed Pad, connect to V- signal or Not Connected
(floating). (Note 1)
Legend: A = Analog ST = Schmitt Trigger
I = Input O = Output I/O = Input/Output P = Power
Note 1: The QFN package has a contact on the bottom of the package. This contact is conductively connected to
the die substrate, and therefore should be unconnected or connected to the same ground as the device’s
V- pin.
2014 Microchip Technology Inc. DS20005304A-page 25
MCP45HVX1
3.1 Positive Power Supply Input (VL)
The VL pin is the device’s positive power supply input.
The input power supply is relative to DGND and can
range from 1.8V to 5.5V. A decoupling capacitor on VL
(to DGND) is recommended to achieve maximum
performance.
3.2 Digit al Ground (DGND)
The DGND pin is the device’s digital ground reference.
3.3 Analog Positive Voltage (V+)
Analog circuitry positive supply voltage. Must have a
higher potential than the V- pin.
3.4 Analog Negative Voltage (V-)
Analog circuitry negative supply voltage. The V-
potential must be lower than or equal to the DGND pin
potential.
3.5 Serial Clock (SCL)
The SCL pin is the serial interface's Serial Clock pin.
This pin is connected to the Host Controller’s SCL pin.
The MCP45HVX1 is an I2C slave device, so its SCL pin
is an input-only pin.
3.6 Serial Data (SDA)
The SDA pin is the serial interface’s Serial Data In/Out
pin. This pin is connected to the Host Controller’s SDA
pin. The SDA pin is an open-drain N-Channel driver.
This pin allows the host controller to read and write the
digital potentiometer registers (Wiper and TCON).
3.7 Address 0 (A0)
The A0 pin is the Address 0 input for the I2C interface.
At the device’s POR/BOR the value of the A0 address
bit is latched. This input along with the A1 pin com-
pletes the device address. This allows up to four
MCP45HVXX devices to be on a single I2C bus.
3.8 Address 1 (A1)
The A1 pin is the I2C interface’s Address 1 pin. Along
with the A0 pins, up to four MCP45HVXX devices can
be on a single I2C bus.
3.9 Wiper Latch (WLAT)
The WLAT pin is used to hold off the transfer of the
received wiper value (in the Shift register) to the Wiper
register. This allows this transfer to be synchronized to
an external event (such as zero crossing). See
Section 4.3.2.
3.10 Shutdown (SHDN)
The SHDN pin is used to force the resistor network
terminals into the hardware shutdown state. See
Section 4.3.1.
3.11 Po te n t io me t e r Ter min a l B
The Terminal B pin is connected to the internal
potentiometer’s Terminal B.
The potentiometer’s Terminal B is the fixed connection
to the zero-scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x00 for both 7-bit and 8-bit devices.
The Terminal B pin does not have a polarity relative to
the Terminal W or A pins. The Terminal B pin can
support both positive and negative current. The voltage
on Terminal B must be between V+ and V-.
3.12 Poten tiome t e r Wip e r (W) Term in a l
The Terminal W pin is connected to the internal
potentiometer’s Terminal W (the wiper). The wiper
terminal is the adjustable terminal of the digital
potentiometer. The Terminal W pin does not have a
polarity relative to Terminal’s A or B pins. The Terminal
W pin can support both positive and negative current.
The voltage on Terminal W must be between V+ and V-.
If the V+ voltage powers-up before the VL voltage, the
wiper is forced to mid scale once the analog POR
voltage is crossed.
If the V+ voltage powers-up after the VL voltage is
greater than the digital POR voltage, the wiper is forced
to the value in the Wiper register once the analog POR
voltage is crossed.
3.13 Potentiometer Terminal A
The Terminal A pin is connected to the internal
potentiometer’s Terminal A.
The potentiometer’s Terminal A is the fixed connection
to the full scale wiper value of the digital potentiometer.
This corresponds to a wiper value of 0xFF for 8-bit
devices or 0x7F for 7-bit devices.
The Terminal A pin does not have a polarity relative to
the Terminal W or B pins. The Terminal A pin can
support both positive and negative current. The voltage
on Terminal A must be between V+ and V-.
3.14 Exposed Pad (EP)
This pad is only on the bottom of the QFN packages.
This pad is conductively connected to the device
substrate. The EP pin must be connected to the V-
signal or left floating. This pad could be connected to a
PCB heat sink to assist as a heat sink for the device.
3.15 Not Connected (NC)
This pin is not internally connected to the die. To reduce
noise coupling, these pins should be connected to
either VL or DGND.
MCP45HVX1
DS20005304A-page 26 2014 Microchip Technology Inc.
4.0 FUNCTIONAL OVERVIEW
This data sheet covers a family of two volatile digital
potentiometer devices that will be referred to as
MCP45HVX1. These devices are:
• MCP45HV31 (7-bit resolution)
• MCP45HV51 (8-bit resolution)
As the Device Block Diagram shows, there are six
main functional blocks. These are:
•Operating Voltage Range
•POR/BOR Operation
•Memory Map
•Control Module
•Resistor Network
•Serial Interface (I2C)
The POR/BOR operation and the Memory Map are
discussed in this section and the Resistor Network and
I2C operation are described in their own sections. The
Device Commands are discussed in Section 7.0.
4.1 Operating Voltage Range
The MCP45HVX1 devices have four voltage signals.
These are:
• V+ – Analog Power
•V
L – Digital Power
• DGND – Digital Ground
• V- – Analog Ground
Figure 4-1 shows the two possible power-up
sequences; analog power rails power-up first, or digital
power rails power-up first. The device has been
designed so that either power rail may power-up first.
The device has a POR circuit for both digital power
circuitry and analog power circuitry.
If the V+ voltage powers-up before the VL voltage, the
wiper is forced to mid scale once the analog POR
voltage is crossed.
If the V+ voltage powers-up after the VL voltage is
greater than the digital POR voltage, the wiper is forced
to the value in the Wiper register, once the analog POR
voltage is crossed.
Figure 4-2 shows the three cases of the digital power
signals (VL/DGND) with respect to the analog power
signals (V+/V-). The device implements level shifts
between the digital and analog power systems, which
allows the digital interface voltage to be anywhere in
the V+/V- voltage window.
FIGURE 4-1: Power-On Sequences.
V-
V+
DGND
VL
V-
V+
DGND
VL
Referenced to V-
Referenced to DGND
V-
V+
DGND
VL
V-
V+
DGND
VL
Referenced to V-
Referenced to DGND
Analog Voltage Powers-Up First Digital Voltage Powers-Up First
2014 Microchip Technology Inc. DS20005304A-page 27
MCP45HVX1
FIGURE 4-2: Voltage Ranges.
V- and DGND
V+
VL
Case 1
V-
V+
DGND
Case 2
V-
V+ and VL
DGND
Case 3
VL
Anywhere
between
V+ and V-
High-
Voltage
Range
High-
Voltage
Range
High-
Voltage
Range
(VL DGND)
MCP45HVX1
DS20005304A-page 28 2014 Microchip Technology Inc.
4.2 POR/BOR Operation
The resistor network’s devices are powered by the
analog power signals (V+/V-), but the digital logic
(including the wiper registers) is powered by the digital
power signals (VL/DGND). So, both the digital circuitry
and analog circuitry have independent POR/BOR
circuits.
The wiper position will be forced to the default state
when the V+ voltage (relative to V-) is above the analog
POR/BOR trip point. The Wiper register will be in the
default state when the VL voltage (relative to DGND) is
above the digital POR/BOR trip point.
The digital-signal-to-analog-signal voltage level shifters
require a minimum voltage between the VL and V-
signals. This voltage requirement is below the
operating supply voltage specifications. The wiper
output may fluctuate while the VL voltage is less than
the level shifter operating voltage, since the analog
values may not reflect the digital value. Output issues
may be reduced by powering-up the digital supply
voltages to their operating voltage, before powering the
analog supply voltage.
4.2.1 POWER-ON RESET
Each power system has its own independent Power-On
Reset circuitry. This is done so that regardless of the
power-up sequencing of the analog and digital power
rails, the wiper output will be forced to a default value
after minimum conditions are met for either power sup-
ply.
Table 4-1 shows the interaction between the analog
and digital PORs for the V+ and VL voltages on the
wiper pin state.
TABLE 4-1: WIPER PIN STATE BASED
ON POR CONDITIONS
4.2.1.1 Digital Circuitry
The Digital Power-On Reset (DPOR) is the case where
the device’s VL signal has power applied (referenced
from DGND) and the voltage rises above the trip point.
The Brown-out Reset (BOR) occurs when a device had
power applied to it, and the voltage drops below the trip
point.
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less than 1.8V.
When the device powers-up, the device VL will cross
the VPOR/VBOR voltage. Once the VL voltage crosses
the VPOR/VBOR voltage, the following happens:
• Volatile wiper registers are loaded with the POR/
BOR value
• The TCON registers are loaded with the default
values
• The device is capable of digital operation
Table 4-2 shows the default POR/BOR Wiper Register
Setting Selection.
When VPOR/VBOR < VL < 2.7V, the electrical
performance may not meet the data sheet
specifications. In this region, the device is capable of
incrementing, decrementing, reading and writing to its
volatile memory if the proper serial command is
executed.
TABLE 4-2: DEFAULT POR/BOR WIPER
REGISTER SETTING
(DIGITAL)
VL Voltage
V+ V oltage
Comments
V+ <
VAPOR V+
VAPOR
VL < VDPOR Unknown Mid Scale
VL VDPOR Unknown Wiper
Register
Value (1)
Wiper register
can be updated
Note 1: Default POR state of the Wiper register
value is the mid-scale value.
Typical
RAB
Value
Package
Code
Default
POR Wiper
Register
Setting(1)
Device
Resolution Wiper
Code
5.0 k -502 Mid scale 8-bit 7Fh
7-bit 3Fh
10.0 k -103 Mid scale 8-bit 7Fh
7-bit 3Fh
50.0 k -503 Mid scale 8-bit 7Fh
7-bit 3Fh
100.0 k -104 Mid scale 8-bit 7Fh
7-bit 3Fh
Note 1: Register setting independent of analog
power voltage.
2014 Microchip Technology Inc. DS20005304A-page 29
MCP45HVX1
4.2.1.2 Analog Circuitry
The Analog Power-On Reset (APOR) is the case
where the device’s V+ pin voltage has power applied
(referenced from V-) and the V+ pin voltage rises above
the trip point.
Once the VL pin voltage exceeds the digital POR trip
point voltage, the Wiper register will control the wiper
setting.
Table 4-3 shows the default POR/BOR wiper setting for
when the VL pin is not powered (< digital POR trip
point).
TABLE 4-3: DEFAULT POR/BOR WIPER
SETTING (ANALOG)
FIGURE 4-3: DGND, VL, V+, and V- Signal Waveform Examples.
Typical
RAB
Value
Package
Code
Default POR Wiper
Setting(1)
Device
Resolution
Analog
Output
Position
Wiper
Register
Code (hex)
5.0 k -502 Mid scale 0x7F 8-bit
0x3F 7-bit
10.0 k -103 Mid scale 0x7F 8-bit
0x3F 7-bit
50.0 k -503 Mid scale 0x7F 8-bit
0x3F 7-bit
100.0 k -104 Mid scale 0x7F 8-bit
0x3F 7-bit
Note 1: Wiper setting is dependent on the Wiper
register value if the VL voltage is greater
than the digital POR voltage.
V-
V+
VL
Referenced to DGND
VPOR/VBOR
DGND
Brown-out condition
Wiper value unknown
Digital logic has been
reset (POR). This
includes the Wiper register.
Digital logic has been
reset (POR). This
includes the Wiper register. Analog Power
is recovering (still Low) and VL
Digital logic has been
reset (POR). This
includes the Wiper register.
Brown-out
condition,
Wiper value
unknown
Analog Power
is Low
Note: When VL is above V+ (floating), the VL pin ESD clamping diode will cause the V+ level to be pulled up.
rail/pin no longer sources current
to V+
MCP45HVX1
DS20005304A-page 30 2014 Microchip Technology Inc.
4.2.2 BROWN-OUT RESET
Each power system has its own independent Brown-
Out Reset circuitry. This is done so that regardless of
the power-down sequencing of the analog and digital
power rails, the wiper output will be forced to a default
value after the low-voltage conditions are met for either
power supply.
Table 4-4 shows the interaction between the analog
and digital BORs for the V+ and VL voltages on the
wiper pin state.
TABLE 4-4: WIPER PIN STATE BASED
ON BOR CONDITIONS
4.2.2.1 Digital Circuitry
When the device’s digital power supply powers-down,
the device VL pin voltage will cross the digital VDPOR/
VDBOR voltage.
Once the VL voltage decreases below the VDPOR/
VDBOR voltage, the following happens:
• Serial Interface is disabled
If the VL voltage decreases below the VRAM voltage,
the following happens:
• Volatile wiper registers may become corrupted
• TCON registers may become corrupted
Section 4.2.1, Power-on Reset describes what
occurs as the voltage recovers above the VDPOR/
VDBOR voltage.
Serial commands not completed due to a brown-out
condition may cause the memory location to become
corrupted.
The brown-out circuit establishes a minimum VDBOR
threshold for operation (VDBOR < 1.8V). The digital
BOR voltage (VDBOR) is higher than the RAM retention
voltage (VRAM) so that as the device voltage crosses
the digital BOR threshold, the value that is loaded into
the volatile Wiper register is not corrupted due to RAM
retention issues.
When VL < VDBOR, all communications are ignored and
potentiometer terminals are forced to the analog BOR
state.
Whenever VL transitions from VL < VDBOR to VL >
VDBOR, (a POR event) the wiper’s POR/BOR value is
latched into the Wiper register and the volatile TCON
register is forced to the POR/BOR state.
When 1.8V V
L, the device is capable of digital
operation.
Table 4-5 shows the digital potentiometer’s level of
functionality across the entire VL range, while
Figure 4-4 illustrates the Power-Up and Brown-Out
functionality.
4.2.2.2 Analog Circuitry
The Analog Brown-Out-Reset (ABOR) is the case
where the device’s V+ pin has power applied (refer-
enced from V-) and the V+ pin voltage drops below the
trip point. In this case, the resistor network terminal’s
pins can become an unknown state.
VL Voltage
V+ V oltage
Comments
V+ <
VABOR V+
VABOR
VL < VDBOR Unknown Mid Scale
VL VDBOR Unknown Wiper
Register
Value (1)
Wiper register
can be updated
Note 1: Default POR state of the Wiper register
value is the mid-scale value.
2014 Microchip Technology Inc. DS20005304A-page 31
MCP45HVX1
TABLE 4-5: DEVICE FUNCTIONALITY AT EACH VL REGION
FIGURE 4-4: Power-Up and Brown Out - V+/V- at Normal Operating Voltage.
VL Level V+/V- Level Serial
Interface Potentiometer
Terminals (2)
Wiper Comment
Register
Setting Output
(2)
VL < VDBOR < 1.8V Valid range Ignored “Unknown” Unknown Invalid
Invalid range Ignored “Unknown” Unknown Invalid
VDBOR VL < 1.8V Valid range “Unknown” Connected Volatile
Wiper Regis-
ter
initialized
Valid The volatile registers are
forced to the POR/BOR
state when VL transitions
above the VDPOR trip
point
Invalid range “Unknown” Connected Invalid
1.8V VL 5.5V Valid range Accepted Connected Volatile
Wiper Regis-
ter deter-
mines Wiper
Setting
Valid
Invalid range Accepted Connected Invalid
Note 1: For system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor
to hold the system in Reset. This ensures that MCP45HVX1 commands are not attempted out of the
operating range of the device.
2: Assumes that V+ > VAPOR.
VPOR/BOR
DGND
VLOutside Specified
Normal Operation Range
Device’s Serial
Wiper Forced to Default POR/BOR setting
VBOR Delay
Normal Operation Range
1.8V
Interface is
“Not Operational”
AC/DC Range
VRAM
Device’s
Interface is
“Not Specified”
Serial
MCP45HVX1
DS20005304A-page 32 2014 Microchip Technology Inc.
4.3 Control Module
The control module controls the following functionality:
•Shutdown
•Wiper Latch
4.3.1 SHUTDOWN
The MCP45HVX1 has two methods to disconnect the
terminal’s pins (P0A, P0W, and P0B) from the resistor
network. These are:
• Hardware Shutdown pin (SHDN)
• Terminal Control Register (TCON)
4.3.1.1 Hardware Shutdown Pin Operation
The SHDN pin has the same functionality as
Microchip’s family of standard voltage devices. When
the SHDN pin is Low, the P0A terminal will disconnect
(become open) while the P0W terminal simultaneously
connects to the P0B terminal (see Figure 4-5).
The Hardware Shutdown Pin mode does not corrupt
the volatile Wiper register. When Shutdown is exited,
the device returns to the wiper setting specified by the
volatile wiper value. See Section 5.7 for additional
description details.
FIGURE 4-5: Hardware Shutdown
Resistor Network Configuration.
4.3.1.2 Terminal Control Register
The Terminal Control (TCON) register allows the
device’s terminal pins to be independently removed
from the application circuit. These terminal control
settings do not modify the wiper setting values. Also,
this has no effect on the serial interface and the
memory/wipers are still under full user control.
The resistor network has four TCON bits associated
with it. One bit for each terminal (A, W, and B) and one
to have a software configuration that matches the
configuration of the SHDN pin. These bits are named
R0A, R0W, R0B, and R0HW. Register 4-1 describes
the operation of the R0HW, R0A, R0B, and R0W bits.
Figure 4-6 shows how the SHDN pin signal and the
R0HW bit signal interact to control the hardware
shutdown of each resistor network (independently).
FIGURE 4-6: R0HW bit and SHDN pin
Interaction.
Note: When the SHDN pin is Active (VIL), the
state of the TCON register bits is
overridden (ignored). When the state of
the SHDN pin returns to the Inactive state
(VIH), the TCON register bits return to
controlling the terminal connection state.
That is, the value in the TCON register is
not corrupted.
Note: When the SHDN pin is active, the serial
interface is not disabled, and serial inter-
face activity is executed.
A
B
W
Resistor Network
Note: When the R0HW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON register R0A, R0W,
and R0B bits is overridden (ignored).
When the state of the R0HW bit no longer
forces the resistor network into the
hardware SHDN state, the TCON register
R0A, R0W, and R0B bits return to
controlling the terminal connection state.
That is, the R0HW bit does not corrupt the
state of the R0A, R0W, and R0B bits.
2014 Microchip Technology Inc. DS20005304A-page 33
MCP45HVX1
4.3.2 WIPER LATCH
The wiper latch pin is used to control when the new
wiper value in the Wiper register is transferred to the
wiper. This is useful for applications that need to
synchronize the wiper updates. This may be for
synchronization to an external event, such as zero
crossing, or to synchronize the update of multiple
digital potentiometers.
When the WLAT pin is High, transfers from the Wiper
register to the wiper are inhibited. When the WLAT pin
is Low, transfers may occur from the Wiper register to
the wiper. Figure 4-7 shows the interaction of the WLAT
pin during an I2C command and the loading of the
wiper.
If the external event crossing time is long, then the
wiper could be updated the entire time that the WLAT
signal is Low. Once the WLAT signal goes High, the
transfer from the Wiper register is disabled. The Wiper
register can continue to be updated.
If the application does not require synchronized Wiper
register updates, then the WLAT pin should be tied
Low.
4.3.3 DEVICE CURRENT MODES
There are two current modes for volatile devices.
These are:
• Serial Interface Inactive (static operation)
• Serial Interface Active
For the I2C interface, static operation occurs when the
SDA and the SCL pins are static (High or Low).
Note 1: This feature only inhibits the data transfer
from the Wiper register to the wiper.
2: When the WLAT pin becomes active,
data transferred to the wiper will not be
corrupted due to the Wiper Register
Buffer getting loaded from an active I2C
command.
MCP45HVX1
DS20005304A-page 34 2014 Microchip Technology Inc.
FIGURE 4-7: WLAT Interaction with I2C ACK Pulse
I2C™ Slave Address + Write Command + Data (less ACK bit)
or
I2C Slave Address + Inc/Dec Command (less ACK bit)
ACK bit
ACK bitSDA
SCL
Wiper Latch
Stop bit
Wiper
WLAT
D[7:0]’ D[7:0]
Wiper Latch
WLAT
D[7:0]’ D[7:0]
D[7:0]’ D[7:0]Wiper
WLAT
Wiper Latch
D[7:0]’ D[7:0]
WLAT
D[7:0]’ D[7:0]
Wiper Latch
WLAT
D[7:0]
Wiper
WLAT
D[7:0]’ D[7:0]
D[7:0]’ D[7:0]Wiper
Wiper Latch
Wiper Latch
WLAT state lock range
(for WLAT rising edge)
Case 1a
Case 1b
Case 1c
Case 2a
Case 3a
Case 3b
D[7:0]’ D[7:0]
D[7:0]’ D[7:0]
D[7:0]’ D[7:0]
D[7:0]’ D[7:0]Wiper
WLAT
Wiper Latch
Case 2b
Wiper D[7:0]’ D[7:0]
D[7:0]’ D[7:0]Wiper
2014 Microchip Technology Inc. DS20005304A-page 35
MCP45HVX1
4.4 Memory Map
The device memory supports 16 locations that are 8-
bits wide (16x8 bits). This memory space contains only
volatile locations (see Ta b l e 4 - 7 ).
4.4.1 VOLATILE MEMORY (RAM)
There are two volatile memory locations. These are:
• Volatile Wiper 0
• Terminal Control (TCON0) Register 0
The volatile memory starts functioning at the RAM
retention voltage (VRAM). The POR/BOR wiper code is
shown in Tab le 4- 6.
Table 4-7 shows this memory map and which serial
commands operate (and do not) on each of these
locations.
Accessing an “invalid” address (for that device) or an
invalid command for that address will cause an error
condition on the serial interface. A Start bit is required
to clear this error condition.
4.4.1.1 Write to Invalid (Reserved)
Addresses
Any write to a reserved address will be ignored and will
generate an error condition. A Start bit is required to
clear this error condition.
TABLE 4-7: MEMORY MAP AND THE SUPPORTED COMMANDS
TABLE 4-6: WIPER REGISTER POR
STANDARD SETTINGS
(DIGITAL)
Resistance
Code Typical
RAB Value
Default
POR Wiper
Setting
Wiper
Code
8-bit 7-bit
-502 5.0 kMid scale 7Fh 3Fh
-103 10.0 kMid scale 7Fh 3Fh
-503 50.0 kMid scale 7Fh 3Fh
-104 100.0 kMid scale 7Fh 3Fh
Address Function Allowed Commands Disallowed Commands (1) Memory Type
00h Volatile Wiper 0 Read, Write,
Increment, Decrement
—RAM
01h-03h Reserved none Read, Write,
Increment, Decrement
—
04h Volatile
TCON Register
Read, Write Increment, Decrement RAM
05h-0Fh Reserved none Read, Write,
Increment, Decrement
—
Note 1: This command on this address will generate an error condition. A Start bit is required to clear this error
condition.
MCP45HVX1
DS20005304A-page 36 2014 Microchip Technology Inc.
4.4.1.2 Terminal Control (TCON) Registers
The Terminal Control (TCON) Register contains four
control bits for wiper 0. Register 4-1 describes each bit
of the TCON register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
The value that is written to this register will appear on
the resistor network terminals when the serial
command has completed.
On a POR/BOR, the registers are loaded with FFh, for
all terminals connected. The host controller needs to
detect the POR/BOR event and then update the volatile
TCON register values.
REGISTER 4-1: TCON0 BITS (1, 2)
R-1 R-1 R-1 R-1 R/W-1 R/W-1 R/W-1 R/W-1
D7 D6 D5 D4 R0HW R0A R0W R0B
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7:4 D7-D4: Reserved. Forced to “1”
bit 3 R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 0 is forced to the hardware pin “shutdown” configuration
bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1 = P0A pin is connected to the Resistor 0 Network
0 = P0A pin is disconnected from the Resistor 0 Network
bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1 = P0W pin is connected to the Resistor 0 Network
0 = P0W pin is disconnected from the Resistor 0 Network
bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1 = P0B pin is connected to the Resistor 0 Network
0 = P0B pin is disconnected from the Resistor 0 Network
Note 1: These bits do not affect the Wiper register values.
2: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the
inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the
state of the TCON bits.
2014 Microchip Technology Inc. DS20005304A-page 37
MCP45HVX1
NOTES:
MCP45HVX1
DS20005304A-page 38 2014 Microchip Technology Inc.
5.0 RESISTOR NETWORK
The resistor network has either 7-bit or 8-bit resolution.
Each resistor network allows zero-scale to full-scale
connections. Figure 5-1 shows a block diagram for the
resistive network of a device. The resistor network has
up to three external connections. These are referred to
as Terminal A, Terminal B, and the wiper (or Terminal
W).
The resistor network is made up of several parts. These
include:
•Resistor Ladder Module
•Wiper
•Shutdown Control (terminal connections)
Terminal A and B as well as the wiper W do not have a
polarity. These terminals can support both positive and
negative current.
FIGURE 5-1: Resistor Block Diagram.
5.1 Resistor Ladder Module
The RAB resistor ladder is composed of the series of
equal value Step resistors (RS) and the Full-Scale
(RFS) and Zero-Scale (RZS) resistances:
RAB = RZS + n * RS + RFS
Where “n” is determined by the resolution of the device.
The RFS and RZS resistances are discussed in
Section 5.1.3.
There is a connection point (tap) between each RS
resistor. Each tap point is a connection point for an
analog switch. The opposite side of the analog switch
is connected to a common signal which is connected to
the Terminal W (wiper) pin (see Section 5.2).
Figure 5-1 shows a block diagram of the Resistor
Network. The RAB (and RS) resistance has small
variations over voltage and temperature.
The end points of the resistor ladder are connected to
analog switches, which are connected to the device
Terminal A and Terminal B pins. In the ideal case, these
switches would have 0 of resistance, that is
RFS =R
ZS =0. This will also be referred to as the
Simplified model.
For an 8-bit device, there are 255 resistors in a string
between Terminal A and Terminal B. The wiper can be
set to tap onto any of these 255 resistors, thus provid-
ing 256 possible settings (including Terminal A and
Terminal B). A wiper setting of 00h connects Terminal
W (wiper) to Terminal B (zero scale). A wiper setting of
7Fh is the mid-scale setting. A wiper setting of FFh con-
nects Terminal W (wiper) to Terminal A (full scale).
Table 5-2 illustrates the full wiper setting map.
For a 7-bit device, there are 127 resistors in a string
between Terminal A and Terminal B. The wiper can be
set to tap onto any of these 127 resistors, thus provid-
ing 128 possible settings (including Terminal A and
Terminal B). A wiper setting of 00h connects Terminal
W (wiper) to Terminal B (zero scale). A wiper setting of
3Fh is the mid-scale setting. A wiper setting of 7Fh con-
nects the wiper to Terminal A (full scale). Table 5-2
illustrates the full wiper setting map.
5.1.1 RAB CURRENT (IRAB)
The current through the RAB resistor (A pin to B pin) is
dependent on the voltage on the VA and VB pins and
the RAB resistance.
EQUATION 5-1: RAB
2014 Microchip Technology Inc. DS20005304A-page 39
MCP45HVX1
5.1.2 STEP RESISTANCE (RS)
Step resistance (RS) is the resistance from one tap set-
ting to the next. This value will be dependent on the
RAB value that has been selected (and the full-scale
and zero-scale resistances). The RS resistors are
manufactured so that they should be very consistent
with each other, and track each other’s values as
voltage and/or temperature change.
Equation 5-2 shows the simplified and detailed equa-
tions for calculating the RS value. The simplified equa-
tion assumes RFS =R
ZS =0. Ta b l e 5 - 1 shows
example step resistance calculations for each device,
and the variation of the detailed model (RFS 0;
RZS 0) from the simplified model (RFS =R
ZS = 0).
As the RAB resistance option increases, the effects of
the RZS and RFS resistance decreases.
The total resistance of the device has minimal variation
due to operating voltage (see device characterization
graphs).
Equation 5-2 shows calculations for the step
resistance.
EQUATION 5-2: RS CALCULATION
TABLE 5-1: EXAMPLE STEP RESISTANCES (RS) CALCULATIONS
Example Resistance ()Variation
% (1) Resolution Comment
RAB RZS (3) R
FS (3) RS
Equation Value
5,000
0 0 5,000 / 127 39.37 0 7-bit
(127 RS)
Simplified Model (2)
80 60 4,860 / 127 38.27 -2.80
0 0 5,000 / 255 19.61 0 8-bit
(255 RS)
Simplified Model (2)
80 60 4,860 / 255 19.06 -2.80
10,000
0 0 10,000 / 127 78.74 0 7-bit
(127 RS)
Simplified Model (2)
80 60 9,860 / 127 77.64 -1.40
0 0 10,000 / 255 39.22 0 8-bit
(255 RS)
Simplified Model (2)
80 60 9,860 / 255 38.67 -1.40
50,000
0 0 50,000 / 127 393.70 0 7-bit
(127 RS)
Simplified Model (2)
80 60 49,860 / 127 392.60 -0.28
0 0 50,000 / 255 196.08 0 8-bit
(255 RS)
Simplified Model (2)
80 60 49,860 / 255 195.53 -0.28
100,000
0 0 100,000 / 127 787.40 0 7-bit
(127 RS)
Simplified Model (2)
80 60 99,860 / 127 786.30 -0.14
0 0 100,000 / 255 392.16 0 8-bit
(255 RS)
Simplified Model (2)
80 60 99,860 / 255 391.61 -0.14
Note 1: Delta % from Simplified Model RS calculation value:
2: Assumes RFS =R
ZS =0.
3: Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of
the device, including the V+/V- voltage, the voltages on the A, B and W terminals, the wiper code selected,
the RAB resistance, and the temperature of the device.
MCP45HVX1
DS20005304A-page 40 2014 Microchip Technology Inc.
5.1.3 RFS AND RZS RESISTORS
The RFS and RZS resistances are artifacts of the RAB
resistor network implementation. In the ideal model, the
RFS and RZS resistances would be 0. These resistors
are included in the block diagram to help better model
the actual device operation. Equation 5-3 shows how to
estimate the RS, RFS, and RZS resistances, based on
the measured voltages of VAB, VFS, and VZS and the
measured current IAB.
EQUATION 5-3: ESTIMATING RS, RFS,
AND RZS
5.2 Wiper
The Wiper terminal is connected to an analog switch
MUX, where one side of all the analog switches are
connected together, the W terminal. The other side of
each analog switch is connected to one of the taps of
the RAB resistor string (see Figure 5-1).
The value in the volatile Wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder. The Wiper
register is 8-bits wide, and Tabl e 5-2 shows the wiper
value state for both 7-bit and 8-bit devices.
The wiper resistance (RW) is the resistance of the
selected analog switch in the analog MUX. This
resistance is dependent on many operational
characteristics of the device, including the V+/V- volt-
age, the voltages on the A, B and W terminals, the
wiper code selected, the RAB resistance, and the tem-
perature of the device.
When the wiper value is at zero scale (00h), the wiper
is connected closest to the B terminal. When the wiper
value is at full scale (FFh for 8-bit, 7Fh for 7-bit), the
wiper is connected closest to the A terminal.
A zero-scale wiper value connects the W terminal
(wiper) to the B terminal (wiper = 00h). A full-scale
wiper value connects the W terminal (wiper) to the A
terminal (wiper = FFh (8-bit), or wiper = 7Fh (7-bit)). In
these configurations, the only resistance between the
Terminal W and the other terminal (A or B) is that of the
analog switches.
TABLE 5-2: VOLATILE WIPER VALUE VS.
WIPER POSITION
Wiper Setting Properties
7-bit 8-bit
7Fh FFh Full Scale (W = A), Increment
commands ignored
7Eh-40h FEh-80h W = N
3Fh 7Fh W = N (Mid Scale)
3Eh-01h 7Eh-01h W = N
00h 00h Zero Scale (W = B)
Decrement command
ignored
2014 Microchip Technology Inc. DS20005304A-page 41
MCP45HVX1
5.2.1 WIPER RESISTANCE (RW)
Wiper resistance is significantly dependent on:
• The Resistor Network’s Supply Voltage (VRN)
• The Resistor Network’s Terminal (A, B, and W)
Voltages
• Switch leakage (occurs at higher temperatures)
•I
W current
Figure 5-2 show the wiper resistance characterization
data for all four RAB resistances and temperatures.
Each RAB resistance determined the maximum wiper
current based on worst-case conditions
RAB =R
AB maximum and at full-scale code, VBW ~= V+
(but not exceeding V+). The V+ targets were 10V, 20V,
and 36V. What this graph shows is that at higher RAB
resistances (50 k and 100 k) and at the highest tem-
perature (+125°C), the analog switch leakage causes
an increase in the measured result of RW, where RW is
measured in a rheostat configuration with RW = (VBW -
VBA) / IBW.
FIGURE 5-2: RW Resistance vs R AB,
Wiper Current (IW), Temperature and Wiper
Code.
Since there is minimal variation of the total device
resistance (RAB) over voltage, at a constant tempera-
ture (see device characterization graphs), the change
in wiper resistance over voltage can have a significant
impact on the RINL and RDNL errors.
5.2.2 POTENTIOMETER
CONFIGURATION
In a potentiometer configuration, the wiper resistance
variation does not affect the output voltage seen on the
W pin and therefore is not a significant source of error.
5.2.3 RHEOSTAT CONFIGURATION
In a rheostat configuration, the wiper resistance varia-
tion creates nonlinearity in the RBW (or RAW) value. The
lower the nominal resistance (RAB), the greater the
possible relative error. Also, a change in voltage needs
to be taken into account. For the 5.0 k device, the
maximum wiper resistance at 5.5V is approximately 6%
of the total resistance, while at 2.7V it is approximately
6.5% of the total resistance.
5.2.4 LEVEL SHIFTERS
(DIGITAL TO ANALOG)
Since the digital logic may operate anywhere within the
analog power range, level shifters are present so that
the digital signals control the analog circuitry. This level
shifter logic is relative to the V- and VL voltages. A delta
voltage of 2.7V between VL and V- is required for the
serial interface to operate at the maximum specified
frequency.
800
1000
1200
1400
1600
1800
2000
2200
2400
e
sistance R
W
(:)
Ͳ40C5kIW=1.7mA +25C5kIW=1.7mA +85C5kIW=1.7mA +125C5kIW=1.7mA
Ͳ40C5kIW=3.3mA +25C5kIW=3.3mA +85C5kIW=3.3mA +125C5kIW=3.3mA
Ͳ40C5kIW=6.0mA +25C5kIW=6.0mA +85C5kIW=6.0mA +125C5kIW=6.0mA
Ͳ40C10kIW=830uA +25C10kIW=830uA +85C10kIW=830uA +125C10kIW=830uA
Ͳ40C10kIW=1.7mA +25C10kIW=1.7mA +85C10kIW=1.7mA +125C10kIW=1.7mA
Ͳ40C10kIW=3.0mA +25C10kIW=3.0mA +85C10kIW=3.0mA +125C10kIW=3.0mA
Ͳ40C50kIW=170uA +25C50kIW=170uA +85C50kIW=170uA +125C50kIW=170uA
Ͳ40C50kIW=330uA +25C50kIW=330uA +85C50kIW=330uA +125C50kIW=330uA
Ͳ40C50kIW=600uA +25C50kIW=600uA +85C50kIW=600uA +125C50kIW=600uA
Ͳ40C100kIW=83uA +25C100kIW=83uA +85C100kIW=83uA +125C100kIW=83uA
Ͳ40C100kIW=170uA +25C100kIW=170uA +85C100kIW=170uA +125C100kIW=170uA
Ͳ40C100kIW=300uA +25C100kIW=300uA +85C100kIW=300uA +125C100kIW=300uA
IW=83uA,+125C(100k:)Increasedwiperresistance(RW)occurs
duetoincreasedanalog switchleakage at
highertemperatures(suchas+125C)and
larger R
resistances
0
200
400
600
800
0 32 64 96 128 160 192 224 256
Wiper R
e
DAC Wiper Code
IW=170uA,+125C(100k:)
IW=170uA,+125C(50k:)
IW=300uA,+125C(100k:)
larger
R
AB
resistances
.
MCP45HVX1
DS20005304A-page 42 2014 Microchip Technology Inc.
5.3 Terminal Curr ents
The terminal currents are limited by several factors,
including the RAB resistance (RS resistance). The
maximum current occurs when the wiper is at either the
zero-scale (IBW) or full-scale (IAW) code. In this case,
the current is only going through the analog switches
(see IT specification in Electrical Characteristics).
When the current passes through at least one RS
resistive element, then the maximum terminal current
(IT) has a different limit. The current through the RAB
resistor is limited by the RAB resistance. The worst
case (max current) occurs when the resistance is at the
minimum RAB value.
Higher current capabilities allow a greater delta voltage
between the desired terminals for a given resistance.
This also allows a more usable range of wiper code val-
ues, without violating the maximum terminal current
specification. Table 5 - 3 shows resistance and current
calculations based on the RAB resistance (RS resis-
tance) for a system that supports ± 18V ( 36V). In
Rheostat configuration, the minimum wiper code value
is shown (for VBW = 36V). As the VBW voltage
decreases, the minimum wiper code value also
decreases. Using a wiper code less then this value will
cause the maximum terminal current (IT) specification
to be violated.
TABLE 5-3: TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)
Note: For high terminal-current applications, it is
recommended that proper PCB layout
techniques be used to address the ther-
mal implications of this high current. The
QFN package has better thermal proper-
ties than the TSSOP package.
RAB Resistance ()R
S(MIN) ()
IAB(MAX) (mA)
(= 36V / RAB(MIN) ) (1)
IT (A, B, or W (IW) ) (mA)
(IBW(W = Z S), IAW(W = FS) (1)
RBW ()
(= 36V / IT(MAX) ) (2)
Rheostat
Min ‘N’
when VBW = 36V
N * RS(MIN) * 36V
 IT (mA) (3)
Rheostat
VBW(MAX) When
Wiper = 01h (V)
(= IT(MAX) * RS(MIN) )
Typical Min Max 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit
5,000 4,000 6,000 15.686 31.496 9.00 25.0 1,440 91 45 0.392 0.787
10,000 8,000 12,000 31.373 62.992 4.50 12.5 2,880 91 45 0.392 0.787
50,000 40,000 60,000 156.863 314.961 0.90 6.5 5539 35 17 1.020 2.047
100,000 80,000 120,000 313.725 629.9 0.45 6.5 5539 17 8 2.039 4.094
Note 1: IBW or IAW currents can be much higher than this depending on voltage differential between Terminal B and
Terminal W or Terminal A and Terminal W.
2: Any RBW resistance greater than this limits the current.
3: If VBW = 36V, then the wiper code value must be greater than or equal to Min ‘N’. Wiper codes less than
Min ‘N’ will cause the wiper current (IW) to exceed the specification. Wiper codes greater than Min ‘N’ will
cause the wiper current to be less than the maximum. The Min ‘N’ number has been rounded up from the
calculated number to ensure that the wiper current does not exceed the maximum specification.
2014 Microchip Technology Inc. DS20005304A-page 43
MCP45HVX1
Figure 5-3 through Figure 5-6 show a graph of the cal-
culated currents (minimum, typical, and maximum) for
each resistor option. These graphs are based on
25 mA (5 k), 12.5 mA (10 k), and 6.5 mA (50 k
and 100 k) specifications.
To ensure no damage to the resistor network (including
long-term reliability) the maximum terminal current
must not be exceeded. This means that the application
must assume that the RAB resistance is the minimum
RAB value (RAB(MIN), see blue lines in graphs).
Looking at the 50 k device, the maximum terminal
current is 6.5 mA. That means that any wiper code
value greater than 36 ensures that the terminal current
is less than 6.5 mA. This is ~14% of the full-scale value.
If the application could change to the 100 k device,
which has the same maximum terminal current specifi-
cation, any wiper code value greater than 18 ensures
that the terminal current is less than 6.5 mA. This is
~7% of the full-scale value. Supporting higher terminal
current allows a greater wiper code range for a given
VBW voltage.
FIGURE 5-3: Maximum IBW vs Wiper
Code - 5 k
.
FIGURE 5-4: Maximum IBW vs Wiper
Code - 10 k
.
FIGURE 5-5: Maximum IBW vs Wiper
Code - 50 k
.
FIGURE 5-6: Maximum IBW vs Wiper
Code - 100 k
.
Figure 5-7 shows a graph of the maximum VBW voltage
vs wiper code (for 5 k and 10 k devices). To ensure
that no damage is done to the resistor network, the
RAB(MIN) resistance (blue line) should be used to deter-
mine VBW voltages for the circuit. Devices where the
RAB resistance is greater than the RAB(MIN) resistance
will naturally support a higher voltage limit.
FIGURE 5-7: Maximum VBW vs Wiper
Code (5 k
and 10 k
devices).
:
A
A
:
A
A
50E
3
A
20E
3
Wiper Code
50E
3
A
20E
3
AB(MAX)
Wiper Code
A
MCP45HVX1
DS20005304A-page 44 2014 Microchip Technology Inc.
Table 5-4 shows the maximum VBW voltage that can be
applied across the Terminal B to Terminal W pins for a
given wiper code value (for the 5 k and 10 k
devices). These calculations assume the ideal model
(RW=R
FS =R
ZS =0) and show the calculations
based on RS(MIN) and RS(MAX). Table 5 -5 shows the
same calculations for the 50 k devices, and Table 5-6
shows the calculations for the 100 k devices. These
tables are supplied as a quick reference.
TABLE 5-4: MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FO R V+ - V- = 36V,
5K AND 10 K DEVICES
Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)
Hex Dec RS(MIN) R
S(MAX) Hex Dec RS(MIN) R
S(MAX) Hex Dec RS(MIN) R
S(MAX)
00h 0 0.000 0.000 20h 32 12.549 18.824 40h 64 25.098
01h 1 0.392 0.588 21h 33 12.941 19.412 41h 65 25.490
02h 2 0.784 1.176 22h 34 13.333 20.000 42h 66 25.882
03h 3 1.176 1.765 23h 35 13.725 20.588 43h 67 25.275
04h 4 1.569 2.353 24h 36 14.118 21.176 44h 68 26.667
05h 5 1.961 2.941 25h 37 14.510 21.765 45h 69 27.059
06h 6 2.353 3.529 26h 38 14.902 22.353 46h 70 27.451
07h 7 2.745 4.118 27h 39 15.294 22.941 47h 71 27.843
08h 8 3.137 4.706 28h 40 15.686 23.529 48h 72 28.235
09h 9 3.529 5.294 29h 41 16.078 24.118 49h 73 28.627
0Ah 10 3.922 5.882 2Ah 42 16.471 24.706 4Ah 74 29.020
0Bh 11 4.314 6.471 2Bh 43 16.863 25.294 4Bh 75 29.412
0Ch 12 4.706 7.059 2Ch 44 17.255 25.882 4Ch 76 29.804
0Dh 13 5.098 7.647 2Dh 45 17.647 26.471 4Dh 77 30.196
0Eh 14 5.490 8.235 2Eh 46 18.039 27.059 4Eh 78 30.588
0Fh 15 5.882 8.824 2Fh 47 18.431 27.647 4Fh 79 30.980
10h 16 5.275 9.412 30h 48 18.824 28.235 50h 80 31.373
11h 17 6.667 10.000 31h 49 19.216 28.824 51h 81 31.765
12h 18 7.059 10.588 32h 50 19.608 29.412 52h 82 32.157
13h 19 7.451 11.176 33h 51 20.000 30.000 53h 83 32.549
14h 20 7.843 11.765 34h 52 20.392 30.588 54h 84 32.941
15h 21 8.235 12.353 35h 53 20.784 31.176 55h 85 33.333
16h 22 8.627 12.941 36h 54 21.176 31.765 56h 86 33.725
17h 23 9.020 13.529 37h 55 21.569 32.353 57h 87 34.118
18h 24 9.412 14.118 38h 56 21.961 32.941 58h 88 34.510
19h 25 9.804 14.706 39h 57 22.353 33.529 59h 89 34.902
1Ah 26 10.196 15.294 3Ah 58 22.745 34.118 5Ah 90 35.294
1Bh 27 10.588 15.882 3Bh 59 23.137 34.706 5Bh 91 35.686
1Ch 28 10.980 16.471 3Ch 60 23.529 35.294 5Ch 92 - 255 36.0 (1, 2)
1Dh 29 11.373 17.059 3Dh 61 23.922 35.882
1Eh 30 11.765 17.647 3Eh 62 24.314 36.0 (1, 2)
1Fh 31 12.157 18.235 3Fh 63 24.706
Note 1: Calculated RBW voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-).
2: This wiper code and greater will limit the IBW current to less than the maximum supported terminal
current (IT).
2014 Microchip Technology Inc. DS20005304A-page 45
MCP45HVX1
TABLE 5-5: MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FO R V+ - V- = 36V,
50 K DEVICES
TABLE 5-6: MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FO R V+ - V- = 36V,
100 K DEVICES
Code VBW(MAX) Code VBW(MAX) Code VBW(MAX)
Hex Dec RS(MIN) R
S(MAX) Hex Dec RS(MIN) R
S(MAX) Hex Dec RS(MIN) RS(MA
X)
00h 0 0.000 0.000 10h 16 16.314 24,471 20h 32 32.627
01h 1 1.020 1.529 11h 17 17.333 26.000 21h 33 33.647
02h 2 2.039 3.059 12h 18 18.353 27.529 22h 34 34.667
03h 3 3.059 4.588 13h 19 19.373 29.059 23h 35 35.686
04h 4 4.078 6.118 14h 20 20.392 30.588 24h - FFh 36 - 255 36.0 (1, 2)
05h 5 5.098 7.647 15h 21 21.412 32.118
06h 6 6.118 9.176 16h 22 22.431 33.647
07h 7 7.137 10.706 17h 23 23.451 35.176
08h 8 8.157 12.235 18h 24 24.471 36.0 (1, 2)
09h 9 9.176 13.765 19h 25 25.490
0Ah 10 10.196 15.294 1Ah 26 26.510
0Bh 11 11.216 16.824 1Bh 27 27.529
0Ch 12 12.235 18.353 1Ch 28 28.549
0Dh 13 13.255 19.882 1Dh 29 29.569
0Eh 14 14.275 21.412 1Eh 30 30.588
0Fh 15 15.294 22.941 1Fh 31 31.608
Note 1: Calculated RBW voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-).
2: This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT).
Code VBW(MAX) Code VBW(MAX)
Hex Dec RS(MIN) R
S(MAX) Hex Dec RS(MIN) R
S(MAX)
00h 0 0.000 0.000 10h 16 32.627
01h 1 2.039 3.059 11h 17 34.667
02h 2 4.078 6.118 12h - FFh 18 - 255 36.0 (1, 2)
03h 3 6.118 9.176
04h 4 8.157 12.235
05h 5 10.196 15.294
06h 6 12.235 18.353
07h 7 14.275 21.412
08h 8 16.314 24.471
09h 9 18.353 27.529
0Ah 10 20.392 30.588
0Bh 11 22.431 33.647
0Ch 12 24.471 36.0 (1, 2)
0Dh 13 26.510
0Eh 14 28.549
0Fh 15 30.588
Note 1: Calculated RBW voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-).
2: This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT).
MCP45HVX1
DS20005304A-page 46 2014 Microchip Technology Inc.
5.4 Variable Resistor (Rheostat)
A variable resistor is created using Terminal W and
either Terminal A or Terminal B. Since the wiper code
value of 0 connects the wiper to the Terminal B, the
RBW resistance increases with increasing wiper code
value. Conversely, the RAW resistance will decrease
with increasing wiper code value. Figure 5-8 shows the
connections from a potentiometer to create a rheostat
configuration.
FIGURE 5-8: Rheostat Configuration.
Equation 5-4 shows the RBW and RAW calculations.
The RBW calculation is for the resistance between the
wiper and Terminal B. The RAW calculation is for the
resistance between the wiper and Terminal A.
EQUATION 5-4: RBW AND RAW
CALCULATION
5.5 Analog Circuitry Power
Requirements
This device has two power supplies. One is for the
digital interface (VL and DGND) and the other is for the
high-voltage analog circuitry (V+ and V-). The
maximum delta voltage between V+ and V- is 36V. The
digital power signals must be between V+ and V-.
If the digital ground (DGND) pin is at half the potential
of V+ (relative to V-), then the terminal pins potentials
can be ±(V+/2) relative to DGND.
Figure 5-9 shows the relationship of the four power sig-
nals. This shows that the V+/V- signals do not need to
be symmetric around the DGND signal.
To ensure that the Wiper register has been properly
loaded with the POR/BOR value, the VL voltage must
be at the minimum specified operating voltage (refer-
enced to DGND).
FIGURE 5-9: Analog Circuitry Voltage
Ranges.
5.6 Resistor Characteristics
5.6.1 V+/V- LOW VOLTAGE OPERATION
The resistor network is specified from 20V to 36V. At
voltages below 20V, the resistor network will function,
but the operational characteristics may be outside the
specified limits. Please refer to Section 2.0 “Typical
Performance Curves” for additional information.
5.6.2 RESISTOR TEMPCO
Biasing the ends (Terminal A and Terminal B) near mid-
supply ((V+ - |V-|) / 2) will give the worst switch
resistance temperature coefficient (tempco).
2014 Microchip Technology Inc. DS20005304A-page 47
MCP45HVX1
5.7 Shutdown Control
Shutdown is used to minimize the device’s current
consumption. The MCP45HVX1 has two methods to
achieve this:
•Hardware Shutdown Pin (SHDN)
•Terminal Control Register (TCON)
The Hardware Shutdown pin is backwards compatible
with the MCP42X1 devices.
5.7.1 HARDWARE SHUTDOWN PIN
(SHDN)
The SHDN pin is available on the potentiometer
devices. When the SHDN pin is forced active (VIL):
• The P0A terminal is disconnected
• The P0W terminal is connected to the P0B termi-
nal (see Figure 4-5)
• The Serial Interface is NOT disabled, and all
Serial Interface activity is executed
The Hardware Shutdown Pin mode does NOT corrupt
the values in the volatile wiper registers nor the TCON
register. When the Shutdown mode is exited (SHDN
pin is inactive (VIH)):
• The device returns to the wiper setting specified
by the volatile wiper value
• The TCON register bits return to controlling the
terminal connection state
FIGURE 5-10: Hardware Shutdown
Resistor Network Configuration.
5.7.2 TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B and W) to the
Resistor Network. This register is shown in Register 4-1.
The R0HW bit forces the selected resistor network into
the same state as the SHDN pin. Alternate low-power
configurations may be achieved with the R0A, R0W
and R0B bits.
When the R0HW bit is “0”:
• The P0A terminal is disconnected
• The P0W terminal is simultaneously connected to
the P0B terminal (see Figure 5-11)
The R0HW bit does NOT corrupt the values in the
volatile wiper registers nor the TCON register. When
the Shutdown mode is exited (R0HW bit = 1):
• The device returns to the wiper setting specified
by the volatile wiper value
• The TCON register bits return to controlling the
terminal connection state
FIGURE 5-11: Resistor Network Shutdown
State (R0HW = 0).
5.7.3 INTERACTION OF SHDN PIN AND
TCON REGISTER
Figure 5-12 shows how the SHDN pin signal and the
R0HW bit signal interact to control the hardware
shutdown of the resistor network.
FIGURE 5-12: R0HW bit and SHDN pin
Interaction.
A
B
W
Resistor Network
Note: When the R0HW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON0 register’s R0A,
R0W and R0B bits is overridden (ignored).
When the state of the R0HW bit no longer
forces the resistor network into the
hardware SHDN state, the TCON0
register’s R0A, R0W and R0B bits return
to controlling the terminal connection
state. In other words, the R0HW bit does
not corrupt the state of the R0A, R0W and
R0B bits.
A
B
W
Resistor Network
MCP45HVX1
DS20005304A-page 48 2014 Microchip Technology Inc.
6.0 SERIAL INTERFACE (I2C)
The MCP45HVX1 devices support the I2C serial
protocol. The MCP45HVX1 I2C module operates in
Slave mode (does not generate the serial clock).
Figure 6-1 shows a typical I2C interface connection.
The MCP45HVX1 devices use the two-wire I2C serial
interface. This interface can operate in Standard, Fast
or High-Speed mode. A device that sends data onto the
bus is defined as transmitter, and a device receiving
data as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the Start and
Stop conditions. The MCP45HVX1 device works as
slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated. Communication is
initiated by the master (microcontroller) which sends
the Start bit, followed by the slave address byte. The
first byte transmitted is always the slave address byte,
which contains the device code, the address bits, and
the R/W bit.
Refer to the NXP I2C document for more details of the
I2C specifications (UM10204, Ver. 05 Oct 2012).
FIGURE 6-1: Typical I2C Interface Block
Diagram.
6.1 Signal Descriptions
The I2C interface uses up to four pins (signals). These
are:
• SDA (Serial Data)
• SCL (Serial Clock)
• A0 (Address 0 bit)
• A1 (Address 1 bit)
6.1.1 SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the Start and Stop conditions, the
High or Low state of the SDA pin can only change when
the clock signal on the SCL pin is Low. During the High
period of the clock, the SDA pin’s value (High or Low)
must be stable. Changes in the SDA pin’s value while
the SCL pin is High will be interpreted as a Start or a
Stop condition.
6.1.2 SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin. The MCP45HVX1 supports three
I2C interface clock modes:
• Standard mode: clock rates up to 100 kHz
• Fast mode: clock rates up to 400 kHz
• High-Speed mode (HS mode): clock rates up to
3.4 MHz
The MCP45HVX1 will not stretch the clock signal (SCL)
since memory read access occurs fast enough.
Depending on the clock rate mode, the interface will
display different characteristics.
6.1.3 THE ADDRESS BITS (A1:A0)
There are up to two hardware pins used to specify the
device address. The number of address pins is
determined by the part number.
The state of the A0 and A1 pins should be static, that is
they should be tied High or tied Low.
SCL
SCL
MCP4XXX
SDA
SDA
A0 (1)
I/O (1)
Host
Controller
Typical I2C™ Interface Connections
Note 1: This pin could be tied High, Low, or
connected to an I/O pin of the Host
Controller.
A1 (1)
I/O (1)
2014 Microchip Technology Inc. DS20005304A-page 49
MCP45HVX1
6.2 I2C Operation
The MCP45HVX1 I2C module is compatible with the
NXP I2C specification. The following lists some of the
module’s features:
• 7-bit slave addressing
• Supports three clock rate modes:
- Standard mode, clock rates up to 100 kHz
- Fast mode, clock rates up to 400 kHz
- High-Speed mode (HS mode), clock rates up
to 3.4 MHz
• Support Multi-Master Applications
• General call addressing
The I2C 10-bit addressing mode is not supported.
The NXP I2C specification only defines the field types,
field lengths, timings, etc. of a frame. The frame con-
tent defines the behavior of the device. The frame con-
tent for the MCP45HVX1 is defined in Section 7.0.
6.2.1 I2C BIT STATES AND SEQUENCE
Figure 6-8 shows the I2C transfer sequence. The serial
clock is generated by the master. The following defini-
tions are used for the bit states:
• Start bit (S)
• Data bit
• Acknowledge (A) bit (driven Low)/
No Acknowledge (A) bit (not driven Low)
• Repeated Start bit (Sr)
• Stop bit (P)
6.2.1.1 Start Bit
The Start bit (see Figure 6-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 6-2: Start Bit.
6.2.1.2 Data Bit
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 6-3).
FIGURE 6-3: Data Bit.
6.2.1.3 Acknowledge (A) Bit
The A bit (see Figure 6-4) is typically a response from
the receiving device to the transmitting device.
Depending on the context of the transfer sequence, the
A bit may indicate different things. Typically, the slave
device will supply an A response after the Start bit and
8 “data” bits have been received. an A bit has the SDA
signal Low.
FIGURE 6-4: Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal High. Table 6 -1 shows
some of the conditions where the slave device will
issue a Not A (A).
If an error condition occurs (such as an A instead of A),
then a Start bit must be issued to reset the command
state machine.
TABLE 6-1: MCP45HVX1 A/A RESPONSES
SDA
SCL
S
1st Bit 2nd Bit
SDA
SCL
Data Bit
1st Bit 2nd Bit
Event Acknowledge
Bit
Response Comment
General Call A Only if GCEN bit is
set
Slave Address
valid
A
Slave Address
not valid
A
Device Mem-
ory Address
and specified
command
(AD3:AD0 and
C1:C0) are an
invalid combi-
nation
AAfter device has
received address
and command
Bus Collision N.A. I2C™ module
resets, or a “don’t
care” if the colli-
sion occurs on the
master’s “Start bit”
A
8
D0
9
SDA
SCL
MCP45HVX1
DS20005304A-page 50 2014 Microchip Technology Inc.
6.2.1.4 Repeated Start Bit
The Repeated Start bit (see Figure 6-5) indicates the
current master device will attempt to continue commu-
nicating with the current slave device without releasing
the I2C bus. The Repeated Start condition is the same
as the Start condition, except that the Repeated Start
bit follows a Start bit (with the Data bits + A bit) and not
a Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 6-5: Repeat Start Condition
Waveform.
6.2.1.5 Stop Bit
The Stop bit (see Figure 6-6) indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of all MCP45HVX1
devices.
FIGURE 6-6: Stop Condition Receive or
Transmit Mode.
6.2.2 CLOCK STRETCHING
“Clock Stretching” is something that the receiving
device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP45HVX1 will not stretch the clock signal (SCL)
since memory read access occurs fast enough.
6.2.3 ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a Start or Stop condition. This is
done so that noisy transmissions (usually an extra Start
or Stop condition) are aborted before they corrupt the
device.
FIGURE 6-7: Typi c al 8-Bi t I2C Waveform Format.
FIGURE 6-8: I2C Data States and Bit Sequence.
Note 1: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled Low when SCL
goes from low-to-high.
• SCL goes Low before SDA is
asserted Low. This may indicate
that another master is attempting to
transmit a data ‘1’.
SDA
SCL
Sr = Repeated Start
1st Bit
SCL
SDA A / A
P
1st Bit
SDA
SCL
S2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit PA / A
SCL
SDA
Start
Condition Stop
Condition
Data allowed
to change
Data or
A valid
2014 Microchip Technology Inc. DS20005304A-page 51
MCP45HVX1
6.2.4 ADDRESSING
The address byte is the first byte received following the
Start condition from the master device. The address
contains four (or more) fixed bits and (up to) three user-
defined hardware address bits (pins A1 and A0). These
7-bits address the desired I2C device. The A6:A2
address bits are fixed to ‘01111’ and the device
appends the value of following two address pins (A1
and A0).
Since there are address bits controlled by hardware
pins, there may be up to four MCP45HVX1 devices on
the same I2C bus.
Figure 6-9 shows the slave address byte format, which
contains the seven address bits. There is also a read/
write (R/W) bit. Tab l e 6 -2 shows the fixed address for
device.
Hardware Address Pins
The hardware address bits (A1, and A0) correspond to
the logic level on the associated address pins. This
allows up to four devices on the bus.
FIGURE 6-9: Slave Address Bits in the
I2C Control Byte.
TABLE 6-2: DEVICE SLAVE ADDRESSES
6.2.5 SLOPE CONTROL
The MCP45HVX1 implements slope control on the
SDA output.
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmitt trigger at SDA
and SCL inputs.
Device Address Comment
MCP45HVX1 ‘0111 1’b + A1:A0 Supports up to
4 devices.
(Note 1)
Note 1: The fixed portion of the I2C address is dif-
ferent than the MCP44XX/MCP45XX/
MCP46XX family (‘0101 11’, ‘0101 1’,
or ‘0101’). This allows the maximum num-
ber of both standard and high-voltage
devices on the single I2C bus.
SA6A5A4A3A2A1 A0 R/W A/A
Start
bit
Slave Address
R/W bit
A bit (controlled by slave device)
R/W = 0 = write
R/W = 1 = read
A = 0 = Slave device Acknowledges byte
A = 1 = Slave device does not Acknowledge byte
“0” “1” “1” “1”See Table 6-2
“1”
MCP45HVX1
DS20005304A-page 52 2014 Microchip Technology Inc.
6.2.6 HS MODE
The I2C specification requires that a High-Speed mode
device must be ‘activated’ to operate in High-Speed
(3.4 Mbit/s) mode. This is done by the master sending
a special address byte following the Start bit. This byte
is referred to as the High-Speed Master Mode Code
(HSMMC).
The MCP45HVX1 device does not acknowledge this
byte. However, upon receiving this command, the
device switches to HS mode. The device can now
communicate at up to 3.4 Mbit/s on SDA and SCL
lines. The device will switch out of the HS mode on the
next Stop condition.
The master code is sent as follows:
1. Start condition (S)
2. High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the High-Speed (HS)
mode master.
3. No Acknowledge (A)
After switching to the High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgments. The master device
can then issue either a Repeated Start bit to address a
different device (at high speed) or a Stop bit to return to
Fast/Standard bus speed. After the Stop bit, any other
master device (in a multi-master system) can arbitrate
for the I2C bus.
See Figure 6-10 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the Phillips I2C specification.
6.2.6.1 Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
Clock modes of the interface.
6.2.6.2 Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
FIGURE 6-10: HS Mode Sequence.
SA ‘0 0 0 0 1 X X X’b Sr A
‘Slave Address’ A/A“Data”
P
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
R/W
P = Stop bit (Stop condition terminates HS mode)
F/S mode HS mode
HS mode continues
F/S mode
Sr A
‘Slave Address’ R/W
HS Select Byte Control Byte Command/Data Byte(s)
Control Byte
2014 Microchip Technology Inc. DS20005304A-page 53
MCP45HVX1
6.2.7 GENERAL CALL
The General Call is a method that the “master” device
can communicate with all other “slave” devices. In a
multi-master application, the other master devices are
operating in Slave mode. The General Call address
has two documented formats. These are shown in
Figure 6-11. We have added an MCP45HVX1 format in
this figure as well.
This will allow customers to have multiple I2C digital
potentiometers on the bus and have them operate in a
synchronous fashion (analogous to the DAC Sync pin
functionality). If these MCP45HVX1 7-bit commands
conflict with other I2C devices on the bus, then the
customer will need two I2C buses and ensure that the
devices are on the correct bus for their desired
application functionality.
Dual Pot devices can not update both Pot0 and Pot1
from a single command. To address this, there are
General Call commands for the Wiper 0, Wiper 1, and
the TCON registers.
Table 6-3 shows the General Call commands. Three
commands are specified by the I2C specification and
are not applicable to the MCP45HVX1 (so command is
Not Acknowledged) The MCP45HVX1 General Call
commands are Acknowledged. Any other command is
Not Acknowledged.
TABLE 6-3: GENERAL CALL COMMANDS
Note: Only one General Call command per issue
of the General Call control byte. Any
additional General Call commands are
ignored and Not Acknowledged.
7-bit
Command
(1, 2, 3) Comment
‘1000
000’b
or
‘1000
001’b
Write next byte (third byte) to volatile
Wiper 0 register
‘1100
000’b
or
‘1100
001’b
Write Next Byte (Third Byte) to TCON
Register
‘1000
010’b
or
‘1000
011’b
Increment Wiper 0 Register
‘1000
100’b
or
‘1000
101’b
Decrement Wiper 0 Register
Note 1: Any other code is Not Acknowledged.
These codes may be used by other
devices on the I2C bus.
2: The 7-bit command always appends a “0”
to form 8-bits.
MCP45HVX1
DS20005304A-page 54 2014 Microchip Technology Inc.
FIGURE 6-11: General Call Formats.
0000S0000 XXXXXAXX0AP
General Call Address
Second Byte
“7-bit Command”
Reserved 7-bit Commands (By I
2
C™ Specification - NXP UM10204, Ver. 05 October 2012)
‘0000 011’
b – Reset and write programmable part of slave address by hardware.
‘0000 010’
b – Write programmable part of slave address by hardware.
‘0000 000’
b – NOT Allowed
MCP45HVX1 7-bit Commands
‘1000 01x’
b – Increment Wiper 0 Register.
‘1000 10x’
b – Decrement Wiper 0 Register.
The Following is a Microchip Extension to this General Call Format
0000S0000 XXXXXAXX0A
General Call Address
Second Byte
“7-bit Command”
MCP45HVX1 7-bit Commands
‘1000 00x’
b – Write Next Byte (Third Byte) to Volatile Wiper 0 Register.
‘1100 00x’
b – Write Next Byte (Third Byte) to TCON Register.
ddddd dddAP
Third Byte
The Following is a “Hardware General Call” Format
0000S0000 XXXXAXX1A
General Call Address
Second Byte
“7-bit Command”
XXXXX XXXAP
n occurrences of (Data + A)
This indicates a “Hardware General Call”
MCP45HVX1 will ignore this byte and
all following bytes (and
A), until
a Stop bit (P) is encountered.
“0” for General Call Command
2014 Microchip Technology Inc. DS20005304A-page 55
MCP45HVX1
NOTES:
MCP45HVX1
DS20005304A-page 56 2014 Microchip Technology Inc.
7.0 DEVICE COMMANDS
The MCP45HVX1’s I2C command formats are speci-
fied in this section. The I2C protocol does not specify
how commands are formatted.
The MCP45HVX1 supports four basic commands. The
location accessed determines the commands that are
supported.
For the volatile wiper registers, these commands are:
• Write Data
• Read Data
•Increment Data
• Decrement Data
These commands have formats for both a single
command or continuous commands. These commands
are shown in Tab l e 7-1.
TABLE 7-1: I2C COMMANDS
Table 7-2 shows the supported commands for each
memory location.
Table 7-3 shows an overview of all the device
commands and their interaction with other device
features.
7.1 Command Byte
The MCP45HVX1 command byte has three fields: the
address, the command operation, and two data bits
(see Figure 7-1). Currently only one of the data bits is
defined (D8).
The device memory is accessed when the master
sends a proper command byte to select the desired
operation. The memory location getting accessed is
contained in the command byte’s AD3:AD0 bits. The
action desired is contained in the command byte’s
C1:C0 bits, see Figure 7-1. C1:C0 determines if the
desired memory location will be read, written,
incremented (wiper setting +1) or decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile Wiper register.
If the address bits and command bits are not a valid
combination, then the MCP45HVX1 will generate a Not
Acknowledge pulse to indicate the invalid combination.
The I2C master device must then force a Start condition
to reset the MCP45HVX1 I2C module.
D9 and D8 are unused data bits. These bits maintain
code compatibility with the MCP44XX, MCP45XX, and
MCP46XX devices.
FIGURE 7-1: Command Byte Format.
Command # of Bit
Clocks (1, 2)
Operates
on Volatile /
Nonvolatile
memory
Operation Mode
Write Data Single 29 Both
Continuous 18n + 11 Volatile Only
Read Data Single 29 Both
Random 48 Both
Continuous 18n + 11 Both
Increment Single 20 Volatile Only
Continuous 9n + 11 Volatile Only
Decrement Single 20 Volatile Only
Continuous 9n + 11 Volatile Only
Note 1: “n” indicates the number of times the
command operation is to be repeated.
2: These clock counts are for “standard” and
“fast” I2C communication.
AA
D
3
A
D
2
A
D
1
A
D
0
C
1
C
0
D
9
D
8
A
MCP45HVXXX
COMMAND BYTE
00 = Write Data
01 = Increment
MSbits (Data)
10 = Decrement
11 = Read Data
Command Operation bits
Memory Address
2014 Microchip Technology Inc. DS20005304A-page 57
MCP45HVX1
TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS
Address Command Data
(10-bits) (1) Comment
Value Function
00h Volatile Wiper 0 Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
Increment Wiper —
Decrement Wiper —
01h-03h Reserved — —
04h (2) Volatile
TCON 0 Register
Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
05h-FFh Reserved — —
Note 1: The data memory is 8-bits wide, so the two MSbs are ignored by the device. This is for compatibility with
the MCP44XX, MCP45XX, and MCP46XX command formats.
2: Increment or Decrement commands are invalid for these addresses.
3: I2C read operation will read two bytes, of which the 8 bits of data are contained within the Least Significant
Byte (LSB). This is for compatibility with the MCP44XX, MCP45XX, and MCP46XX command formats.
MCP45HVX1
DS20005304A-page 58 2014 Microchip Technology Inc.
7.2 Data Byte
Only the Read command and the Write command have
data byte(s). Even though only one byte of data is
required for the commands, the supported commands
will be formatted for compatibility with the MCP44XX,
MCP45XX, and MCP46XX command formats with sup-
port of 10 bits of data.
7.3 Error Condition
If the four address bits received (AD3:AD0) and the two
command bits received (C1:C0) are a valid
combination, the MCP45HVX1 will Acknowledge the
I2C bus.
If the address bits and command bits are an invalid
combination, then the MCP45HVX1 will Not Acknowl-
edge the I2C bus.
Once an error condition has occurred, any following
commands are ignored until the I2C bus is reset with a
Start condition.
7.3.1 ABORTING A TRANSMISSION
A Restart or Stop condition in the expected data bit
position will abort the current command sequence and
data will not be written to the MCP45HVX1.
TABLE 7-3: COMMANDS
# of Bit Clocks
Command Name Single Continuous
(1)
Write Data 29 18n + 11
Read Data 29 (2) 18n + 11
Increment Wiper 20 9n + 11
Decrement Wiper 20 9n + 11
Note 1: “n” indicates the number of times the command operation is to be repeated.
2: For a random read (read from any memory location), 40 bit clocks are required.
2014 Microchip Technology Inc. DS20005304A-page 59
MCP45HVX1
7.4 Write Data
The Write command format, see Figure 7-2, includes
the I2C control byte, an A bit, the MCP45HVX1 com-
mand byte, an A bit, the MCP45HVX1 data byte, an A
bit, and a Stop (or Restart) condition. The MCP45HVX1
generates the A / A bits.
A Write command to a volatile memory location
changes that location after a properly formatted Write
command and the A/A clock have been received.
7.4.1 SINGLE WRITE TO VOLATILE
MEMORY
Data is written to the MCP45HVX1 after every byte
transfer (during the Acknowledge). If a Stop or Restart
condition is generated during a data transfer (before
the A), the data will not be written to the MCP45HVX1.
After the A bit, the master can initiate the next
sequence with a Stop or Restart condition.
Refer to Figure 7-2 for the byte write sequence.
7.4.2 CONTINUOUS WRITES TO
VOLATILE MEMORY
A Continuous Write mode of operation is possible when
writing to the volatile memory registers (address 00h
and 04h). This Continuous Write mode allows writes
without a Stop or Restart condition or repeated trans-
missions of the I2C Control Byte. Figure 7-3 shows the
sequence for three continuous writes. The writes do not
need to be to the same volatile memory address. The
sequence ends with the master sending a Stop or
Restart condition.
FIGURE 7-2: I2C Write Sequence.
Control Byte Write command Write Data bits
1011S1A1A00 0
AD AD AD AD
A0xxA D3D7 D6 D5 D4 D2 D1 D0 A P
0123
Fixed
Address
Variable
Address
Device
Memory
Address Command Write “Data” bits
Write bit
Reserved
MCP45HVX1
DS20005304A-page 60 2014 Microchip Technology Inc.
FIGURE 7-3: I2C Continuous Volatile Wiper Write.
Stop bit
Control Byte Write command Write Data bits
1011S1A1A00 0A0xx A D3D7 D6 D5 D4 D2 D1 D0 A
Fixed
Address
Variable
Address
Device
Memory
Address Command Write “Data” bits
Write command Write Data bits
00xxA D3D7 D6 D5 D4 D2 D1 D0 A
Write command Write Data bits
00xxA D3D7 D6 D5 D4 D2 D1 D0 A P
Write bit
AD AD AD AD
0123
AD AD AD AD
0123
AD AD AD AD
0123
Note: Only functions when writing the volatile wiper registers (AD3:AD0 = 00h and 01h) or the TCON reg-
isters (AD3:AD0 = 04h)
Reserved
Reserved
Reserved
2014 Microchip Technology Inc. DS20005304A-page 61
MCP45HVX1
7.5 Read Data
The Read command format, see Figure 7-4, includes
the Start condition, I2C control byte (with R/W bit set to
“0”), A bit, MCP45HVX1 command byte, A bit, followed
by a Repeated Start bit, I2C control byte (with R/W bit
set to “1”), and the MCP45HVX1 transmitting the
requested data high byte, and A bit, the data low byte,
the master generating the A, and Stop condition.
The I2C control byte requires the R/W bit equal to a
logic one (R/W = 1) to generate a read sequence. The
memory location read will be the last address
contained in a valid write MCP45HVX1 command byte
or address 00h if no write operations have occurred
since the device was reset (Power-On Reset or Brown-
Out Reset).
7.5.1 SINGLE READ
Figure 7-4 shows the waveforms for a single read.
For single reads the master sends a Stop or Restart
condition after the data byte is sent from the slave.
7.5.1.1 Random Read
Figure 7-5 shows the sequence for a Random Read.
7.5.2 CONTINUOUS READS
Continuous reads allows the devices’ memory to be
read quickly. Continuous reads are possible to all
memory locations.
Figure 7-6 shows the sequence for three continuous
reads.
For continuous reads, instead of transmitting a Stop
or Restart condition after the data transfer, the master
reads the next data byte. The sequence ends with the
master Not Acknowledging and then sending a Stop or
Restart.
7.5.3 IGNORING AN I2C TRANSMISSION
AND “FALLING OFF” THE BUS
The MCP45HVX1 expects to receive complete, valid
I2C commands, and will assume any command not
defined as valid is due to a bus corruption, and will
enter a passive High condition on the SDA signal. All
signals will be ignored until the next valid Start
condition and control byte are received.
FIGURE 7-4: I2C Read (Last Memory Address Accessed).
Note: The MSB (Most Significant Byte) of the 16
read bits is all 0’s to maintain read com-
mand format compatibility with the
MCP44XX/MCP45XX/MCP46XX families
of devices.
Stop bit
Control Byte
1011S1A1A01 A
Fixed
Address
Variable
Address
Read bits
P
00000 000A1
Read bit
D3D7 D6 D5 D4 D2 D1 D0 A2
Read Data bits
Note 1: Master device is responsible for A/A signal. If a A signal occurs, the MCP45HVX1 will abort
this transfer and release the bus.
2: The master device will Not Acknowledge, and the MCP45HVX1 will release the bus so the
master device can generate a Stop or Repeated Start condition.
3: The MCP45HVX1 retains the last “Device Memory Address” that it has received. That is, the
MCP45HVX1 does not “corrupt” the “Device Memory Address” after Repeated Start or Stop
conditions.
4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
MCP45HVX1
DS20005304A-page 62 2014 Microchip Technology Inc.
FIGURE 7-5: I2C Random Read.
FIGURE 7-6: I2C Continuous Reads.
Stop bit
Control Byte READ command
1011S1A1A00 1
AD AD AD AD
A1xXASr
0
1
23
Fixed
Address
Variable
Address
Device
Memory
Address Command
Control Byte Read bits
P
0000 0 0 00A1
Write bit
D3D7 D6 D5 D4 D2 D1 D0 A2
1011 1A1A01 A
Read bit
Repeated Start bit
Read Data bits
Note 1: Master device is responsible for A/A signal. If a A signal occurs, the MCP45HVX1 will abort
this transfer and release the bus.
2: The master device will Not Acknowledge, and the MCP45HVX1 will release the bus so the
master device can generate a Stop or Repeated Start condition.
3: The MCP45HVX1 retains the last “Device Memory Address” that it has received. This is, the
MCP45HVX1 does not “corrupt” the “Device Memory Address” after Repeated Start or Stop
conditions.
Stop bit
Control Byte
1011S1A1A01 A
Fixed
Address
Variable
Address
Read bits
00000 000A1
Read bit
D3D7 D6 D5 D4 D2 D1 D0 A1
Read Data bits
0000 0 0 00A1D3D7 D6 D5 D4 D2 D1 D0 A1
P
00000 0 00A1D3D7 D6 D5 D4 D2 D1 D0 A2
Read Data bits
Read Data bits
Note 1: Master device is responsible for A/A signal. If a A signal occurs, the MCP45HVX1 will abort
this transfer and release the bus.
2: The master device will Not Acknowledge, and the MCP45HVX1 will release the bus so the
master device can generate a Stop or Repeated Start condition.
2014 Microchip Technology Inc. DS20005304A-page 63
MCP45HVX1
7.6 Increment Wiper
The Increment command provides a quick and easy
method to modify the potentiometer’s wiper by +1 with
minimal overhead. The Increment command will only
function on the volatile wiper setting memory locations
00h and 01h. The Increment command to nonvolatile
addresses will be ignored and will generate an A.
When executing an Increment command, the volatile
wiper setting will be altered from n to n+1 for each
Increment command received. The value will
increment up to 100h max on 8-bit devices and 80h on
7-bit devices. If multiple Increment commands are
received after the value has reached 100h (or 80h), the
value will not be incremented further. Tab le 7 - 4 shows
the Increment command versus the current volatile
wiper value.
The Increment command will most commonly be
performed on the volatile wiper locations until a desired
condition is met. The MCP45HVX1 is responsible for
generating the A bits.
Refer to Figure 7-7 for the Increment command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, the Increment command can be followed by any
other valid command. This means that writes do not
need to be to the same volatile memory address.
The advantage of using an Increment command
instead of a read-modify-write series of commands is
speed and simplicity. The wiper will transition after each
command acknowledge when accessing the volatile
wiper registers.
TABLE 7-4: INCREMENT OPERATION VS.
VOLATILE WIPER VALUE
FIGURE 7-7: I2C Increment Command Sequence.
Note: Table 7-4 shows the valid addresses for
the Increment Wiper command. Other
addresses are invalid.
Note: The command sequence can go from an
increment to any other valid command for
the specified address. Issuing an
increment or decrement to a reserved
location will cause an error condition (A
will be generated).
Current Wiper
Setting Wipe r (W)
Properties
Increment
Command
Operates?
7-bit
Pot 8-bit
Pot
7Fh FFh Full Scale (W = A) No
07Eh
40h
FEh
80
W = N
3Fh 7Fh W = N (Mid Scale) Yes
3Eh
01h
7Eh
01
W = N
00h 00h Zero Scale (W = B) Yes
Control Byte INCR command (n+1) INCR command (n+2)
1011S1A1A00 0
AD AD AD AD
A1xxA 0
AD AD AD AD 1xxAP
(2)
0
1
2
34321
Fixed
Address
Variable
Address
Device
Memory
Address Command
Write bit
Note 1: Increment command (INCR) only functions when accessing the volatile wiper registers
(AD3:AD0 = 00h and 01h).
2: This command sequence does not need to terminate (using the Stop bit) and can change to
any other desired command sequence (Increment, Read, or Write).
Reserved Reserved
MCP45HVX1
DS20005304A-page 64 2014 Microchip Technology Inc.
7.7 Decrement Wiper
The Decrement command provides a quick and easy
method to modify the potentiometer’s wiper by -1 with
minimal overhead. The Decrement command will only
function on the volatile wiper setting memory locations
00h and 01h.
When executing a Decrement command, the volatile
wiper setting will be altered from n to n-1 for each
Decrement command received. The value will
decrement down to 000h min. If multiple Decrement
commands are received after the value has reached
000h, the value will not be decremented further.
Table 7-5 shows the Decrement command versus the
current volatile wiper value.
The Decrement command will most commonly be
performed on the volatile wiper locations until a desired
condition is met.
Refer to Figure 7-8 for the Decrement command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, the Decrement command can be followed by
any other valid command. This means that writes do
not need to be to the same volatile memory address.
The advantage of using a Decrement command
instead of a read-modify-write series of commands is
speed and simplicity. The wiper will transition after each
command acknowledge when accessing the volatile
wiper registers.
TABLE 7-5: DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
FIGURE 7-8: I2C Decrement Command Sequence.
Note: Table 7-5 shows the valid addresses for
the Decrement Wiper command. Other
addresses are invalid.
Note: The command sequence can go from a
decrement to any other valid command for
the specified address.
Current Wiper
Setting Wipe r (W)
Properties
Decrement
Command
Operates?
7-bit
Pot 8-bit
Pot
7Fh FFh Full Scale (W = A) Yes
7Eh
40h
FEh
80
W = N
3Fh 7Fh W = N (Mid Scale) Yes
3Eh
01h
7Eh
01
W = N
00h 00h Zero Scale (W = B) No
Control Byte DECR command (n-1) DECR command (n-2)
1011S1A1A00 1
AD AD AD AD
A0xxA 1
AD AD AD AD 0xxAP
(2)
0
1
2
34321
Fixed
Address
Variable
Address
Device
Memory
Address Command
Write bit
Note 1: Decrement command (DECR) only functions when accessing the volatile wiper registers
(AD3:AD0 = 00h and 01h).
2: This command sequence does not need to terminate (using the Stop bit) and can change to
any other desired command sequence (DECR, Read, or Write).
Reserved Reserved
2014 Microchip Technology Inc. DS20005304A-page 65
MCP45HVX1
NOTES:
MCP45HVX1
DS20005304A-page 66 2014 Microchip Technology Inc.
8.0 APPLICATIONS EX AMPLES
Digital potentiometers have a multitude of practical
uses in modern electronic circuits. The most popular
uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming.
8.1 Using Shutdown Modes
Figure 8-1 shows a possible application circuit where
the independent terminals could be used.
Disconnecting the wiper allows the transistor input to
be taken to the bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the RBW rheostat value to the Common B.
Disconnecting Terminal B modifies the transistor input
by the RAW rheostat value to the Common A. The
Common A and Common B connections could be
connected to V+ and V-.
FIGURE 8-1: Example Application Circuit
using Terminal Disconnects.
8.2 Soft wa re Reset Sequence
At times, it may become necessary to perform a
Software Reset Sequence to ensure the MCP45HVX1
device is in a correct and known I2C Interface state.
This technique only resets the I2C state machine.
This is useful if the MCP45HVX1 device powers-up in
an incorrect state (due to excessive bus noise, etc), or
if the master device is reset during communication.
Figure 8-2 shows the communication sequence to
software reset the device.
FIGURE 8-2: Software Reset Sequence
Format.
The first Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
master device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP45HVX1 is driving an A bit
on the I2C bus, or is in Output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP45HVX1 holding the
bus Low. By sending out nine ‘1’ bits, it is ensured that
the device will see an A bit (the master device does not
drive the I2C bus Low to acknowledge the data sent by
the MCP45HVX1), which also forces the MCP45HVX1
to reset.
The second Start bit is sent to address the rare possi-
bility of an erroneous write. This could occur if the mas-
ter device was reset while sending a Write command to
the MCP45HVX1, and then as the master device
returns to normal operation and issues a Start condition
while the MCP45HVX1 is issuing an Acknowledge. In
this case, if the 2nd Start bit is not sent (and the Stop bit
was sent) the MCP45HVX1 could initiate a write cycle.
M
The Stop bit terminates the current I2C bus activity. The
MCP45HVX1 waits to detect the next Start condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
Note: This technique is documented in AN1028.
Note: The potential for this erroneous write only
occurs if the master device is reset while
sending a Write command to the
MCP45HVX1.
S‘1’‘1’‘1’‘1’‘1’‘1’‘1’‘1’ S P
Start
bit
Nine bits of ‘1’
Start bit
Stop bit
2014 Microchip Technology Inc. DS20005304A-page 67
MCP45HVX1
8.3 High-Voltage DAC
A high-voltage DAC can be implemented using the
MCP45HVX1, with voltages as high as 36V. The circuit
is shown in Figure 8-3. The equation to calculate the
voltage output is shown in Equation 8-1.
FIGURE 8-3: High-Voltage DAC.
EQUATION 8-1: DAC OUTPUT VOLTAGE
CALCULATION
8.4 Variable Gain Instrumentation
Amplifier
A variable gain instrumentation amplifier can be
implemented using the MCP45HVX1 along with a high-
voltage dual analog switch and a high-voltage
instrumentation amplifier.
Figure 8-3. The equation to calculate the voltage output
is shown in Equation 8-2.
FIGURE 8-4: Variable Gain
Instrumentation Amplifier for Data Acquisition
System.
EQUATION 8-2: DAC OUTPUT VOLTAGE
CALCULATION
N = 0 to 255 (decimal)
VOUT(N) = x ( VD x ( 1 + ) )
R1
R2
N
255
7-bit
8-bit
N = 0 to 127 (decimal)
VOUT(N) = x ( VD x ( 1 + ) )
R1
R2
N
127
Gain(N) = 1 + 49.4 k
(N / 255) x RAB
N = 0 to 255 (decimal)
7-bit
8-bit
Gain(N) = 1 + 49.4 k
(N / 127) x RAB
N = 0 to 127 (decimal)
MCP45HVX1
DS20005304A-page 68 2014 Microchip Technology Inc.
8.5 Audio Volume Control
A digital volume control can be implemented with the
MCP45HVX1. Figure 8-5 shows a simple audio volume
control implementation.
Figure 8-6 shows a circuit-referenced voltage detect
circuit. The output of this circuit could be used to control
the Wiper Latch of the MCP45HVX1 device in the
Audio Volume control circuit to reduce zipper noise or
to update the different channels at the same time.
The op amp (U1) could be an MCP6001, while the gen-
eral purpose comparators (U2 and U3) could be an
MCP6541. U4 is a simple AND gate.
U1 establishes the signal zero reference. The upper
limit of the comparator is set above its offset. The WLAT
pin is forced High whenever the voltage falls between
2.502V and 2.497V (a 0.005V window).
The capacitor C1 AC couples the VIN signal into the cir-
cuit, before feeding into the windowed comparator (and
MCP45HVX1 Terminal A pin).
FIGURE 8-5: Audio Volume Control.
FIGURE 8-6: Referenced Voltage
Crossing Detec t.
8.6 Programmable Power Supply
The ADP1611 is a step-up DC-to-DC switching con-
verter. Using the MCP45HVX1 device allows the power
supply to be programmable up to 20V. Figure 8-7
shows a programmable power supply implementation.
Equation 8-3 shows the equation to calculate the
output voltage of the programmable power supply. This
output is derived from the RBW resistance of the
MCP45HVX1 device and the R2 resistor. The ADP1611
will adjust its output voltage to maintain 1.23V on the
FB pin.
When power is connected, L1 acts as a short, and
VOUT is a diode drop below the +5V voltage. The VOUT
voltage will ramp to the programmed value.
FIGURE 8-7: Programmable Power
Supply.
EQUATION 8-3: POWER SUPPLY OUTPUT
VOLTAGE
CALCULATION
N = 0 to 255 (decimal)
VOUT(N) = 1.23V x ( 1 + ( ) )
R2
N * RAB
255
7-bit
8-bit
N = 0 to 127 (decimal)
VOUT(N) = 1.23V x ( 1 + ( ) )
R2
N * RAB
127
2014 Microchip Technology Inc. DS20005304A-page 69
MCP45HVX1
8.7 Programmable Bidirectional
Current Source
A programmable bidirectional current source can be
implemented with the MCP45HVX1. Figure 8-8 shows
an implementation where U1 and U2 work together to
deliver the desired current (dependent on selected
device) in both directions. The circuit is symmetrical
(R1A =R
1B, R2A =R
2B, R3A =R
3B) in order to improve
stability. If the resistors are matched, the load current
(IL) calculation is shown below:
EQUATION 8-4: LOAD CURRENT (IL)
FIGURE 8-8: Programmable Bidirectional
Current Sou rce .
8.8 LCD Contrast Contr ol
The MCP45HVX1 can be used for LCD contrast
control. Figure 8-9 shows a simple programmable LCD
contrast control implementation.
Some LCD panels support a fixed power supply of up
to 28V. The high-voltage digital potentiometer's wiper
can support contrast adjustments through the entire
voltage range.
FIGURE 8-9: Programmable Contrast
Control.
MCP45HVX1
DS20005304A-page 70 2014 Microchip Technology Inc.
8.9 Implementing Log Steps with a
Linear Digital Potentiometer
In audio volume control applications, the use of
logarithmic steps is desirable since the human ear
hears in a logarithmic manner. The use of a linear
potentiometer can approximate a log potentiometer,
but with fewer steps. An 8-bit potentiometer can
achieve fourteen 3 dB log steps plus a 100% (0 dB)
and a mute setting.
Figure 8-10 shows a block diagram of one of the
MCP45HVx1 resistor networks being used to attenuate
an input signal. In this case, the attenuation will be
ground referenced. Terminal B can be connected to a
Common mode voltage, but the voltages on the A, B
and wiper terminals must not exceed the
MCP45HVx1’s V+/V- voltage limits.
FIGURE 8-10: Signal Attenuation Block
Diagram – Ground Referenced.
Equation 8-5 shows the equation to calculate voltage
dB gain ratios for the digital potentiometer, while
Equation 8-6 shows the equation to calculate
resistance dB gain ratios. These two equations assume
that the B terminal is connected to ground.
If Terminal B is not directly resistively connected to
ground, then this Terminal B to ground resistance
(RB2GND) must be included into the calculation.
Equation 8-7 shows this equation.
EQUATION 8-5: dB CALCULATIONS
(VOLTAGE)
EQUATION 8-6: dB CALCULATIONS
(RESISTANCE) – CASE 1
EQUATION 8-7: dB CALCULATIONS
(RESISTANCE) – CASE 2
Table 8-1 shows the codes that can be used for 8-bit
digital potentiometers to implement the log attenuation.
The table shows the wiper codes for -3 dB, -2 dB, and
-1 dB attenuation steps. This table also shows the
calculated attenuation based on the wiper code’s linear
step. Calculated attenuation values less than the
desired attenuation are shown with red text. At lower
wiper code values, the attenuation may skip a step. If
this occurs, the next attenuation value is colored
magenta to highlight that a skip occurred. For example,
in the -3 dB column the -48 dB value is highlighted
since the -45 dB step could not be implemented (there
are no wiper codes between 2 and 1).
2014 Microchip Technology Inc. DS20005304A-page 71
MCP45HVX1
TABLE 8-1: LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS
# of
Steps
-3 dB Steps -2 dB Steps -1 dB Steps
Desired
Attenuation Wiper
Code
Calculated
Attenuation
(1)
Desired
Attenuation Wiper
Code
Calculated
Attenuation
(1)
Desired
Attenuation Wiper
Code
Calculated
Attenuation
(1)
0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB
1 -3 dB 180 -3.025 dB -2 dB 203 -1.981 dB -1 dB 227 -1.010 dB
2 -6 dB 128 -5.987 dB -4 dB 161 -3.994 dB -2 dB 203 -1.981 dB
3 -9dB 90 -9.046 dB -6 dB 128 -5.987 dB -3 dB 180 -3.025 dB
4 -12 dB 64 -12.007 dB -8 dB 101 -8.044 dB -4 dB 161 -3.994 dB
5 -15 dB 45 -15.067 dB -10 dB 81 -9.961 dB -5 dB 143 -5.024 dB
6 -18 dB 32 -18.028 dB -12 dB 64 -12.007 dB -6 dB 128 -5.987 dB
7 -21 dB 23 -20.896 dB -14 dB 51 -13.979 dB -7 dB 114 -6.993 dB
8 -24 dB 16 -24.048 dB -16 dB 40 -16.090 dB -8 dB 101 -8.044 dB
9 -27 dB 11 -27.303 dB -18 dB 32 -18.028 dB -9 dB 90 -9.046 dB
10 -30 dB 8 -30.069 dB -20 dB 25 -20.172 dB -10 dB 81 -9.961 dB
11 -33 dB 6 -32.568 dB -22 dB 20 -22.110 dB -11 dB 72 -10.984 dB
12 -36 dB 4 -36.090 dB -24 dB 16 -24.048 dB -12 dB 64 -12.007 dB
13 -39 dB 3 -38.588 dB -26 dB 13 -25.852 dB -13 dB 57 -13.013 dB
14 -42 dB 2 -42.110 dB -28 dB 10 -28.131 dB -14 dB 51 -13.979 dB
15 -48 dB 1 -48.131 dB -30 dB 8 -30.069 dB -15 dB 45 -15.067 dB
16 Mute 0 Mute -32 dB 6 -32.602 dB -16 dB 40 -16.090 dB
17 -34 dB 5 -34.151 dB -17 dB 36 -17.005 dB
18 -36 dB 4 -36.090 dB -18 dB 32 -18.028 dB
19 -38 dB 3 -38.588 dB -19 dB 29 -18.883 dB
20 -42 dB 2 -42.110 dB -20 dB 25 -20.172 dB
21 -48 dB 1 -48.131 dB -21 dB 23 -20.896 dB
22 Mute 0 Mute -22 dB 20 -22.110 dB
23 -23 dB 18 -23.025 dB
24 -24 dB 16 -24.048 dB
25 -25 dB 14 -25.208 dB
26 -26 dB 13 -25.852 dB
27 -27dB 11 -27.303 dB
28 -28 dB 10 -28.131 dB
29 -29 dB 9 -29.046 dB
30 -30 dB 8 -30.069 dB
31 -31 dB 7 -31.229 dB
32 -33 dB 6-32.568 dB
33 -34 dB 5 -34.151 dB
34 -36 dB 4 -36.090 dB
35 -39 dB 3-38.588 dB
36 -42 dB 2 -42.110 dB
37 -48 dB 1 -48.131 dB
38 Mute 0 Mute
Legend: Calculated Attenuation Value Color Code: Black -> Above Target Value; Red -> Below Target Value
Desired Attenuation Value Color Code: Magenta -> Skipped Desired Attenuation Value(s).
Note 1: Attenuation values do not include errors from digital potentiometer errors, such as Full-Scale Error or Zero-
Scale Error.
MCP45HVX1
DS20005304A-page 72 2014 Microchip Technology Inc.
8.10 Using the General Call Command
The use of the General Call Address Increment,
Decrement, or Write commands is analogous to the
“Load” feature (LDAC pin) on some DACs (such as the
MCP4921). This allows all the devices to “Update” the
output level “at the same time”.
For some applications, the ability to update the wiper
values “at the same time” may be a requirement, since
the delay from writing to one wiper value and then the
next may cause application issues. A possible example
would be a “tuned” circuit that uses several
MCP45HVX1 in rheostat configuration. As the system
condition changes (temperature, load, etc.) these
devices need to be changed (incremented/decre-
mented) to adjust for the system change. These
changes will either be in the same direction or in oppo-
site directions. With the Potentiometer device, the cus-
tomer can either select the PxB terminals (same
direction) or the PxA terminal(s) (opposite direction).
Figure 8-12 shows that the update of six devices takes
6*TI2CDLY time in “normal” operation, but only
1*TI2CDLY time in “General Call” operation.
Figure 8-11 shows two I2C bus configurations. In many
cases, the single I2C bus configuration will be
adequate. For applications that do not want all the
MCP45HVX1 devices to do General Call support or
have a conflict with General Call commands, the
multiple I2C bus configuration would be used.
FIGURE 8-11: Typical Application I2C Bus
Configurations.
FIGURE 8-12: Example Comparison of “Normal Operation” vs. “General Call Operation” Wiper
Updates.
Note: The application system may need to
partition the I2C bus into multiple buses to
ensure that the MCP45HVX1 General Call
commands do not conflict with the Gen-
eral Call commands that the other I2C
devices may have defined. Also, if only a
portion of the MCP45HVX1 devices are to
require this synchronous operation, then
the devices that should not receive these
commands should be on the second I2C
bus.
Single I2C™ Bus Configuration
Host
Controller
Device 1 Device 3 Device n
Device 2 Device 4
Multiple I2C Bus Configuration
Host
Controller
Device 1a Device 3a Device na
Device 2a Device 4a
Device 1b Device 3b Device nb
Device 2b Device 4b
Bus b
Bus a
Device 1n Device 3n Device nn
Device 2n Device 4n
Bus n
Normal Operation
General Call Operation
INC
POT01
INC
POT02
INC
POT03
INC
POT04
INC
POT05
INC
POT06
TI2CDLY TI2CDLY TI2CDLY TI2CDLY TI2CDLY
TI2CDLY = Time from one I2C command completed to completing the next I2C command.
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
TI2CDLY TI2CDLY TI2CDLY TI2CDLY TI2CDLY
TI2CDLY
TI2CDLY
2014 Microchip Technology Inc. DS20005304A-page 73
MCP45HVX1
8.11 Desi gn Con siderations
In the design of a system with the MCP45HVX1
devices, the following considerations should be taken
into account:
•Power Supply Conside ration s
•Layout Considerations
8.11.1 POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply’s traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-13 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VL) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V+ and V-
should reside on the analog plane.
FIGURE 8-13: Typi c al Mic roc ont ro ll er
Connections.
8.11.2 LAYOUT CONSIDERATIONS
In the design of a system with the MCP45HVX1
devices, the following layout considerations should be
taken into account:
•Noise
•PCB Area Requirements
•Power Dissi pation
8.11.2.1 Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP45HVX1’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the
silicon is capable of providing. Particularly harsh
environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.11.2.2 PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the package dimensions
and area for the different package options. The table
also shows the relative area factor compared to the
smallest area. For space critical applications, the QFN
package would be the suggested package.
TABLE 8-2: PACKAGE FOOTPRINT (1)
Package Package Footprint
Pins
Type Code
Dimensions
(mm)
Area (mm2)
Relative Area
XY
14 TSSOP ST 5.10 6.40 32.64 1.31
20 QFN MQ 5.00 5.00 25.00 1
Note 1: Does not include recommended land
pattern dimensions.
MCP45HVX1
DS20005304A-page 74 2014 Microchip Technology Inc.
8.11.3 RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (tempco) are shown in the device character-
ization graphs.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end-to-end change in RAB resistance.
8.11.3.1 Power Dissipation
The power dissipation of the high-voltage digital poten-
tiometer will most likely be determined by the power
dissipation through the resistor networks.
Table 8-3 shows the power dissipation through the
resistor ladder (RAB) when Terminal A = +18V and
Terminal B = -18V. This is not the worst-case power
dissipation based on the 25 mA terminal current
specification. Tab l e 8-3 shows the worst-case current
(per resistor network), which is independent of the RAB
value).
TABLE 8-3: RAB POWER DISSIPATION
TABLE 8-4: RBW POWER DISSIPATION
RAB Resist anc e ()| V
A | + |VB |
=
(V)
Power
(mW) (1)
Typical Min Max
5,000 4,000 6,000 36 324
10,000 8,000 12,000 36 162
50,000 40,000 60,000 36 32.4
100,000 80,000 120,000 36 16.2
Note 1: Power = V * I = V2/RAB(MIN).
RAB ()
(Typical) | VW | + |VB | =
(V)
IBW (2)
(mA) Power
(mW) (1)
5,000 36 25 900
10,000 36 12.5 450
50,000 36 6.5 234
100,000 36 6.5 234
Note 1: Power = V * I.
2: See Electrical Specifications (max IW).
2014 Microchip Technology Inc. DS20005304A-page 75
MCP45HVX1
NOTES:
MCP45HVX1
DS20005304A-page 76 2014 Microchip Technology Inc.
9.0 DEVICE OPTIONS
9.1 Standard Options
9.1.1 POR/BOR WIPER SETTING
The default wiper setting (mid scale) is indicated by the
customer in three digit suffix: -202, -502, -103 and -503.
Table 9-1 indicates the device’s default settings.
TABLE 9-1: DEFAULT POR/BOR WIPER
SETTING SELECTION
9.2 Custom Options
Custom options can be made available.
9.2.1 CUSTOM WIPER VALUE ON POR/
BOR EVENT
Customers can specify a custom wiper setting via the
Non-Standard Customer Authorization Request
(NSCAR) process.
Typical
RAB
Value
Package
Code
Default
POR Wiper
Setting
Device
Resolution Wiper
Code
5.0 k -502 Mid scale 8-bit 7Fh
7-bit 3Fh
10.0 k -103 Mid scale 8-bit 7Fh
7-bit 3Fh
50.0 k -503 Mid scale 8-bit 7Fh
7-bit 3Fh
100.0 k -104 Mid scale 8-bit 7Fh
7-bit 3Fh
Note 1: Non-Recurring Engineering (NRE)
charges and minimum ordering require-
ments for custom orders. Please contact
Microchip sales for additional informa-
tion.
2: A custom device will be assigned custom
device marking.
2014 Microchip Technology Inc. DS20005304A-page 77
MCP45HVX1
NOTES:
MCP45HVX1
DS20005304A-page 78 2014 Microchip Technology Inc.
10.0 DEVELOPMENT SUPPORT
10.1 Development Tools
Several development tools are available to assist in
your design and evaluation of the MCP45HVX1
devices. The currently available tools are shown in
Table 10-1.
Figure 10-1 shows how the TSSOP20EV bond-out
PCB can be populated to easily evaluate the
MCP45HVX1 devices. Evaluation can use the PICkit™
Serial Analyzer to control the position of the volatile
wiper and state of the TCON register.
Figure 10-2 shows how the SOIC14EV bond-out PCB
can be populated to evaluate the MCP45HVX1
devices. The use of the PICkit Serial Analyzer would
require blue wire since the header H1 is not compatibly
connected.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
10.2 Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs and Design Guides. Tab l e 10-2 shows
some of these documents.
TABLE 10-1: DEVELOPMENT TOOLS
TABLE 10-2: TECHNICAL DOCUMENTATION
Board Name Part # Comment
20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit™ Serial Analyzer
(Order #: DV164122)
14-pin SOIC/TSSOP/DIP Evaluation Board SOIC14EV
Application
Note Number Title Literature #
TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073
AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316
AN1080 Understanding Digital Potentiometers Resistor Variations DS01080
AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737
AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692
AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691
AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219
— Digital Potentiometer Design Guide DS22017
— Signal Chain Design Guide DS21825
— Analog Solutions for Automotive Applications Design Guide DS01005
2014 Microchip Technology Inc. DS20005304A-page 79
MCP45HVX1
FIGURE 10-1: Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV.
0
4.7k
0
45HVx1
Four blue wire jumpers to connect
PICkit™ Serial interface (I2C™) to device pins 1x6 male header, with 90° right angle
MCP45HVX1-xxxE/ST
installed in U3 (bottom 14 pins of TSSOP-20 footprint)
Connected to
Digital Ground
Connected to
Digital Power (VL) Plane
Through-hole Test
Point (Orange)
Wiper 0
VL
SCL
A1
SDA
A0
V+
P0A
P0W
P0B
V-
(DGND) Plane
WLAT
SHDN
DGND
NC
1.0 µF
P0A pin shorted
(jumpered) to
V+ pin
P0B pin shorted
(jumpered) to
V- pin
4.7k
4.7k
4.7k
4.7k
4.7k
MCP45HVX1
DS20005304A-page 80 2014 Microchip Technology Inc.
FIGURE 10-2: Digital Potentiometer Evaluation Board Circuit Using SOIC14EV.
MCP45HVX1
1.0 µF
VLSCLA1SDAA0WLATSHDN
V+P0AP0WP0BV-DGNDNC
0
0
4.7k 4.7k
4.7k
4.7k
4.7k
4.7k
P0A pin shorted
(jumpered) to
V+ pin
P0B pin shorted
(jumpered) to
V- pin
2014 Microchip Technology Inc. DS20005304A-page 81
MCP45HVX1
NOTES:
MCP45HVX1
DS20005304A-page 82 2014 Microchip Technology Inc.
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
RoHS Compliant JEDEC® designator for Matte Tin (Sn)
*This package is RoHS Compliant. The RoHS Compliant
JEDEC designator ( ) can be found on the outer packaging
for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
20-Lead QFN (5x5x0.9 mm) Example
PIN 1PIN 1
3
e
14-Lead TSSOP (4.4 mm) Example
YYWW
NNN
XXXXXXXX
Part Number Code Part Number Code
MCP45HV51-502E/ST 45H51502 MCP45HV31-502E/ST 45H31502
MCP45HV51-103E/ST 45H51103 MCP45HV31-103E/ST 45H31103
MCP45HV51-503E/ST 45H51503 MCP45HV31-503E/ST 45H31503
MCP45HV51-104E/ST 45H51104 MCP45HV31-104E/ST 45H31104
45H51502
E416
256
Part Number Code Part Number Code
MCP45HV51-502E/MQ 502E/MQ MCP45HV31-502E/MQ 502E/MQ
MCP45HV51-103E/MQ 103E/MQ MCP45HV31-103E/MQ 103E/MQ
MCP45HV51-503E/MQ 503E/MQ MCP45HV31-503E/MQ 503E/MQ
MCP45HV51-104E/MQ 104E/MQ MCP45HV31-104E/MQ 104E/MQ
45HV31
502E/MQ
1416256
XYWW
2014 Microchip Technology Inc. DS20005304A-page 83
MCP45HVX1
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP45HVX1
DS20005304A-page 84 2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc. DS20005304A-page 85
MCP45HVX1
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP45HVX1
DS20005304A-page 86 2014 Microchip Technology Inc.
20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-120A
2014 Microchip Technology Inc. DS20005304A-page 87
MCP45HVX1
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP45HVX1
DS20005304A-page 88 2014 Microchip Technology Inc.
2014 Microchip Technology Inc. DS20005304A-page 89
MCP45HVX1
APPENDIX A: REVISION HISTORY
Revision A (June 2014)
• Original Release of this Document.
APPENDIX B: TERMINOLOGY
This appendix discusses the terminology used in this
document and it also describes how a parameter is
measured.
B.1 Potentiometer (Voltage Divider)
The potentiometer configuration is when all three
terminals of the device are tied to different nodes in the
circuit. This allows the potentiometer to output a
voltage proportional to the input voltage. This
configuration is sometimes called Voltage Divider
mode. The potentiometer is used to provide a variable
voltage by adjusting the wiper position between the two
endpoints as shown in Figure B-1. Reversing the
polarity of the A and B terminals will not affect
operation.
FIGURE B-1: POTENTIOMETER
CONFIGURATION.
The temperature coefficient of the RAB resistors is
minimal by design. In this configuration, the resistors all
change uniformly, so minimal variation should be seen.
B.2 Rheost at (Variable Resistor)
The rheostat configuration is when two of the three dig-
ital potentiometer’s terminals are used as a resistive
element in the circuit. With Terminal W (wiper) and
either Terminal A or Terminal B, a variable resistor is
created. The resistance will depend on the tap setting
of the wiper (and the wiper’s resistance). The
resistance is controlled by changing the wiper setting.
Figure B-2 shows the two possible resistors that can be
used. Reversing the polarity of the A and B terminals
will not affect operation.
FIGURE B-2: RHEOSTAT
CONFIGURATION.
MCP45HVX1
DS20005304A-page 90 2014 Microchip Technology Inc.
B.3 Resolution
The resolution is the number of wiper output states that
divide the full-scale range. For the 8-bit digital
potentiometer, the resolution is 28, meaning the digital
potentiometer wiper code ranges from 0 to 255.
B.4 Step Resi stance (RS)
The resistance Step size (RS) equates to one LSb of
the resistor ladder. Equation B-1 shows the calculation
for the step resistance (RS).
EQUATION B-1: RS CALCULATION
B.5 Wiper Resistance
Wiper resistance is the series resistance of the analog
switch that connects the selected resistor ladder node
to the Wiper terminal common signal (see Figure 5-1).
A value in the volatile Wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The resistance is dependent on the voltages on the
analog switch source, gate, and drain nodes, as well as
the device’s wiper code, temperature, and the current
through the switch. As the device voltage decreases,
the wiper resistance increases.
The wiper resistance is measured by forcing a current
through the W and B terminals (IWB) and measuring the
voltage on the W and A terminals (VW and VA). Termi-
nal A is not biased. Equation B-2 shows how to calcu-
late this resistance.
EQUATION B-2: RW CALCULATION
The wiper resistance in potentiometer-generated
voltage divider applications is not a significant source
of error (it does not affect the output voltage seen on
the W pin).
The wiper resistance in rheostat applications can
create significant nonlinearity as the wiper is moved
toward zero scale (00h). The lower the nominal
resistance, the greater the possible error.
B.6 RZS Resistance
The analog switch between the resistor ladder and the
Terminal B pin introduces a resistance, which we call
the Zero-Scale resistance (RZS). Equation B-3 shows
how to calculate this resistance.
EQUATION B-3: RZS CALCULATION
B.7 RFS Resistance
The analog switch between the resistor ladder and the
Terminal A pin introduces a resistance, which we call
the Full-Scale resistance (RFS). Equation B-4 shows
how to calculate this resistance.
EQUATION B-4: RFS CALCULATION
2014 Microchip Technology Inc. DS20005304A-page 91
MCP45HVX1
B.8 Least Signifi cant Bit (LSb)
This is the difference between two successive codes
(either in resistance or voltage). For a given output
range it is divided by the resolution of the device
(Equation B-5).
EQUATION B-5: LSb CALCULATION
B.9 Monotonic Operation
Monotonic operation means that the device’s output
(resistance (RBW) or voltage (VW)) increases with
every one code step (LSb) increment of the Wiper
register.
FIGURE B-3: THEORETICAL VW
OUTPUT VS CODE (MONOTONIC
OPERATION).
FIGURE B-4: THEORETICAL RBW
OUTPUT VS CODE (MONOTONIC
OPERATION).
0x40
0x3F
0x3E
0x03
0x02
0x01
0x00
Wiper Code
Voltage (VW ~= VOUT)
VW (@ tap)
VS0
VS1
VS3
VS63
VS64
VW = VSn + VZS(@ Tap 0)
n = 0
n = ?
0x3F
0x3E
0x3D
0x03
0x02
0x01
0x00
Digital Input Code
Resistance (RBW)
RW
(@ tap)
RS0
RS1
RS3
RS62
RS63
RBW = RSn + RW(@ Tap n)
n = 0
n = ?
MCP45HVX1
DS20005304A-page 92 2014 Microchip Technology Inc.
B.10 Full-Scale Error (EFS)
The Full-Scale Error (see Figure B-5) is the error of
the VW pin relative to the expected VW voltage
(theoretical) for the maximum device wiper register
code (code FFh for 8-bit and code 7Fh for 7-bit), see
Equation B-6. The error is defined with no resistive
load on the P0W pin.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
EQUATION B-6: FULL-SCALE ERROR
FIGURE B-5: FULL-SCALE ERROR
EXAMPLE.
B.11 Zero-Scale Error (EZS)
The Zero-Scale Error (see Figure B-6) is the difference
between the ideal and measured VOUT voltage with the
Wiper register code equal to 00h (Equation B-7). The
error is defined with no resistive load on the P0W pin.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
EQUATION B-7: ZERO SCALE ERROR
FIGURE B-6: ZERO-SCALE ERROR
EXAMPLE.
Note: Analog switch leakage increases with
temperature. This leakage increases sub-
stantially at higher temperatures (>
~100°C). As analog switch leakage
increases, the full-scale output value
decreases, which increases the Full-
Scale Error.
Note: Analog switch leakage increases with
temperature. This leakage increases sub-
stantially at higher temperatures (>
~100°C). As analog switch leakage
increases the zero-scale output value
decreases, which decreases the Zero-
Scale Error.
2014 Microchip Technology Inc. DS20005304A-page 93
MCP45HVX1
B.12 Integral Nonlinearity (P-INL)
Potentiometer Configuration
The Potentiometer Integral nonlinearity (P-INL) error is
the maximum deviation of an actual VW transfer
function from an ideal transfer function (straight line).
In the MCP45HVX1, P-INL is calculated using the zero-
scale and full-scale wiper code end points. P-INL is
expressed in LSb. P-INL is also called relative
accuracy. Equation B-8 shows how to calculate the P-
INL error in LSb and Figure B-7 shows an example of
P-INL accuracy.
Positive P-INL means higher VW voltage than ideal.
Negative P-INL means lower VW voltage than ideal.
EQUATION B-8: P-INL ERROR
FIGURE B-7: P-INL ACCURACY.
B.13 Differential Nonlinearity (P-DNL)
Potentiometer Configuration
The Potentiometer Differential nonlinearity (P-DNL)
error (see Figure B-8) is the measure of VW step size
between codes. The ideal step size between codes is
1 LSb. A P-DNL error of zero would imply that every
code is exactly 1 LSb wide. If the P-DNL error is less
than 1 LSb, the digital potentiometer guarantees mono-
tonic output and no missing codes. The P-DNL error
between any two adjacent codes is calculated in
Equation B-9.
P-DNL error is the measure of variations in code widths
from the ideal code width.
EQUATION B-9: P-DNL ERROR
FIGURE B-8: P-DNL ACCURACY.
Note: Analog switch leakage increases with
temperature. This leakage increases sub-
stantially at higher temperatures
(> ~100°C). As analog switch leakage
increases, the Wiper output voltage (VW)
decreases, which affects the INL Error.
Note: Analog switch leakage increases with
temperature. This leakage increases sub-
stantially at higher temperatures
(> ~100°C). As analog switch leakage
increases, the Wiper output voltage (VW)
decreases, which affects the DNL Error.
MCP45HVX1
DS20005304A-page 94 2014 Microchip Technology Inc.
B.14 Integral Nonlinearity (R-INL)
Rheostat Configuration
The Rheostat Integral nonlinearity (R-INL) error is the
maximum deviation of an actual RBW transfer function
from an ideal transfer function (straight line).
In the MCP45HVX1, INL is calculated using the Zero-
Scale and Full-Scale wiper code end points. R-INL is
expressed in LSb. R-INL is also called relative
accuracy. Equation B-10 shows how to calculate the R-
INL error in LSb and Figure B-9 shows an example of
R-INL accuracy.
Positive R-INL means higher VOUT voltage than ideal.
Negative R-INL means lower VOUT voltage than ideal.
EQUATION B-10: R-INL ERROR
FIGURE B-9: R-INL ACCURACY.
B.15 Differential Nonlinearity (R-DNL)
Rheostat Configurat ion
The Rheostat Differential nonlinearity (R-DNL) error
(see Figure B-10) is the measure of RBW step size
between codes in actual transfer function. The ideal
step size between codes is 1 LSb. A R-DNL error of
zero would imply that every code is exactly 1 LSb wide.
If the R-DNL error is less than 1 LSb, the RBW Resis-
tance guarantees monotonic output and no missing
codes. The R-DNL error between any two adjacent
codes is calculated in Equation B-11.
R-DNL error is the measure of variations in code widths
from the ideal code width. A R-DNL error of zero would
imply that every code is exactly 1 LSb wide.
EQUATION B-11: R-DNL ERROR
FIGURE B-10: R-DNL ACCURACY.
2014 Microchip Technology Inc. DS20005304A-page 95
MCP45HVX1
B.16 Total Unadjusted Error (ET)
The Total Unadjusted Error (ET) is the difference
between the ideal and measured VW voltage.
Typically, calibration of the output voltage is
implemented to improve system performance.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
Equation B-12 shows the Total Unadjusted Error
calculation.
EQUATION B-12: TOTAL UNADJUSTED
ERROR CALCULATION
B.17 Settling Time
The settling time is the time delay required for the VW
voltage to settle into its new output value. This time is
measured from the start of code transition, to when the
VW voltage is within the specified accuracy. It is related
to the RC characteristics of the resistor ladder and
wiper switches.
In the MCP45HVX1, the settling time is a measure of
the time delay until the VW voltage reaches within 0.5
LSb of its final value, when the volatile Wiper register
changes from zero scale to full scale (or full scale to
zero scale).
B.18 Major-Code Transition Glitch
Major-code transition glitch is the impulse energy
injected into the wiper pin when the code in the Wiper
register changes state. It is normally specified as the
area of the glitch in nV-Sec, and is measured when the
digital code is changed by 1 LSb at the major carry tran-
sition (Example: 01111111 to 10000000, or
10000000 to 01111111).
B.19 Digital Feedthrough
The digital feedthrough is the glitch that appears at the
analog output caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec, and is measured with a full-scale change
(Example: all 0s to all 1s and vice versa) on the digital
input pins. The digital feedthrough is measured when
the digital potentiometer is not being written to the out-
put register.
B.20 Power-Supply Sensitivity (PSS)
PSS indicates how the output (VW or RBW) of the digital
potentiometer is affected by changes in the supply volt-
age. PSS is the ratio of the change in VW to a change
in VL for mid-scale output of the digital potentiometer.
The VW is measured while the VL is varied from 5.5V to
2.7V as a step, and expressed in %/%, which is the %
change of the VW output voltage with respect to the %
change of the VL voltage.
EQUATION B-13: PSS CALCULATION
B.21 Power-Supply Rejection Ratio
(PSRR)
PSRR indicates how the output of the digital potentiom-
eter is affected by changes in the supply voltage. PSRR
is the ratio of the change in VW to a change in VL for full-
scale output of the digital potentiometer. The VW is
measured while the VL is varied +/- 10% (VA and VB
voltages held constant), and expressed in dB or µV/V.
Note: Analog switch leakage increases with
temperature. This leakage increases sub-
stantially at higher temperatures
(> ~100°C). As analog switch leakage
increases, the Wiper output voltage (VW)
decreases, which affects the Total
Unadjusted Error.
MCP45HVX1
DS20005304A-page 96 2014 Microchip Technology Inc.
B.22 Ratiometric Temperature
Coefficient
The ratiometric temperature coefficient quantifies the
error in the ratio RAW/RWB due to temperature drift.
This is typically the critical error when using a digital
potentiometer in a voltage divider configuration.
B.23 Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end resistance (Nominal resistance
RAB) due to temperature drift. This is typically the
critical error when using the device in an adjustable
resistor configuration.
Characterization curves of the resistor temperature
coefficient (tempco) are shown in Sectio n 2.0 “T ypic al
Performance Curves”.
B.24 -3dB Bandwidth
This is the frequency of the signal at the A terminal, that
causes the voltage at the W pin to be -3dB from its
expected value, based on its wiper code. The expected
value is determined by the static voltage value on the A
terminal and the wiper code value.
B.25 Resistor Noise Density (eN_WB)
This is the random noise generated by the device’s
internal resistances. It is specified as a spectral density
(voltage per square root Hertz).
2014 Microchip Technology Inc. DS20005304A-page 97
MCP45HVX1
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP45HV31: Single Potentiometer (7-bit) with I2C™ Interface
MCP45HV51: Single Potentiometer (8-bit) with I2C Interface
Tape and Reel
Option: T = Tape and Reel(1)
“blank” = Tube
Resistance
Version: 502 = 5 k
103 = 10 k
503 = 50 k
104 = 100 k
Temperature
Range: E = -40°C to +125°C
Package: ST = Plastic TSSOP-14, 14-lead
MQ = Plastic QFN-20 (5x5), 20-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP45HV51T-502E/ST
5k, 8-bit, 14-LD TSSOP
b) MCP45HV51T-103E/ST
10 k, 8-bit, 14-LD TSSOP
c) MCP45HV31T-503E/ST
50 k, 7-bit, 14-LD TSSOP
d) MCP45HV31T-104E/MQ
100 k, 7-bit, 20-LD QFN (5x5)
a) MCP45HV51T-502E/MQ
5k, 8-bit, 20-LD QFN (5x5)
b) MCP45HV51T-103E/MQ
10 k, 8-bit, 20-LD QFN (5x5)
c) MCP45HV31T-503E/MQ
50 k, 7-bit, 20-LD QFN (5x5)
d) MCP45HV31T-104E/MQ
100 k, 7-bit, 20-LD QFN (5x5)
XXX
Resistance
Version
[X](1)
Tape and Reel
Option
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
MCP45HVX1
DS20005304A-page 98 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005304A-page 99
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN:978-1-63276-299-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and ds PIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005304A-page 100 2014 Microchip Technology Inc.
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03/25/14
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