0.1 GHz to 13.0 GHz,0.5 dB LSB, 6-Bit,
GaAs Digital Attenuator
Data Sheet
HMC424ACHIPS
Rev. B Document Feedback
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FEATURES
Attenuation range: 0.5 dB (LSB) steps to 31.5 dB
±0.5 dB typical step error
Low insertion loss: 2.8 dB typical at 4.0 GHz
High linearity at VEE = −5 V
Input P0.1dB: 25 dBm typical
Input IP3: 45 dBm typical
High RF input power handling: 25 dBm maximum
Low relative phase: 30° at 6.0 GHz
Single-supply operation: −3 V to −5 V
Die size: 1.390 mm × 0.770 mm × 0.102 mm
APPLICATIONS
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
Intermediate frequency (IF) and RF designs
Military and space
FUNCTIONAL BLOCK DIAGRAM
RF2
HMC424ACHIPS
RF1
V1
16dB
8dB
4dB
2dB
1dB
0.5dB
V2V3
VEE
V4V5V6
13970-001
Figure 1.
GENERAL DESCRIPTION
The HMC424ACHIPS is a broadband, 6-bit, gallium arsenide
(GaAs), digital attenuator monolithic microwave integrated
circuit (MMIC) chip with a 31.5 dB attenuation control range in
0.5 dB steps.
The HMC424ACHIPS offers excellent attenuation accuracy of
±(0.2 dB + 3% of attenuation state) and high input linearity over
the specified frequency range from 0.1 GHz to 13.0 GHz with a
typical insertion loss of ≤4.2 dB. The attenuator bit values are
0.5 dB (LSB), 1 dB, 2 dB, 4 dB, 8 dB, and 16 dB for a total
attenuation of 31.5 dB with a ±0.5 dB of typical step error.
The device allows a user to program the attenuation state via six
parallel control inputs toggled between 0 V and VEE.
The HMC424ACHIPS operates with a single negative supply
voltage from −3 V to −5 V, and requires an external driver to
interface with a CMOS/transistor to transistor logic (TTL)
interface.
The HMC424ACHIPS comes in a RoHS compliant, 9-pad bare die.
HMC424ACHIPS Data Sheet
Rev. B | Page 2 of 11
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 5
Typical Performance Characteristics ............................................. 6
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................6
Input Power Compression and Third-Order Intercept ............8
Theory of Operation .........................................................................9
Power Supply ..................................................................................9
RF Input and Output ....................................................................9
Applications Information .............................................................. 10
Mounting and Bonding Techniques ........................................ 10
Assembly Diagram ..................................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
3/2020—Rev. 01.1115 to Rev. B
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Changes to Title, Features Section, Applications Section, and
General Description Section ........................................................... 1
Changes to Table 1 ............................................................................ 3
Added Table 2, Figure 2, Thermal Resistance Section, and
Table 3; Renumbered Sequentially ................................................. 4
Changes to Table 2 ............................................................................ 4
Deleted Bias Voltage & Current Table and Control Voltage
Table; Renumbered Sequentially .................................................... 5
Added Figure 3, Table 4, and Figure 4 ........................................... 5
Changes to Figure 5 .......................................................................... 5
Added Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase Section, Figure 8, Figure 9, and Figure 12 ........... 6
Changes to Figure 7, Figure 10, and Figure 11 ............................. 6
Added Figure 13, Figure 14, and Figure 16 ................................... 7
Changes to Figure 15 ........................................................................ 7
Deleted Handling Precautions Section, Mounting Section, and
Wire Bonding Section ....................................................................... 7
Added Input Power Compression and Third-Order Intercept
Section, Figure 18 to Figure 20, and Figure 22 .............................. 8
Changes to Figure 17 and Figure 21 ............................................... 8
Added Theory of Operation Section, Power Supply Section, and
RF Input and Output Section ........................................................... 9
Changes to Figure 23 ......................................................................... 9
Added Applications Information Section ................................... 10
Changed Mounting & Bonding Techniques for Millimeterwave
GaAs MMICs Section to Mounting and Bonding Techniques
Section .............................................................................................. 10
Changes to Mounting and Bonding Techniques Section,
Figure 24, and Figure 25 ................................................................ 10
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
Data Sheet HMC424ACHIPS
Rev. B | Page 3 of 11
SPECIFICATIONS
Supply voltage (VEE) = -3 V to -5 V, control input voltage (VCTL) = 0 V or VEE, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 0.1 13.0 GHz
INSERTION LOSS IL 0.1 GHz to 4.0 GHz 2.8 3.3 dB
4.0 GHz to 8.0 GHz 3.4 4.0 dB
8.0 GHz to 13.0 GHz 4.2 4.6 dB
ATTENUATION 0.1 GHz to 13.0 GHz
Range
Between minimum and
maximum attenuation states
31.5 dB
Step Size Between any successive
attenuation states
0.5 dB
Step Error Between any successive
attenuation states
±0.5 dB
State Error All attenuation states,
referenced to insertion loss state
0.1 GHz to 8.0 GHz −(0.2 + 3% of
attenuation state)
+(0.2 + 3% of
attenuation state)
dB
8.0 GHz to 13.0 GHz −(0.2 + 4% of
attenuation state)
+(0.2 + 4% of
attenuation state)
dB
RETURN LOSS (RF1 AND RF2) All attenuation states,
0.1 GHz to 13.0 GHz
12 dB
RELATIVE PHASE Between minimum and
maximum attenuation states
0.1 GHz to 6.0 GHz 30 Degrees
6.0 GHz to 13.0 GHz 70 Degrees
SWITCHING CHARACTERISTICS Between all attenuation states
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 30 ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 50 ns
INPUT LINEARITY1
All attenuation states,
500 MHz to 6.0 GHz
0.1 dB Compression P0.1dB VEE = −3 V 23 dBm
V
EE = −5 V 25 dBm
Third-Order Intercept IP3 VEE = −5 V, 10 dBm per tone,
1 MHz spacing
45 dBm
VEE = −3 V, 10 dBm per tone,
1 MHz spacing
35 dBm
SUPPLY CURRENT IDD V
EE = −3 V to −5 V 2 5 mA
DIGITAL CONTROL INPUTS V1 to V6
Voltage
Low VINL V
EE = −3 V −1.0 0 V
V
EE = −5 V −3.0 0 V
High VINH V
EE = −3 V −3.0 −2.2 V
V
EE = −5 V −5.0 −4.2 V
Current VEE = −3 V to −5 V
Low IINL 35 μA
High IINH 1 μA
1 Input linearity performance degrades at frequencies less than 250 MHz; see Figure 17, Figure 21, and Figure 22.
HMC424ACHIPS Data Sheet
Rev. B | Page 4 of 11
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, VEE −7 V
Digital Control Input Voltage
V
EE
– 0.5 V
RF Input Power1 (All Attenuation States,
f = 0.8 to 13.0 GHz, TCASE = 85°C,
VEE = −3 V to −5 V)
25 dBm
Continuous Power Dissipation, PDISS
(TCASE = 85°C)
0.56 W
Temperature
Junction, TJ 150°C
Storage −65°C to +150°C
ESD Sensitivity, Human Body Model
(HBM)
250 V (Class 1A)
1 For power derating at frequencies less than 800 MHz, see Figure 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
0
–14
–12
–10
–8
–6
–4
–2
0.01 0.10 1.00
POWER DERATING (d B)
FREQUENCY ( GHz)
13970-026
V
EE
= –3V
V
EE
= –5V
Figure 2. Power Derating at Frequencies Less than 0.8 GHz
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type θJC Unit
C-9-21 330 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
ESD CAUTION
Data Sheet HMC424ACHIPS
Rev. B | Page 5 of 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pad No.
Mnemonic
Description
1 RF1 Attenuator RF Input. This pin is dc-coupled and ac matched to 50 Ω. An external dc blocking capacitor is required if
the RF line potential is not equal to 0 V.
2 VEE Power Supply.
3 RF2 Attenuator RF Output. This pin is dc-coupled and ac matched to 50 Ω. An external dc blocking capacitor is
required if the RF line potential is not equal to 0 V.
4 to 9 V1 to V6 Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 5). There is an internal pull-
down resistor on these pins to VEE.
INTERFACE SCHEMATICS
RF1, RF2
13970-003
Figure 4. RF1 and RF2 Interface Schematic
100kΩ VEEV1 TO V6
13970-004
Figure 5. V1 to V6 Interface Schematic
VEE
2kΩ3pF
13970-005
Figure 6. VEE Interface Schematic
HMC424ACHIPS Data Sheet
Rev. B | Page 6 of 11
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
0
–6
–5
–4
–3
–2
–1
0 3 6912 1525811 1414 7 10 13
INSERTION LOSS (dB)
FREQUENCY ( GHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
13970-006
Figure 7. Insertion Loss vs. Frequency over Temperature
0
–50
–35
–40
–45
–30
–25
–15
–20
–5
–10
036 9 12 15
25811 1414710 13
INPUT RET URN LOS S ( dB)
FREQUENCY ( GHz)
16.0dB
4.0dB
1.0dB
0dB
31.5dB
8.0dB
2.0dB
0.5dB
13970-007
Figure 8. Input Return Loss vs. Frequency over Major Attenuation States
2.0
–0.5
0
0.5
1.0
1.5
0 6 12 18 24 32410 16 22 28 302 8 14 20 26
ST ATE ERRO R ( dB)
ATTENUATION STATE (dB)
13.0GHz
8.0GHz
4.0GHz
0.1MHz
13970-008
Figure 9. State Error vs. Attenuation State over Frequency
0
–35
–25
–30
–20
–15
–10
–5
036912 15
25811 14
14710 13
NORM ALIZ E D ATTE NUATION (d B)
FREQUENCY ( GHz)
31.5dB
4.0dB 8.0dB
1.0dB 16.0dB
2.0dB0.5dB
13970-009
Figure 10. Normalized Attenuation vs. Frequency over Major Attenuation
States
0
–70
–50
–60
–40
–30
–20
–10
036912 1525811 1414710 13
OUTPUT RE TURN LOSS ( dB)
FREQUENCY ( GHz)
16.0dB
4.0dB
1.0dB
0dB
31.5dB
8.0dB
2.0dB
0.5dB
13970-010
Figure 11. Output Return Loss vs. Frequency over Major Attenuation States
2.0
–2.0
–1.5
–0.5
–1.0
0
0.5
1.0
1.5
036912 1525811 1414710 13
ST ATE ERRO R ( dB)
FREQUENCY ( GHz)
31.5dB
8.0dB
2.0dB
0.5dB
16.0dB
4.0dB
1.0dB
13970-011
Figure 12. State Error vs. Frequency over Major Attenuation States
Data Sheet HMC424ACHIPS
Rev. B | Page 7 of 11
1.0
–1.0
–0.6
–0.2
0.2
0.6
–0.8
–0.4
0
0.4
0.8
0612 18 24 32410 16 22 28 302814 20 26
STEP ERROR (dB)
ATTENUATION STATE (dB)
13.0GHz
8.0GHz
4.0GHz
0.1MHz
13970-012
Figure 13. Step Error vs. Attenuation State over Frequency
70
–10
0
10
30
20
40
50
60
0 6 12 18 24 32
410 16 22 28 302814 20 26
REL ATIVE P HAS E ( Degrees)
ATTENUATION STATE (dB)
13.0GHz
8.0GHz
4.0GHz
0.1MHz
13970-013
Figure 14. Relative Phase vs. Attenuation State over Frequency
2.0
–2.0
–1.5
–0.5
–1.0
0
0.5
1.0
1.5
036912 15
25811 14
14710 13
STEP ERROR (dB)
FREQUENCY ( GHz)
31.5dB
8.0dB
2.0dB
0.5dB
16.0dB
4.0dB
1.0dB
13970-014
Figure 15. Step Error vs. Frequency over Major Attenuation States
80
–10
0
20
30
10
40
50
60
70
036912 1525811 1414710 13
REL ATIVE P HAS E ( Degrees)
FREQUENCY ( GHz)
31.5dB
8.0dB
2.0dB
0.5dB
16.0dB
4.0dB
1.0dB
13970-015
Figure 16. Relative Phase vs. Frequency over Major Attenuation States
HMC424ACHIPS Data Sheet
Rev. B | Page 8 of 11
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
30
0
15
10
5
20
25
036912 15
25811 14
14710 13
INPUT P0. 1dB (d Bm)
FREQUENCY ( GHz)
VEE = –3V
VEE = –5V
13970-016
Figure 17. Input P0.1dB vs. Frequency at Minimum Attenuation State over
VEE = −5 V and VEE = −3 V
30
0
25
15
20
5
10
0 3 6 9 12 1525 8 11 1414710 13
INPUT P0. 1dB (d Bm)
FREQUENCY ( GHz)
16.0dB
4.0dB
1.0dB
0dB
31.5dB
8.0dB
2.0dB
0.5dB
13970-017
Figure 18. Input P0.1dB vs. Frequency over Major Attenuation States,
VEE = −5 V
30
0
25
15
20
5
10
0 3 6 9 12 152 5 8 11 1414710 13
INPUT P0. 1dB (d Bm)
FREQUENCY ( GHz)
16.0dB
4.0dB
1.0dB
0dB
31.5dB
8.0dB
2.0dB
0.5dB
13970-018
Figure 19. Input P0.1dB vs. Frequency over Major Attenuation States,
VEE = −3 V
50
0
15
10
5
20
25
35
30
45
40
036912 1525811 1414710 13
INPUT IP 3 ( dBm)
FREQUENCY ( GHz)
VEE = –3V
VEE = –5V
13970-019
Figure 20. Input IP3 vs. Frequency at Minimum Attenuation State over
VEE = −5 V and VEE = −3 V
60
0
50
30
40
10
20
0 6 12 14284 10
INPUT IP 3 ( dBm)
FREQUENCY ( GHz)
31.5dB
8.0dB
2.0dB
0.5dB
IL
16.0dB
4.0dB
1.0dB
13970-020
Figure 21. Input IP3 vs. Frequency over Major Attenuation States,
VEE = −5 V
60
0
50
30
40
10
20
0 6 12 142 84 10
INPUT IP 3 ( dBm)
FREQUENCY ( GHz)
31.5dB
8.0dB
2.0dB
0.5dB
IL
16.0dB
4.0dB
1.0dB
13970-021
Figure 22. Input IP3 vs. Frequency over Major Attenuation States,
VEE = −3 V
Data Sheet HMC424ACHIPS
Rev. B | Page 9 of 11
THEORY OF OPERATION
The HMC424ACHIPS incorporates a 6-bit attenuator die that
offers an attenuation range of 31.5 dB in 0.5 dB steps. The
attenuation state is changed by the parallel control voltage
inputs (V1 to V6) directly (see Table 5).
The HMC424ACHIPS allows the user to program the
attenuation state via six parallel control inputs toggled between
0 V and VEE. When interfacing with a TTL/CMOS interface, an
external level shifter is required. An example simple driver
using standard logic ICs provides fast switching while using
minimum dc current. The series resistance is recommended to
suppress unwanted RF signals at the input of the V1 to V6
control lines.
POWER SUPPLY
The HMC424ACHIPS requires a single dc voltage applied to
the VEE pin. The ideal power-up sequence is as follows:
1. Connect the ground reference.
2. Apply a supply voltage to the VEE pin.
3. Power up the digital control inputs. The relative order of
the digital control inputs is not important.
4. Apply an RF input signal to RF1.
The power-down sequence is the reverse of the power-up
sequence.
RF INPUT AND OUTPUT
The attenuator in the HMC424ACHIPS is bidirectional. The
RF1 and RF2 pins are interchangeable as the RF input and
output ports. The attenuator is internally matched to 50 Ω at
both the input and the output. Therefore, no external matching
components are required.
The RF input and output pins of the HMC424ACHIPS are
internally dc biased to 0 V. T herefore, they require external dc
blocking capacitors if the RF line potential is not equal to 0 V.
Select the value of these dc blocking capacitors based on the
minimum operating frequency. Use larger value capacitors to
extend the operation to lower frequencies.
100Ω
10kΩ
TTL
OR
CMOS
V
CC
GND
–5V dc
74HCT04 ( TTL )
OR 74HC04 ( CM OS)
TO GaAs IC
ATTENUATOR
CONTROL INPUTS
V1 TO V6
V
Z
= 5.1V
I
ZT
= 50µA
COMPENSATED
DEVICES
CD4689
13970-022
NOTE
CD4689 IS A ZENER DIODE . VZ IS THE ZENER VOLTAGE, AND IZT
IS THE Z E NE R TEST CURRENT .
Figure 23. Suggested Driver Circuit
Table 5. V1 to V6 Truth Table
Control Voltage Input
V1 (16 dB) V2 (8 dB) V3 (4 dB) V4 (2 dB) V5 (1 dB) V6 (0.5 dB) Attenuation State, RF1 to RF2
Low Low Low Low Low Low Reference insertion loss
Low Low Low Low Low High 0.5 dB
Low Low Low Low High Low 1 dB
Low Low Low High Low Low 2 dB
Low Low High Low Low Low 4 dB
Low High Low Low Low Low 8 dB
High Low Low Low Low Low 16 dB
High High High High High High 31.5 dB
1 Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected.
HMC424ACHIPS Data Sheet
Rev. B | Page 10 of 11
APPLICATIONS INFORMATION
MOUNTING AND BONDING TECHNIQUES
The HMC424ACHIPS is back metallized and must be attached
directly to the ground plane with gold tin (AuSn) eutectic
preforms or with electrically conductive epoxy.
The die thickness is 0.102 mm (4 mil). The 50 Ω microstrip
transmission lines on 0.127 mm (5 mil) thick alumina thin film
substrates are recommended for bringing RF to and from the
HMC424ACHIPS (see Figure 24).
RF G ROUND PL ANE
0.102mm ( 0. 004") THICK GaAs MMIC
RIBBO N BOND
0.127mm ( 0. 005") THICK ALUMI NA
THIN FILM SUBSTRATE
0.076mm
(0.003")
13970-023
Figure 24. Bonding RF Pads to 5 mil Substrate
When using 0.254 mm (10 mil) thick alumina thin film substrates,
the HMC424ACHIPS must be raised 0.150 mm (6 mil) so that the
surface of the HMC424ACHIPS is coplanar with the surface of the
substrate. One way to accomplish this is by attaching the 0.102 mm
(4 mil) thick die to a 0.150 mm (6 mil) thick molybdenum heat
spreader (moly tab), which is then attached to the ground plane
(see Figure 25).
RF G ROUND PL ANE
0.102mm ( 0. 004") THICK GaAs MMIC
RIBBO N BOND
0.254mm ( 0. 010") THICK ALUMI NA
THIN FILM SUBSTRATE
0.150mm
(0. 006” ) THICK
MOLY TAB
0.076mm
(0.003")
13970-024
Figure 25. Bonding RF Pads to 10 mil Substrate
Microstrip substrates are placed as close to the
HMC424ACHIPS as possible to minimize bond length. Typical
die to substrate spacing is 0.076 mm (3 mil).
RF bonds made with 3 mil × 5 mil ribbon are recommended.
DC bonds made with 1 mil diameter wire are recommended.
All bonds must be as short as possible.
ASSEMBLY DIAGRAM
An assembly diagram of the HMC424ACHIPS is shown in
Figure 26.
TO –5V SUPPLY
RF AND DC BONDS
1mm GO LD WIRE
50Ω
TRANSMISSION
LINE
3mm
NOMINAL
GAP
13970-025
Figure 26. Assembly Diagram
Data Sheet HMC424ACHIPS
Rev. B | Page 11 of 11
OUTLINE DIMENSIONS
07-19-2019-A
0.102
SIDE VIEW
TOP VIEW
(CIRCUIT SIDE)
1.390
0.437
0.217
0.1700.1700.1700.1700.1700.157
0.788
0.770
0.082
0.082
0.227
0.212
0.358
0.212
0.043
1
2
456789
3
Figure 27. 9-Pad Bare Die [CHIP]
(C-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code2
HMC424A −40°C to +85°C 9-Pad Bare Die [CHIP] C-9-2 H424A
XXXX
HMC424A-SX −40°C to +85°C 9-Pad Bare Die [CHIP] C-9-2 H424A
XXXX
1 All models are RoHS compliant.
2 XXXX is the 4-digit lot number.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13970-3/20(B)