SK70704/SK70706
784 Kbps HDSL Data Pump Chip Set
Datasheet
The HDSL Data Pump is a chip set consisting of the following two devices:
■SK70704 Analog Core Chip (ACC)
■SK70706 HDSL Digital Transceiver (HDX)
The HDSL Data Pump is a 2-wire transceiver which provides echo-cancelling and 2B1Q line
coding. It incorporates transmit pulse shaping, filtering, line drivers, receive equalization, timing
and data recovery to provide 784 kbps, clear-channel, “data pipe” transmission. The Data Pump
provides Near-End Cross-Talk (NEXT) performance in excess of that required over all ANSI
and ETSI test loops. Typical transmission range on 26 AWG (0.4 mm) cable exceeds 13 kft (4
km) in a noise-free environment or 9.5 kft (2.9 km) with ANSI-specified noise levels.
The Data Pump meets the requirements of Bellcore TA-NWT-001210, ANSI T1 Technical Report
No. 28-1994 and ETSI ETR-152. It provides one end of a single-channel HDSL transmission
system from the twisted pair interface back to the Data Pump/HDSL data interface. The Data
Pump can be used at either the HTU-R or the HTU-C end of the interface.
Applications
Product Features
■T1 (2-pair) and fractional T1 transport
■N-channel digital pair-gain
■Wireless base station to switch interface
■Campus and private networking
■Fully integrated, 2-chip set for interfacing
to 2-wire HDSL lines at 784 kbps
■Single +5 V power supply
■Integrated line drivers, filters and hybrid
circuits result in greatly reduced external
logic and simplified support circuitry
requirements
■Simple line interface circuitry, via
transformer coupling, to twisted pair line
■Internal ACC voltage reference
■Converts serial binary data to scrambled
2B1Q encoded data
■Self-contained activation/start-up state
machine for simplified single loop designs
■Programmable for either central office
(HTU-C) or remote site (HTU-R)
applications
■
■Compliant with:
■– Bellcore TA-NWT-001210
■– ANSI HDSL Technical Report No. 28-
1994
■– ETSI ETR-152 (1995)
■– ITU G.991.1
■Design allows for operation in either
Software Control or stand-alone Hardware
Control mode
■Typical power consumption is less than 1.0
W allowing remote power feeding for
repeater and
HTU-R equipment
■Input or Output Reference Clock of 12.544
MHz
■Digital representation of receive signal
level and noise margin values available for
SNR controlled activation
As of January 15, 2001, this document replaces the Level One document Order Number: 249192-001
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set. January 2001
Datasheet
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
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whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The SK70704/SK70706 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
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Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet 3
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Contents
1.0 Pin Assignments and Signal Descriptions......................................................8
2.0 Functional Description...........................................................................................15
2.1 Transmit ..............................................................................................................15
2.2 Receive ...............................................................................................................15
2.3 Control.................................................................................................................15
2.4 Component Description.......................................................................................15
2.4.1 Analog Core Chip (ACC) ........................................................................15
2.4.2 HDSL Digital Transceiver (HDX) ............................................................16
2.4.3 HDX/ACC Interface ................................................................................17
2.5 Line Interface.......................................................................................................18
2.6 HDSL Data Interface ...........................................................................................19
2.7 Microprocessor Interface (HDX)..........................................................................22
2.7.1 Control Pins............................................................................................22
2.7.2 Register Access .....................................................................................23
2.8 Activation State Machines ...................................................................................31
2.8.1 HTU-C Data Pump Activation.................................................................31
2.8.2 HTU-C Framer Activation .......................................................................32
2.8.3 HTU-R Data Pump Activation.................................................................34
2.8.4 HTU-R Framer Activation .......................................................................34
2.8.5 HDSL Synchronization State Machine ...................................................34
3.0 Application Information.........................................................................................38
3.1 HDSL Framer State Machine
Design38
3.2 PCB Layout .........................................................................................................38
3.2.1 Digital Section ........................................................................................38
3.2.2 Analog Section .......................................................................................39
3.2.3 User Interface.........................................................................................39
4.0 Test Specifications..................................................................................................45
5.0 Mechanical Specifications....................................................................................55
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
4 Datasheet
Figures
1 SK70704/SK70706 Bolck Diagram .......................................................................7
2 Package Markings.................................................................................................7
3 SK70704 ACC Pin Locations ................................................................................8
4 SK70706 HDX Pin Assignments .........................................................................10
5 HDX/ACC Interface – Relative Timing ................................................................18
6 HDX/ACC Framer Interface – Relative Timing.................................................... 20
7 Model for HDSL Data Pump and HDSL Framer Applications .............................22
8 HTU-C Data Pump Activation State Machine .....................................................33
9 HTU-C HDSL Framer Activation State Machine .................................................33
10 HTU-R Data Pump Activation State Machine .....................................................35
11 HTU-R HDSL Framer Activation State Machine .................................................36
12 HDSL Synchronization State Machine ................................................................37
13 PCB Layout Guidelines ....................................................................................... 40
14 Typical Support Circuitry for HTU-C Applications ...............................................41
15 Typical Support Circuitry for HTU-R Applications ...............................................43
16 SK70706 HDX Control and Status Signals (Stand-alone Mode) ........................44
17 ACC Normalized Pulse Amplitude Transmit Template ....................................... 46
18 ACC Transmitter Timing......................................................................................47
19 ACC Transmit Power Spectral Density ...............................................................47
20 ACC Receiver Syntax and Timing....................................................................... 48
21 HDX/HDSL Data Interface Timing....................................................................... 50
22 RESET and INTERRUPT Timing (mP Control Mode) ........................................53
23 Parallel Data Channel Timing .............................................................................54
24 Data Pump Package Specifications ....................................................................55
Tables
1 SK70704 ACC Pin Assignments/Signal Descriptions ...........................................8
2 SK70706 HDX Pin Assignments/Signal Descriptions .........................................10
3 ACC Transmit Control .........................................................................................16
4 HDX/ACC Serial Port Word Bit Definitions (See Figure 5)................................ 18
5 HDSL Framer TDATA Requirements..................................................................19
6 Register Summary ..............................................................................................24
7 Main Control Register WR0 ................................................................................ 25
8 InInterrupt Mask Register WR2........................................................................... 25
9 Read Coefficient Select Register WR3 ...............................................................26
10 Main Status Register RD0................................................................................... 26
11 Receiver Gain Word Register ............................................................................ 27
12 Noise Margin Register RD2
(Noise Margin Coding)28
13 Coefficient Read Register ...................................................................................29
14 Activation Status Register RD5...........................................................................29
15 Receiver AGC and FFE Step Gain Register RD6...............................................30
16 Data Pump/Framer Activation State Machine Correspondences........................32
17 Activation – Synchronization ...............................................................................34
18 Components for Suggested Circuitry (Figure 14 and Figure 15) ........................41
19 Transformer Specifications
(Figure 14 and Figure 15, Reference T1)42
20 Crystal Specifications
Datasheet 5
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
(Figure 14 and Figure 15, Reference Y1)42
21 ACC Absolute Maximum Ratings ........................................................................45
22 ACC Recommended Operating Conditions.........................................................45
23 ACC DC Electrical Characteristics (Over Recommended Range) ......................45
24 ACC Transmitter Electrical Parameters (Over Recommended Range) ..............46
25 ACC Receiver Electrical Parameters (Over Recommended Range) ..................47
26 HDX Absolute Maximum Ratings ........................................................................48
27 HDX Recommended Operating Conditions.........................................................48
28 HDX DC Electrical Characteristics (Over Recommended Range) ......................49
29 HDX/HDSL Data Interface Timing Specifications (Figure 19) .............................51
30 HDX/Microprocessor Interface Timing Specifications (Figure 21 and Figure 22)51
31 General System and Hardware Mode Timing .....................................................52
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
6 Datasheet
Revision History
Revision Date Description
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 7
Figure 1. SK70704/SK70706 Bolck Diagram
Figure 2. Package Markings
Package Topside Markings
Marking Definition
Part # Unique identifier for this product family.
Rev # Identifies the particular silicon “stepping” — refer to the specification update for additional stepping
information.
Lot # Identifies the batch.
FPO # Identifies the Finish Process Order.
AGC
o
Back
End
Control
Logic
Σ
Deci-
mation
Filter
Σ
DFE
Phase
Detector
CK6M
TDATA
TFP
RDATA
RFP
ICLK
HTUC
LOSW
REFCLK
DATA
ADDR
CTRL
ACC
Line
Driver
A/D
Modulator
Σ
Σ
VCO
To Various
Blocks
VPLL
TCK3M
TSGN
TMAG
AD0
AD1
AGCKIK
CK25M
FS
DTR
HDX
XO
XI
IBIAS
BTIP
RRING
BRING
RTIP
TTIP
TRING
VREF
Tx
Filter
Activation
Control
Decision
Circuit
FFE
DAGC
AGC
Tap
Echo
Canceller
2B1Q
Encoder
Serial
I/F
Scrambler
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
8 Datasheet
1.0 Pin Assignments and Signal Descriptions
The ACC is packaged in a 28-pin PLCC. Figure 3 shows the ACC pin locations. Table 1 lists signal
descriptions for each pin, except pins 18 and 19, which are not connected.
The HDX is packaged in a 44-pin PLCC. Figure 4 shows the HDX pin locations. Table 2 lists
signal descriptions for each pin, including pin 29, which is not connected.
Figure 3. SK70704 ACC Pin Locations
Table 1. SK70704 ACC Pin Assignments/Signal Descriptions
Group Pin # Symbol I/O1Description
Line
13 RTIP AI Receive Tip and Ring inputs. Connect these pins to the line transformer per
network requirements.
14 RRING AI
16 BTIP AI Bias Tip and Ring. Inputs provide a bias setting for the receiver. Provide
balanced network inputs.
17 BRING AI
21 TTIP AO Transmit Tip and Ring. Line driver outputs.
22 TRING AO
PLL
7XOAO
Crystal Oscillator. Connect a 25.088 MHz crystal across these two pins.
8XIAI
9VPLLAOPLL Voltage Control. Supplies control voltage to the VCO.
1. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
123
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
262728
ACC
SK70704
AD1
AD0
FS
DTR
CK25M
DGND
XO
XI
VPLL
PGND
IBIAS
TMAG
TCK3M
AGCKIK
RGND
RRING
RTIP
RVCC
n/c
BRING
BTIP
TSGN
DVCC
TVCC
TRING
TTIP
TGND
n/c
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 9
Power
10 PGND S PLL Ground. 0 V.
12 RVCC S Receive Power supply. +5 V (± 5%).
23 TVCC S Transmit Power supply. +5 V (± 5%).
24 DVCC S Digital Power Supply. +5 V (± 5%).
6DGNDSDVCC Ground. 0 V.
15 RGND S RVCC Ground. 0 V.
20 TGND S TVCC Ground. 0 V.
Clock and
Control
3FSDI392 kHz Clock Input. From HDX FS.
4DTRDISerial Control Data. Input from HDX at 12.544 Mbps.
5 CK25M DO 25.088 MHz HDSL Reference Clock. Used as the receive timing reference
for the HDX. Tie to HDX CK25M.
27 TCK3M DI 3.136 MHz Clock. Input from HDX TCK3M.
Data Input
and
Output
28 AGCKIK DO AGC Adjust Signal. Output to HDX AGCKIK.
1 AD1 DO A-to-D Converter Data Line 1. Connect to HDX AD1.
2 AD0 DO A-to-D Converter Data Line 0. Connect to HDX AD0.
25 TSGN DI Transmit Quat Sign. Input from HDX.
26 TMAG DI Transmit Quat Magnitude. Input from HDX.
Analog
Input 11 IBIAS AI Input Bias. Provides input bias current.
Table 1. SK70704 ACC Pin Assignments/Signal Descriptions (Continued)
Group Pin # Symbol I/O1Description
1. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
10 Datasheet
Figure 4. SK70706 HDX Pin Assignments
Table 2. SK70706 HDX Pin Assignments/Signal Descriptions
Group Pin # Symbol I/O4Description
Power
1 VCC1 S Logic supply input. (Refer to Table 27)
44 VCC2 S I/O supply input.
2 GND1 S Ground.
3 GND2 S Ground.
28 GND3 S Ground.
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. The period is 6 ms ±1/392 ms.
3. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
4. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
HDX
SK70706
FS
DTR
CK25M
RESET2
AGCKIK
AD1
AD0
17
16
15
14
13
12
11
10
9
8
7
ICLK
HTU-C
CK6MEN
CK6M
REFCLK
TFP
TDATA
RFST
ADDR3(ACTVNG)
RDATA
RFP
n/c
LOSW
RESET1
INT(TEXP)
CHIPSEL
WRITE
READ
D0(LOST, LOS)
D1(LOSWT)
D2(ILMT)
D3(RPTR)
TCK3M
GND3
TSGN
TMAG
GND2
ADDR0(QUIET)
ADDR1(ACTREQ)
ADDR2(LOOPID)
VCC2
VCC1
GND1
D7(TXTST)
D4(FELB)
D5(BELB)
D6(RCLKU)
NOTE: Pin Functions in Hardware Control Mode are shown in parentheses.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 11
User Port
10 RFST DO Receive Frame and Stuff Bit Indicator. Goes High for 18 consecutive ICLK
periods to indicate four stuffing bits (b4703 - 4706) and 14 frame bits (b1-14)
on RDATA.
13 REFCLK DI1
DO
12.544 MHz HDSL Reference Clock. In HTU-C Mode, this clock generates
transmit and receive timing and must have ±32 ppm accuracy.
In HTU-R Mode, this output is derived by dividing CK25M by two.
16 HTU-C DI Operation Mode Select. When HTU-C is High, the Data Pump operates in
HTU-C mode; when HTU-C is Low, the Data Pump operates in HTU-R mode.
Tied to internal pull-up device.
17 ICLK DO Bit Rate Clock. Nominally 784 kHz, REFCLK is the source of ICLK in HTU-C
Mode. CK25M is the source of ICLK in HTU-R Mode.
30 LOSW DO Loss of Sync Word Indicator. Normally Low in Active States, goes High to
indicate receipt of six consecutive mismatched frame synch words. LOSW is
logic High in all states except Active States.
8 RDATA DO
Receive HDSL Data Stream. Output data to HDSL framer at 784 kbps:HDSL
payload of Loop 1 or Loop 2 bytes plus the F-bits, eoc, crc, losd, febe, ps,
bpv, hrp, indc/indr and uib bits, Sync bits for frame positions b1-14, Stuff bits
for frame positions b4703 - 4706. RDATA bits are forced high in all states
except the Active State.
7RFPDO
Receive Frame Pulse. Low for one ICLK cycle during the last bit of the
current HDSL receive frame on RDATA, either b4702 or b4706. Period is within
one baud time of 6 ms.2 RFP is valid when LOSW transitions Low.
11 TDATA DI1
Transmit HDSL Data Stream. Input data from HDSL framer at
784 kbps:HDSL payload of Loop 1 or Loop 2 bytes plus the F-bits, eoc, crc,
losd, febe, ps, bpv, hrp, indc/indr and uib bits, Sync bits for frame positions b1-
14, Stuff dummy bits; may be 1s or 0s. Tied to internal pull-up device. When
ACTIVE, the Data Pump is transparent and the HDSL framer must generate
the appropriate bits on TDATA as shown in Table 5.
12 TFP DI1
Transmit Frame Pulse. Should be Low for one ICLK cycle the during last bit
of the current HDSL frame on TDATA, either b4702 or b4706. Period is within
one baud time of 6 ms.2 If TFP is pulled Low and is Low again three ICLK
cycles later, RDATA, RFP, RFST, ICLK, CK6MEN, and LOSW go to tri-state.
Tied to internal pull-up device.
Table 2. SK70706 HDX Pin Assignments/Signal Descriptions (Continued)
Group Pin # Symbol I/O4Description
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. The period is 6 ms ±1/392 ms.
3. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
4. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
12 Datasheet
Hardware
Interface
(Hardware
Control
Mode)
4 QUIET DI3Quiet Mode Enable. Pull High to force HDX into Deactivated State. Any later
transition to Low will not return HDX to Active State. See ACTREQ.
5 ACTREQ DI3Activation Request (HTU-C mode) or no function (HTU-R mode). Tie this
pin Low in HTU-R mode. If QUIET is Low, a rising edge on this pin initiates
activation, but the signal is ignored after activation. See QUIET.
6 LOOPID DI3/O
Loop Number Control (HTU-C mode) or Loop Number Indicator (HTU-R
mode). Low = loop 1; High = loop 2. Input Signal for HTU-C mode, output for
HTU-R mode. In HTU-R mode valid only when LOSW is Low.
Note: The ETSI recommendation uses overhead bits for loop identification.
9ACTVNGDOActivating State Indication. High when the HDX is in the Activating State.
18 RESET2 DI1Reset Pulse. Pull Low on power up to initialize circuits and stop all clocks.
31 RESET1 DI1Reset Pulse. Pull Low to initialize internal circuits.
32 TEXP DO Timer Expiry. Goes High to indicate 30 second timer expiration in all states.
33 CHIPSEL DI3Chip Select Assert these three pins Low to activate Hardware Control
Mode. When any of them goes High, the HDX reverts
immediately to Software Control Mode.
34 WRITE DI3Write Pulse
35 READ DI3Read Pulse
36
LOST
(HTU-C) DO
Loss of Signal Timer Expiration. In HTU-C mode, LOST goes High when
the Data Pump enters the Inactive State. The transition from the Deactivated to
the Inactive State occurs 1 second after the end of transmission by the HTU-R
when deactivation began from either the Active-1 or Active-2 State. When the
Data Pump transitions from the Activating State to the Deactivated State it may
immediately enter the Inactive State without waiting for HTU-R transmission to
cease (Figure 8).
LOS
(HTU-R) DO Loss of Signal Energy Indicator. In HTU-R mode LOS goes High to indicate
loss of signal energy on entering the Inactive State (Figure 10).
37 LOSWT DO Loss of Sync Word Timer. LOSWT goes High when LOSW is sustained for
longer than 2 sec.
38 ILMT DI1
Insertion Loss Measurement Test. Set High to transmit a framed &
scrambled, “all 1s”, 2B1Q pulse sequence. Pulse sequence will have a valid
sync word. In the HTU-R configuration, when the ILMT mode is selected, the
Data Pump may begin activation.
39 RPTR DI1Repeater Mode Enable. When in HTU-C mode, ICLK output phase is aligned
to the TFP input pulse width. Ignored in HTU-R mode.
40 FELB DI1
Front-End Loopback (HTU-C only). In Inactive State, set High to cause the
ACC to loopback. The returned signal activates the HDX which receives its
own transmitted data. The system ignores incoming data from HTU-R during
loopback irrespective of status.
Table 2. SK70706 HDX Pin Assignments/Signal Descriptions (Continued)
Group Pin # Symbol I/O4Description
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. The period is 6 ms ±1/392 ms.
3. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
4. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 13
Hardware
Interface
(Hardware
Control
Mode)
-cont’d
41 BELB DI1Back-End Loopback. In Active State a High forces an internal, transparent
loopback with RDATA connected to TDATA and RFP connected to TFP.
42 RCLKU DO
Receive Baud Rate (392 kHz) Clock. Aligned with ICLK in HTU-R mode,
phase synchronous with receive pulse stream, However, during Activating
State, the clocks may not be aligned. In the HTU-C mode RCLKU has a
constant, arbitrary, phase relationship with ICLK in Active State.
43 TXTST DI1
Transmit Test. Set high to enable isolated transmit pulse generation. The
time between pulses is approximately 6 ms. TDATA controls the sign and TFP
controls the magnitude of the transmitted quat pulses according to the 2B1Q
encoding rules. In the HTU-R configuration, when the TXTST mode is
selected, the Data Pump may begin activation.
Processor
Interface
(Software
Control
Mode)
36
37
38
39
40
41
42
43
D0
D1
D2
D3
D4
D5
D6
D7
DI1/O
DI1/O
DI1/O
DI1/O
DI1/O
DI1/O
DI1/O
Data bit 0. Eight-bit, parallel data bus.
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
4
5
6
9
ADDR0
ADDR1
ADDR2
ADDR3
DI3
DI3
DI3
DI3
Address bit 0. Four-bit address, selects read or write register.
Address bit 1
Address bit 2
Address bit 3
18 RESET2 DI1Reset Pulse. Pull Low on power up to initialize circuits and stop all clocks.
31 RESET1 DI1Reset Pulse. Pull Low to initialize internal circuits. ICLK continues.
32 INT DO Interrupt Output. Open drain output. Requires an external 10 kΩ pull up
resistor. Goes Low on interrupt.
33 CHIPSEL DI3Chip Select. Pull Low to read or write to registers.
34 WRITE DI3Write Pulse. Pull Low to write to registers.
35 READ DI3Read Pulse. Pull Low to read from registers.
Misc. 29 n/c –No internal connection.
Table 2. SK70706 HDX Pin Assignments/Signal Descriptions (Continued)
Group Pin # Symbol I/O4Description
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. The period is 6 ms ±1/392 ms.
3. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
4. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
14 Datasheet
Clock and
Control
14 CK6M DI36.272 or 12.544 MHz Reference Clock. Mandatory in HTU-R mode. Tie High
or Low in HTU-C Mode. Clock input requires ± 32 ppm accuracy.
15 CK6MEN DO CK6M Enable. Active High enable for CK6M clock. In HTU-R mode, this pin
goes Low to indicate the PLL is tracking the input signal from the
HTU-C. Not used in HTU-C.
19 CK25M DI Receive Timing Clock (25.088 MHz). Tie to CK25M on ACC.
20 DTR DO Serial Control Data Link. Transfers data at 12.544 Mbps. Tie to DTR on
ACC.
21 FS DO 392 kHz Clock . Derived from CK25M. Tie to FS on ACC.
22 AD0 DI Analog to Digital Converter input pin. Tie to AD0 on ACC.
23 AD1 DI Analog to Digital Converter input pin. Tie to AD1 on ACC.
24 AGCKIK DI AGC Adjust Signal. Controls analog gain circuit. Tie to AGCKIK on ACC.
25 TCK3M DO Transmit Clock. Tie to TCK3M on ACC.
26 TMAG DO Transmit Magnitude Bit. Tie to TMAG on ACC.
27 TSGN DO Transmit Sign Bit. Tie to TSGN on ACC.
Table 2. SK70706 HDX Pin Assignments/Signal Descriptions (Continued)
Group Pin # Symbol I/O4Description
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. The period is 6 ms ±1/392 ms.
3. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
4. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 15
2.0 Functional Description
The HDSL Data Pump is a fully-integrated, two-chip solution (see block diagram on front page)
which includes an SK70704 Analog Core Chip (ACC) and an SK70706 HDSL Digital Transceiver
(HDX).
2.1 Transmit
The transmit data stream is supplied to the HDX at the TDATA input in a binary fashion. The HDX
scrambles and 2B1Q encodes the data and adds the sync word and stuff quats based on the TFP
frame pulse position. The injected stuff quats in a frame are equal to the last scrambled data symbol
in that frame. The 2B1Q encoded transmit quat data stream (TSGN / TMAG) is then passed to the
ACC which filters and drives it onto the line. For additional details on the transmit function, refer
to Component Description.
2.2 Receive
The composite waveform of the receive signal plus trans-hybrid echo is filtered and converted to
digital words at a rate of 392 k-words/second in the ACC. The ACC passes the digitized receive
quat stream (AD0 and AD1) to the HDX. The HDX performs digital filtering, linear echo
cancellation, frame recovery and descrambling. The HDX uses the transmit quat stream to generate
the echo estimates and estimate error values. Using this error and the delayed transmit quat stream,
the echo canceller coefficients are updated. The recovered, decoded and descrambled data is then
output to the framer-mux from the HDX RDATA pin. For additional details on the receive function,
refer to Component Description.
2.3 Control
The Data Pump offers two control modes - Hardware Mode and Software Mode. In Hardware
mode the HDX receives control inputs via individually designated pins. In Software mode the
HDX control data is supplied via an 8-bit parallel port. In either mode, communication between the
HDX and the ACC is established via a unidirectional serial port (DTR).
2.4 Component Description
The following paragraphs describe the chip set components individually with reference to internal
functions and the interfaces between Data Pump components.
2.4.1 Analog Core Chip (ACC)
The ACC incorporates the following analog functions:
•the transmit driver
•transmit and receive filters
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
16 Datasheet
•Phase-Locked Loop (PLL)
•hybrid circuitry analog-to-digital converter
The ACC provides the complete analog front end for the HDSL Data Pump. It performs transmit
pulse shaping, line driving, receive A/D, and the VCO portion of the receiver PLL function.
Transmit and receive controls are implemented through the serial port. The ACC line interface uses
a single twisted pair line for both transmit and receive. Table 2 lists the ACC pin descriptions.
Refer to Test Specifications for ACC electrical and timing specifications.
2.4.1.1 ACC Transmitter
The ACC performs the pulse shaping and driving functions. The ACC transmitter generates a 4-
level output of 1/(8*f(TCK3M)) defined by TMAG and TSGN. Table 3 lists 2B1Q pulse coding
parameters. Refer to Test Specifications for frequency and voltage templates.
2.4.1.2 ACC Receiver
The ACC receiver is a sophisticated sigma-delta converter. It sums the differential signal at RTIP/
RRING minus the signal at BTIP/BRING. The first A/D signal comes out of AD0 at a bit stream
rate of 12.544 MHz. The second stage of the A/D samples the noise of the first and generates the
AD1 bit stream at 12.544 MHz.
Receiver gain is controlled by the HDX via the AGC2-0 bits in the DTR serial control stream. The
AGCKIK output from the ACC is normally Low. It goes High when the signal level in the sigma
delta A/D is approaching its clipping level, signaling the HDX to lower the gain.
The VCO is part of a phase-locked loop (PLL) locked to the receive data baud rate using an
external phase detector. The VCO frequency is varied by pulling an external crystal with external
varactor diodes that are controlled by the VPLL output. The VPLL output is, in turn, controlled by
the serial port VCO and PLL bits.
2.4.2 HDSL Digital Transceiver (HDX)
The HDX incorporates the following digital functions:
•bit-rate transmit and receive signal-processing
•adaptive Echo-Cancelling (EC)
•adaptive decision feedback-equalization (DFE) using the receive quat stream and the internal
error signal
•fixed and adaptive digital-filtering functions
•activation/start-up control and the microprocessor interface to the HDSL framer.
Table 3. ACC Transmit Control
TSGN TMAG Output Symbol (quat)
10 +3
11 +1
01 -1
00 -3
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 17
The HDX also provides the Data Pump Back-End interface for the customer defined/developed
HDSL framer via serial data channels and clock signals. A simple, parallel 8-bit microprocessor
interface on the HDX allows high-speed access to control, status and filter coefficient words.
Table 2 lists the HDX pin descriptions. Refer to Test Specifications for HDX electrical and timing
specifications.
The microprocessor interface on the HDX provides bit flags for signal presence, synchronization,
activation completion, and loss of synchronization for a time greater than two seconds. Single-byte
words representing receive signal level and the noise margin of the transceiver are also available on
the microprocessor interface. One control byte allows the user to start the Data Pump activation
sequence. The HDX controls the complete activation/start-up sequence, allowing flexible, single-
loop, fractional applications.
2.4.3 HDX/ACC Interface
The ACC provides the 25.088 MHz master clock, CK25M, to the HDX. The serial control stream
framing signal FS is sampled inside the ACC with the CK25M rising edge. The serial control
stream, DTR, is sampled inside the ACC by the rising edge of an internally-generated clock at
f(CK25M)/2. This ACC internal clock has the same phase relationship with a similar clock inside
the HDX, as established by the FS signal. In the HDX, the half-rate clock CK25M/2 and FS
transition on the rising edge of CK25M, and DTR transitions coincide with the falling edge of
CK25M/2. The output REFCLK in HTU-R Mode is equal to CK25M/2.
The A/D converter outputs, AD0 and AD1, are clocked out of the ACC with CK25M, having
transitions coincidental with the rising edge of CK25M/2. The HDX samples AD0 and AD1 with
the falling edge of its internal CK25M/2.
Transmit data, represented by TSGN and TMAG, is clocked from the HDX using the falling edge
of TCK3M, the 3.136 MHz (f(REFCLK)/4) transmit time base clock. The ACC uses the rising
edge of TCK3M to sample TSGN and TMAG. TSGN and TMAG change state at the baud rate, or
every 8 cycles of TCK3M. Figure 5 shows relative timing for the HDX/ACC interface.
2.4.3.1 HDX/ACC Serial Port
The HDX continually writes to the ACC serial port. This serial stream consists of two 16-bit words
as shown in Table 4. The data flows from the HDX to the ACC at a rate of f(CK25M)/2. Refer to
the Test Specifications section for serial port timing relationships and electrical parameters.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
18 Datasheet
2.5 Line Interface
The Data Pump line interface consists of three differential pairs. The transmit outputs TTIP and
TRING, receive inputs RTIP and RRING, and the balance inputs BTIP and BRING, all connect
through a common transformer to a single twisted-pair line (see Figure 14 and Figure 15). The
transmit outputs require resistors in series with the transformer. A passive prefilter is required for
the receive inputs. The balance inputs feed the transmit signals back to the Data Pump providing
passive echo cancellation. Protection circuitry should be inserted between all Data Pump line
interface pins and the transformer. Refer to the Applications section for typical schematics.
Figure 5. HDX/ACC Interface – Relative Timing
CK25M
TCK3M
CK25M/2
AD0
AD1
DTR
FS
B1 B0 A15 A14 A13 B15
A1 A0
Table 4. HDX/ACC Serial Port Word Bit Definitions (See Figure 5)
Bit Word A (on DTR) Word B (on DTR)
15 INIT COR4
14 n/a COR3
13 n/a COR2
12 TXOFF COR1
11 TXDIS COR0
10 TXTST VCO2
9AGC2 VCO1
8AGC1 VCO0
7 AGC0 PLL7
6 FELB PLL6
5 n/a PLL5
4 PTR4 PLL4
3 PTR3 PLL3
2 PTR2 PLL2
1 PTR1 PLL1
0 PTR0 PLL0
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 19
2.6 HDSL Data Interface
The HDSL data interface includes the transmit and receive binary data streams, transmit and
receive frame pulses, the 784 kHz clock (ICLK) and the receive frame and stuff quat indicator
(RFST). Figure 6 shows relative timing for the framer interface. Refer to Test Specifications
section for details on the Data Pump/framer interface. Figure 7 shows a complete HDSL system
with both the remote HTU-R and central office HTU-C HDSL framer interfaces illustrated. Table 5
shows the TDATA requirements for the framer interface through the activation sequence. Once the
ACTIVE 0-to-1 transition occurs, the Data Pump becomes transparent. Therefore, the HDSL
framer must supply appropriate data to TDATA. Table Table 5 summarizes this requirement.
Table 5. HDSL Framer TDATA Requirements
Activation Process TDATA
Framer Data Pump Overhead Data
Idle Activating don’t care don’t care
Idle Active 1 live all 1s
Active-R Active 1 live all 1s
Active-T Active 1 live live
Link Active Active 1 live live
Link Active Active 2 live live
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
20 Datasheet
The HDSL framer interface is subject to the following rules:
1. When frame sync is not present (LOSW is High), all RDATA bits are set to 1.
Figure 6. HDX/ACC Framer Interface – Relative Timing
b4699 b4700 b4701 b4702 b1 b2 b3 b4
A) Transmit Timing–Without Stuff Bits
ICLK
TFP
TDATA
b4699 b4700 b4701 b4702 b1 b2 b14 b15
C) Receive Timing–Without Stuff Bits
ICLK
RFP
RDATA
RFST
b4701 b4702 b4703 b4704 b4705 b4706 b1 b2
B) Transmit Timing–With Stuff Bits
ICLK
TFP
TDATA
b4702 b4703 b4704 b1 b15b14b4705 b4706
D) Receive Timing–With Stuff Bits
ICLK
RFP
RDATA
RFST
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 21
1. If frame sync is lost on both Data Pump-R1 and Data Pump-R2, both units will fall back on the
local reference frequency with ± 32 ppm tolerance, and stuff bits will be injected in their
RDATA streams on every other frame. If frame sync is lost on either Data Pump-R1 or Data
Pump-R2, that unit can be made to fall back on the REFCLK from the Data Pump-R which is
still in frame sync, and stuff bits will be injected in the RDATA stream on every other frame of
the out-of-frame Data Pump-R.
2. If frame sync is lost on either Data Pump-C1 or Data Pump-C2, the receiver in each unit will
fall back on the reference clock with ± 32 ppm or ± 5 ppm tolerance, and inject stuff bits in the
RDATA stream on every other frame.
3. If either T1-R or T1-C loses sync or signal, it is assumed that the corresponding T1 receiver
will fall back on a local reference with ± 32 ppm tolerance, and that transmit bit-stuffing
control will still be applied through the TFP signal from the HDSL framer.
4. The HDSL framer should provide TFP signal with a period of 6 ms ± 1/392 ms prior to an
activation request for the HTU-C Data Pump(s). The framer should provide a valid TFP after
power-up, before or immediately after LOS goes Low for the HTU-R Data Pump(s).
5. If for any reason the TFP signal from the HDSL framer is inactive (always High or
unconnected), then the Data Pump will inject stuff bits in the TDATA stream in every other
frame, although the Data Pump will not be synchronized to the HDSL framer. When a new
TFP is provided the Data Pump will immediately reset the transmit frame alignment, typically
causing loss of alignment at the other end.
6. A simultaneous RESET2 to all HTU-C Data Pumps which use a common REFCLK eliminates
phase shift between the ICLK outputs which may exist after power-up.
The ICLK outputs of all HTU-R Data Pumps may have an arbitrary phase difference even us-
ing a common CK6M reference.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
22 Datasheet
2.7 Microprocessor Interface (HDX)
Three primary control pins, CHIPSEL (Chip Select), READ and WRITE, execute the Software
Mode which also uses an interrupt output pin to report status changes. Four additional pins are used
for the parallel bus addressing and eight pins for data I/O. Refer to Test Specifications for
microprocessor interface timing in Software Mode.
2.7.1 Control Pins
Chip Select: The Chip Select (CHIPSEL) pin requires an active Low signal to enable Data Pump
read or write transfers over the data bus. To enable Hardware Mode hold this pin Low, along with
READ and WRITE.
Figure 7. Model for HDSL Data Pump and HDSL Framer Applications
HDSL
Framer
-R
DP-R1
DP-R2
HTU-R
Local Xtal
Osc
TDATA
TFP
LOSW
ICLK
RDATA
RFP
RFST
RFCLK
TDATA
TFP
LOSW
ICLK
RDATA
RFP
RFST
To T1 I/F
(T1-R)
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
RFCLK
HDSL
Framer
-C
DP-C1
DP-C2
HTU-C
TDATA
TFP
LOSW
ICLK
RDATA
RFP
RFST
TDATA
TFP
LOSW
ICLK
RDATA
RFP
RFST
To T1 I/F
(T1-C)
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
Rate
Synth
Local Xtal
Osc
RFCLK
f
R (C)
RFCLK
CK6M
CK6M
f
R (R)
Frequency Relationships
1. fTCLK (DS1-C) = (DS1-R); tolerance = ±32 ppm, even with loss of signal on DS1-R
2. fTCLK (DS1-R) = (DS1-C); tolerance = ±32 ppm, even wit loss of signal on DS1-C
3. fICLK (C) = fR(C)/16; tolerance = ±32 ppm if sourced by local crystal oscillator (stratum 4)
= ±5 ppm if sourced by office clock (stratum 3)
4. fICLK (R) = fICLK (C) if loop is activated with receive frame sync acquired
= fR(R)/16 if receive sync is lost; tolerance = ±32 ppm. (fR(R) = 12.544 MHz)
= fR(R)/8 if fR(R) = 6.272 MHZ
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 23
Data Read: The Data Read pin (READ) requires an active Low pulse to enable a read transfer on
the data bus. When READ is pulled Low, the Data Pump data bus lines go from tristate to active
and output the data from the register addressed by ADDR0-ADDR3. To avoid reading data during
register updates, reads should be synchronized to the falling edge of FS. Alternatively, each read
should be repeated until the same data is read twice within one baud time.
Data Write: The Data Write pin (WRITE) requires an active Low pulse to enable a write transfer
on the data bus. Data transfer is triggered by the rising edge of the WRITE pulse. To ensure data is
written to the register addressed by ADDR0-ADDR3, valid data must be present on the HDX data
bus lines before WRITE goes High.
Interrupt: The Interrupt pin (INT) is an open drain output requiring an external pull-up resistor.
The INT output is pulled active Low when an internal interrupt condition occurs. INT is latched
and held until Main Status Register RD0 is read. An internal interruption results from a Low-to-
High transition in any of four status indicators: ACTIVE, LOSW, LOSWT or TEXP. Any transition
on LOS will also generate an interrupt. If an interrupt mask bit in register WR2 is set, any transition
of the corresponding status bit will not trigger the INT output.
2.7.2 Register Access
2.7.2.1 Write
To write to an HDX register, proceed as follows:
1. Drive CHIPSEL Low.
2. Drive an address (0000, 0010, or 0011) onto ADDR0-ADDR3.
3. Observe address setup time.
4. Set 8-bit input data word on D0-D7.
5. Pull WRITE Low, observing minimum pulse width.
6. Pull WRITE High, observing hold time for data and address lines.
2.7.2.2 Read
Procedures for reading the HDX registers vary according to which register is being read. Accessing
registers RD0, RD1, RD2, RD5 and RD6 is relatively simple. Reading registers RD3 and RD4 is
more complex. Unless parallel port reads are synchronized with the falling edge of FS, all read
operations should be repeated until the same data is read twice within one baud time.
To read register RD0, RD1, RD2, RD5 or RD6 proceed as follows:
1. Drive CHIPSEL Low.
2. Pull READ Low, observing minimum pulse width.
3. Pull READ High to complete the read cycle.
Registers RD3 and RD4 hold the coefficient values from the DFE, EC, FFE and AGC as shown in
Table 9. Register RD3 holds the lower byte value and register RD4 holds the upper byte value. To
reconstruct the complete 16-bit word, concatenate the least significant and most significant bytes.
To read registers RD3 and RD4 proceed as follows:
1. Select the desired coefficient by writing the appropriate code from Table 9 to register WR3.
2. Enable the Coefficient Read Register by writing a 1 to bit b0 (CRD1) in register WR2.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
24 Datasheet
3. Perform standard register read procedure listed in steps 1 through 6 above to read the lower
byte from RD3 and the upper byte from RD4.
4. Concatenate the RD3 and RD4 to obtain the complete 16-bit word.
2.7.2.3 Registers
Three write registers and seven read registers are available to the user. Table 6 lists these registers
and the following paragraphs describe them in more detail.
Some of the registers contain reserved bits. Software must deal correctly with reserved fields. For
reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits
being any particular value. In some cases, software must program reserved bit positions to a
particular value. This value is defined in the individual bit descriptions.
After asserting the RESET1 or RESET2 signal, the Data Pump initializes its registers to the default
value.
2.7.2.4 WR0—Main Control Register
Address: A3-0 = 0000
Default: 00h
Attributes: Write Only
Control Register bits serve the same purpose in Software Mode as the like-named individual pins
in Hardware Mode. Table 7 lists bit assignments for the WR0 register.
Table 6. Register Summary
ADDR Write Registers Read Registers
A3-A0 WR# Name Table RD# Name Table
0000 WR0 Main Control 7RD0 Main Status 10
0001 reserved n/a RD1 Receiver Gain Word 11
0010 WR2 Interrupt Mask 8RD2 Noise Margin 12
0011 WR3 Read Coefficient Select 9RD3 Coefficient Read Register (lower byte) 13
0100 reserved RD4 Coefficient Read Register (upper byte) 13
0101 reserved RD5 Activation Status 14
0110 reserved RD6 Receiver AGC and FFE Step Gain 15
0111-1001 reserved reserved
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 25
2.7.2.5 WR2—Interrupt Mask Register
Address: A3-0 = 0010
Default: 00h
Attributes: Write Only
Table 8 shows the various interrupt masks provided in register WR2.
Table 7. Main Control Register WR0
Bit Description
b7
Transmit Test Pattern Enable (TXTST). Set TXTST to 1 to enable isolated transmit pulse generation. The time
between pulses is 6 ms. TDATA controls the sign and TFP controls the magnitude of the transmitted symbols according
to the 2B1Q encoding rules. In the HTU-R configuration when the TXTST mode is selected, the Data Pump may begin
activation.
b6 Back-End Loop Back (BELB). In the Active State, set BELB to 1 to enable an internal, transparent loopback of the
HDX RDATA to TDATA and RFP to TFP.
b5 Front End Loop Back (FELB). In the HTU-C mode with the Data Pump in the Inactive State, set FELB to 1 to enable
an ACC front-end loopback. The Data Pump will begin activation and transmission on the line, but will ignore any signal
from the HTU-R instead synchronizing to its own transmit signal.
b4
Repeater Mode (RPTR). The RPTR bit is set to 1 and the HTU-C pin is pulled High to program the Data Pump for
operation on the side of the HDSL repeater driving the remote HTU-R. RPTR is set to 0 and the HTU-C pin is tied Low
to program the Data Pump for operation on the side of the repeater driven by the central office
HTU-C.
b3
Loop Control (LOOPID). For 2-pair ANSI HDSL applications, LOOPID defines the frame sync word format to encode
the loop number in HTU-C mode. Set LOOPID to 0 for Loop1 or to 1 for Loop2. The Data Pump transmits a 7-quat,
time-reversed, double-Barker code on Loop2.
For 3-pair ETSI HDSL applications, LOOPID should be set to 0 on all loops because the loop number is encoded in the
HDSL overhead using the Z bits.
b2 Insertion Loss Measurement Test (ILMT). Set ILMT to 1 to enable transmission of a scrambled all ones insertion loss
measurement test pattern. In the HTU-R configuration when the ILMT mode is selected, the Data Pump may begin
activation.
b1
Quiet Mode (QUIET). Set QUIET to 1 to force the Data Pump into the De-Activated State with the transmitter silent.
Setting QUIET to 0 will not cause the Data Pump to reactivate. In the HTU-R mode, the Data Pump will not respond to
an S0 signal from the HTU-C when QUIET is set to 1, but may activate after QUIET is set to 0 even if the HTU-C
transmission has already ceased.
b0
Activation Request (ACTREQ). In the HTU-C mode when the Data Pump is in the Inactive State and Quiet is set to 0,
setting the ACTREQ bit to 1 will initiate an activation sequence. Because ACTREQ is a level- rather than an edge-
triggered signal, it should be reset to 0 again within approximately 25 seconds to prevent the immediate start of another
activation cycle if the current activation attempt fails. If an activation attempt fails, the processor should allow the Data
Pump to remain in the Inactive State where the transmitter is silent for 32 seconds before generating another activation
request to allow the HTU-R to return to the Inactive State. It is possible to shorten this quiet period following a failed
activation by implementing additional algorithms described in the section entitled “Activation State Machines.”
Table 8. InInterrupt Mask Register WR2
Bit Description
b7:6 Reserved. Must be set to 0.
b5 LOSMSK. 1=Masked. 0=Not Masked. Interrupt mask for the LOS condition.
b4 LSWTMSK. 1=Masked. 0=Not Masked. Interrupt mask for the LOSWT condition.
b3 LSWMSK. 1=Masked. 0=Not Masked. Interrupt mask for the LOSW condition.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
26 Datasheet
2.7.2.6 WR3—Read Coefficient Select Register
Address: A3-0 = 0011
Default: 00h
Attributes: Write Only
Table 9 lists the bit maps used to select the coefficient read from the HDX.
2.7.2.7 RD0—Main Status Register
Address: A3-0 = 0000
Default: xxh (x=undefined)
Attributes: Read Only
Status Register bits serve the same purpose in Software Mode as the like-named individual pins in
Hardware mode. Table 10 lists the bit assignments in this register.
b2 ACTMSK. 1=Masked. 0=Not Masked. Interrupt mask for the TEXP condition and the ACTIVE
condition.
b1 Reserved. Must be set to 0.
b0 Enable coefficient read register (CRD1). 1=Enable. 0=Disable. Used in conjunction with WR3 for
reading coefficient values.
Table 8. InInterrupt Mask Register WR2 (Continued)
Bit Description
Table 9. Read Coefficient Select Register WR3
Hex Value Selected Registers Description
00-07 DFE1-DFE8 DFE coefficients
08-0F EC1-EC8 Echo Cancellation
10-15 FFE1-FFE6 FFE coefficients 1-6
16-19 reserved
1A AGC Tap AGC Tap
1B-FF reserved
Table 10. Main Status Register RD0
Bit Active Description
b7 Timer Expiry (TEXP). Set to 1 to indicate 30-second timer expiration in the Active State.
•Causes interrupt on changing from 0 to 1; masked by ACTMSK = 1
•Latched event; reset on read, with persistence while in the Active State
b6 TIP/RING polarity reversed (INVERT). 0 = polarity reversal. Valid only in Active State.
b5 Change Of Frame Alignment (COFA). Indicates that re-acquisition of frame sync is in a different
position with respect to the last frame position. Does not cause interrupt. Latched event; reset on
read.
b4 Loss Of Signal for HTU-R (LOS). 1 = loss of line signal energy on entering Inactive State.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 27
2.7.2.8 RD1—Receiver Gain Word Register
Address: A3-0 = 0001
Default: xxh (x=undefined)
Attributes: Read Only
The 8-bit word in this register is the eight most significant bits of the main FFE AGC tap, which,
along with the AGC and DAGC values (RD6), represent the receiver gain required to compensate
for line loss, and to normalize the receive 2B1Q pulses to a fixed threshold. Bit b7 (sign bit, always
0) is the MSB with bit b0 the LSB. The AGC tap value is determined as follows:
2.7.2.9 RD2—Noise Margin Register
Address: A3-0 = 0010
Default: xxh (x=undefined)
Attributes: Read Only
The noise margin of the received signal is an input to the HDSL framer’s Activation State
Machine. The noise margin must reach a threshold level before the HDSL framer can transition to
the fully Active State. The HDX provides a calculated, logarithmic noise margin value used by the
HDSL framer. This eight-bit word, stored in register RD2, is available every baud, although
updated only every 64 baud. Table 12 shows the noise margin coding. To calculate the SNR, use
this equation:
Loss of Signal Timer Expiration for HTU-C (LOST). 1 = loss of signal for 1 second on entering
Inactive State.
•Causes interrupt on transitions from 0 to 1 or 1 to 0 that are masked by LOSMSK = 1
•LOS/LOST is not a latched event
b3 Loop Number Control (LOOPID). 0 = loop 1; 1 = loop 2. Valid only in Active States, 0 in all others.
Note: This bit is used only for ANSI systems. The ETSI recommendation defines overhead bits for
loop identification.
b2 Loss of Sync Word Timer Expiry (LOSWT). Indicates two seconds of LOSW.
•Causes interrupt on changing from 0 to 1; masked when LSWTMSK = 1
•Latched event; reset on read; with persistence while in the Deactivated State
b1 Loss of Sync Word (LOSW).
•Causes interrupt on changing from 0 to 1; masked by LSWMSK = 1
•Latched event; reset on read; with persistence while in the Pending Deactivation State
b0 Active State (ACTIVE). 1 = Completion of layer 1 activation.
•Causes interrupt on changing from 0 to 1; masked by ACTMSK = 1
•Latched event; reset on read with persistence if still in the Active State
Table 10. Main Status Register RD0 (Continued)
Bit Active Description
Table 11. Receiver Gain Word Register
Bit Description
b7-b0 FFE AGC Tap Value (eight most significant bits).
AGC Tap =
Σ
b
i
*2
i
-6
i
= 0
6
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
28 Datasheet
SNR =Noise Margin + 21.5 dB
Error propagation in the DFE and de-scrambler may introduce some fractional errors in this
formula, however, the relationship between the SNR and the noise margin remains valid as long as
the noise follows a Gaussian distribution.
Since the average period of the calculation is very short (64 baud = 163 µs), the recommended
procedure for evaluating transmission quality is to average at least 1000 samples over a 163 ms
period.
Table 12. Noise Margin Register RD2
(Noise Margin Coding)
MSB LSB Noise
Margin1
b7 b6 b5 b4 b3 b2 b1 b0
00110101 +26.5
00101111 +23.5
00101011 +21.5
00101001 +20.5
00100111 +19.5
00100101 +18.5
00100100 +18.0
00100010 +17.0
00100000 +16.0
00011110 +15.0
00011100 +14.0
00011010 +13.0
00011000 +12.0
00010110 +11.0
00010100 +10.0
00010010 +9.0
00010000 +8.0
00001110 +7.0
00001100 +6.0
00001010 +5.0
00001000 +4.0
00000110 +3.0
00000100 +2.0
00000010 +1.0
00000000 0.0
11111110 -1.0
11111100 -2.0
1. Accuracy of noise margin is ±1 dB.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 29
2.7.2.10 RD3 (LSB), RD4 (MSB)—Coefficient Read Register
Address: RD3 (A3-0 = 0011)
RD4 (A3-0 = 0100)
Default: xxh (x=undefined)
Attributes: Read Only
Coefficient Read Word (read from the HDX) comes from the location configured in the Read
Coefficient Select Register (WR3, Address A3-0 = 0011). The HDX updates this word on the
rising edge of the receive clock, FS. Read register RD3 is the lower byte, and RD4 is the upper
byte.
2.7.2.11 RD5—Activation Status Register
Address: A3-0 = 0101
Default: xxh (x=undefined)
Attributes: Read Only
The ACT bits indicate the current state of the HDX transceiver during the Activating State as listed
in Table 14. For any state other than the Activating State, the ACT bits will be “0000”.
11111010 -3.0
11111000 -4.0
11110110 -5.0
11110100 -6.0
Table 12. Noise Margin Register RD2
(Noise Margin Coding) (Continued)
MSB LSB Noise
Margin1
b7 b6 b5 b4 b3 b2 b1 b0
1. Accuracy of noise margin is ±1 dB.
Table 13. Coefficient Read Register
Bit Description
b7-b0 Coefficient Word Value. RD3 contains the lower byte; RD4 the upper byte.
Table 14. Activation Status Register RD5
ACT Bits 3-0 State in
HTU-C Mode State in
HTU-R Mode
0000 Inactive Inactive
0001 Pre-AGC Wait
0010 Pre-EC AAGC
0011 SIGDET EC
0100 AAGC PLL1
0101 EC PLL2
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
30 Datasheet
2.7.2.12 RD6—Receive Step Gain Register
Address: A3-0 = 0110
Default: xxh (x=undefined)
Attributes: Read Only
This 8-bit register represents AGC and FFE gain coefficients (GAGC and GFFE, respectively). Bit
assignments are listed in Table 15. The approximate line loss (LL) can be determined using these
values in the following equation:
LL = 20log10 (GFFE * AGC tap) + GAGC + 28 dB
GFFE corresponds to DAGC in the HDX and GAGC is from the ACC. Bits ST0-ST2 indicate the
Data Pump activation states as shown in Figure 8, Figure 10 and Table 16.
0110 PLL 4LVLDET
0111 4LVLDET FRMDET
1000 FRMDET –
Table 14. Activation Status Register RD5
ACT Bits 3-0 State in
HTU-C Mode State in
HTU-R Mode
Table 15. Receiver AGC and FFE Step Gain Register RD6
Bit Description
b7 ST2. Data Pump Activation State–bit 2.
b6 ST1. Data Pump Activation State–bit 1.
b5-b4
GFFE1, GFFE0. Digital Gain Word–bit 1 and Digital Gain Word–bit 0.
Bits <5:4>GFFE Value
00 = 20 = 1
01 = 21 = 2
10 = 22 = 4
11 = 23 = 8
b3 ST0. Data Pump Activation State–bit 0
b2-b0
GAGC2-GAGC0. Analog Gain Word–bit 2,1 and 0.
Bits <2:0>GAGC Value (dB)
000 = -12
001 = -10
010 = -8
011 = -6
100 = -4
101 = -2
110 = 0
111 = +2
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 31
2.8 Activation State Machines
The Data Pump Activation/Start-Up circuitry is compatible with ANSI T1E1.4/94-006. Full HTU-
C activation is partitioned between the Data Pump and the framer. Figure 8 represents the HTU-C
Data Pump Activation State Machine, and Figure 9 shows the HTU-C framer activation state
machine. Figure 10 and 11 present the corresponding HTU-R state machines. Table 16 lays out the
correspondence between the Data Pump and Framer state machines. In Software Mode, the STn
bits in Read Register 6 (ADDR 0110) show the current status of the state machine.
2.8.1 HTU-C Data Pump Activation
When the HTU-C Data Pump is powered up and reset is applied, the chip is in the Inactive State as
shown at the top of Figure 8. Starting at the Inactive State, the device progresses in a clockwise
direction through the Activating, Active-1, Active-2, Pending De-Activation and De-Activated
States.
In the hardware mode when the Data Pump is in the Inactive State and the QUIET pin is Low, a
Low-to-High transition on the ACTREQ pin initiates activation of the link. In the software mode
when the Data Pump is in the Inactive State and the QUIET bit is set to 0, setting the ACTREQ bit
to 1 initiates activation of the link. Because the ACTREQ control bit is level sensing, it should be
set to 1 and then reset to 0 again within 25 seconds to generate a single activation request.
During the Activating State, the echo canceller, equalizer and timing recovery circuits are all
adapting during the simultaneous transmission and reception of the framed, scrambled-ones data
transmitted as a two-level code (S0) or as the four-level code (S1). If the receive frame sync word
is not detected in two consecutive frames within 30 seconds, the timer expires and the device
moves to the De-Activated State and ceases transmission. It will then immediately transition to the
Inactive State (setting LOST regardless of whether HTU-R transmission has ceased). Another
activation request should not be generated for 32 seconds allowing the HTU-R to time-out, detect
LOS and move from the De-Activated to the Inactive State. In microprocessor-based systems, this
time may be shortened by implementing a processor routine to reset the HTU-R Data Pumps which
are in the Activating State when no HTU-C signal is present.
Successful detection of the sync word drives the State machine to the Active-1 State. This is
indicated by a 0-to-1 transition of the ACTIVE bit (Software Mode). If the HTU-C Data Pump
remains locked to the sync word until the Activation Timer expires, the device transitions to the
Active-2 (fully active) State. If sync is lost, as indicated by a 0-to-1 transition on LOSW, the HTU-
C Data Pump transitions to the Pending De-Activation State.
In Pending De-Activation, the HTU-C Data Pump progresses to the De-Activated and Inactive
States with the expiration of the respective timers. If the sync word is detected before the LOSW
timer expires, the HTU-C Data Pump returns to either Active 1 or Active-2. The HTU-C Data
Pump returns to whichever state it occupied before transitioning to Pending De-Activation.
The HTU-C Data Pump will exit the Active-2 State in one of two ways. A Low-to-High transition
on the QUIET pin (Hardware Mode) or the QUIET bit (Software Mode), forces the HTU-C Data
Pump directly to the De-Activated State. The only other means of exiting the Active State is
through a loss of receive sync word (LOSW). LOSW is set when six consecutive frames occur
without a sync word match. The LOSW event puts the HTU-C Data Pump into the Pending De-
Activation State.
The HTU-C Data Pump remains in the Pending De-Activation State for a maximum of two
seconds. If a sync word is detected within two seconds after the LOSW event, the HTU-C Data
Pump reenters the Active State. If the LOSW condition exceeds two seconds, an LOSWT event
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
32 Datasheet
occurs which sends the chip to the De-Activated State. When the De-Activated State is reached
from Pending De-Activation, the HTU-C Data Pump returns to the Inactive State and declares
LOST when it detects no signal from the HTU-R for one second. The Data Pump should remain in
the Inactive State for 15 seconds before another activation attempt.
2.8.2 HTU-C Framer Activation
Figure 9 shows the activation state machine for the HTU-C HDSL framer. Transition to the Link
Active stage from the Idle stage (upper left) requires successful exchange of a pair of indicator bits,
indc and indr. “INDC” and “INDR” are internal status signals within the HDSL framer; “indc”
and “indr” are bits in the overhead channel. The HTU-C device transmits the indc bit, and the
HTU-R device transmits the indr bit. The overhead frame carries these indicator bits during
transmission of the S1 training pattern.
Figure 9 illustrates the two partially active states (Active-R and Active-T) which may serve as
transitions between the Idle and Link Active States. If the HTU-C device reaches the SNR
threshold, its framer sets the INDC bit and the device transitions to the Active-R State. If the HTU-
R device reaches the SNR threshold, it will transmit the indr bit to the HTU-C. The HTU-C will
then transition to the Active-T State. From either of the partially Active States, the devices
transition to the full Link Active State only with both Indication bits set.
Upon entering the Active States (Active-R, Active-T or Link Active), the chip will open up the full
duplex communication link with the HTU-R. Only the Active and Pending De-Activation States
allow full payload transmission. In all states except Active-1 and Active-2, the RDATA output is
clamped High.
Table 16. Data Pump/Framer Activation State Machine Correspondences
ST2 ST1 ST0 Data Pump State Framer State
0 0 0 Inactive Idle
001
Activating – 30 s
timer running Idle
010
Active – 30 s timer
running (Active-1)1
Idle, Active-R or
Active-T, or Link
Active
011
Active – 30 s timer
expired (Active-2)1Link Active
100
Pending De-
Activation1
Link Active or
Active-R or
Active-T
1 0 1 De-Activated Idle
110unused unused
111unused unused
1. The data pump samples the TDATA input for all transmit data
except the 14 sync bits at the start of each frame during
states 010, 011 and 100.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 33
Figure 8. HTU-C Data Pump Activation State Machine
Figure 9. HTU-C HDSL Framer Activation State Machine
De-Activated
Txmitter silent
(1, 0, 1) Inactive
Txmitter silent
(0, 0, 0)
LOST
0 1
DP Activating
Txmitting S0 or S1
(0, 0, 1)
Active 1
Txmitting S1 or
2B1Q Live data
(0, 1, 0)
LOSW 1 0
Active 2
Txmitting 2B1Q
Live data
(0, 1, 1) Actvation
Timer
Expiration
Pending
De-Activation
Txmitting 2B1Q
Data (1, 0, 0)
LOSW
1 0
LOSW
0 1
LOSW
1 0 LOSW
0 1
Activation
Timer
Expiration
LOSWT
0 1 ACTREQ
0 1
Power On
NOTE: (n, n, n) indicates the status of bits ST2, ST1 and ST0 respectively.
Idle
Active-R
Active-T
Link
Active
LOSWT = 1
INDC: 0 1
or
Timer Expiration
indr: 0 1
or
Timer Expiration
ACTIVE: 0 1
&
indr: 0 1
ACTIVE: 0 1
&
INDC: 0 1
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
34 Datasheet
2.8.3 HTU-R Data Pump Activation
Figure 10 and Figure 11 represent the HTU-R Data Pump Activation State Machine and the HTU-
R HDSL Framer State Machine. The activation state machines for HTU-R and HTU-C devices are
similar. Both Data Pump machines start at the Inactive State and progress clockwise through the
Activating, Active-1, Active-2, Pending De-Activation, and De-Activated States. One difference
between them is in the initial condition required to exit from the Inactive State. The HTU-C Data
Pump responds to the Activation Request (ACTREQ) signal. The HTU-R device responds only to
the presence of signal energy on the link. Thus, only an active HTU-C device can bring up the link.
Once the HTU-C begins transmitting, the HTU-R device will automatically activate and attempt
synchronization.
The other difference between the Data Pump state machines is the impetus for the change from the
De-Activated to the Inactive State. In the HTU-C Data Pump, expiration of a one-second loss of
signal timer (LOST) causes the transition. In the HTU-R the transition occurs immediately on Loss
of Signal (LOS).
2.8.4 HTU-R Framer Activation
The HDSL framer activation state machines for HTU-C and HTU-R are also similar. The
difference is in the indicator bits which cause the transition to either the Active-T or Active-R
State. On the HTU-R side, the INDR bit causes the transition to the Active-R State, and the indc bit
causes the transition to the Active-T State. From either partially active state, receipt of the
remaining indicator bit or timer expiry causes the transition to the full Link Active State.
2.8.5 HDSL Synchronization State Machine
Figure 12 shows the HDSL Synchronization State Machine incorporated in the HDX. It applies to
both HTU-C and HTU-R devices. Table 17 lists the correspondence between the Synchronization
states and Activation states. The Sync state machine is clocked by the receive signal framing.
Starting at the initial Out-of-Sync condition (State 0), the device progresses in a clockwise
direction through State 1 until Sync is declared in State 2. Two consecutive frame sync word
matches are required to achieve synchronization.
Once the In-Sync condition is declared, six consecutive frame sync mismatches will cause the
device to transition through States 3 through 7 and declare an Out-of-Sync condition in State 8.
From State 8, the device will return either to State 2 or to State 0. If the 2-second timer expires
without reestablishing frame sync (LOSWT = 1) or if the receive signal is lost entirely (LOS = 1),
the device returns directly to State 0.
If frame sync is reestablished, the device will return to the In-Sync condition (State 2) through
State 9 if two consecutive frames are received without any change of frame alignment (COFA = 0).
If a change of frame alignment does occur (COFA = 1), two consecutive matches are required to
transition through State 10 back to State 2.
Table 17. Activation – Synchronization
Activation State Synchronization States
Inactive State 0
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 35
Activating State 1
Active States 2, 3, 4, 5, 6, and 7
Pending De-Activation States 8, 9, and 10
Figure 10. HTU-R Data Pump Activation State Machine
Table 17. Activation – Synchronization (Continued)
Activation State Synchronization States
NOTE: (n, n, n) indicates the status of bits ST2, ST1 and ST0 respectively.
De-Activated
Txmitter silent
(1, 0, 1) Inactive
Txmitter silent
(0, 0, 0)
LOS
0 1
Power
On
DP Activating
Txmitting S0 or
S1
(0, 0, 1)
Active 1
Txmitting S1 or
2B1Q Live data
(0, 1, 0)
Active 2
Txmitting 2B1Q
Live data
(0, 1, 1) Activation
Timer
Expiration
PendIng
De-Activation
Txmitting 2B1Q
Data (1, 0, 0)
LOSW
1 0
LOSW
0 1
LOSW
1 0 LOSW
0 1
Activation Timer
Expiration
LOSWT
0 1
1-sec
Timer
LOSW 1 0
LOS
1 0
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
36 Datasheet
Figure 11. HTU-R HDSL Framer Activation State Machine
Idle
Active-R
Active-T
Link
Active
LOSWT = 1
INDR: 0 1
or
Timer Expiration
ACTIVE: 0 1
&
indc: 0 1
ACTIVE: 0 1
&
INDR: 0 1
indc: 0 1
or
Timer Expiration
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 37
Figure 12. HDSL Synchronization State Machine
NOTES:
1. “Sync” = Frame Sync Word Match. “No Sync” = Frame Sync Word Mismatch.
2. A 0-to-1 transition on QUIET will set the Sync State Machine from any State to State 0.
3. Expiration of the Activation Timer will set the Sync State Machine from State 1 to State 0.
Sync
No Sync
Initial
"Out-of-Sync"
State 0
ACTIVE = 0
LOSW = 0
LOS = 1
1
No Sync
Out of Sync
State 8
ACTIVE = 0
LOSW = 1
LOS = 0
No Sync
9
Sync with No
Change Of
Frame
Alignment
No Sync
No Sync
7 6
No Sync
5
No Sync
4
No Sync
3
No Sync
In Sync
State 2
ACTIVE =1
LOSW = 0
LOS = 0
Sync No Sync
LOS = 1
or
LOSWT = 1
Sync
Sync
Sync
Sync with Change
Of Frame
Alignment
Sync
COFA = 1
Sync
(COFA = 0)
No Sync
10 COFA = 1
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
38 Datasheet
3.0 Application Information
3.1 HDSL Framer State Machine
Design
There are two issues that impact implementation of the HDSL Framer Activation State machines
for both LTU and NTU devices. These issues relate to the data transparency characteristics of the
Data Pump as follows:
1. Once the ACTIVE 0-to-1 transition occurs, the Data Pump becomes transparent. Therefore,
the HDSL framer must put appropriate data in TDATA. Table 5 summarizes this requirement.
2. The link indicator bits (indc and indr) must stabilize before the device makes the transition
from the Idle to the Active-T State. Thus, the HDSL framer design may detect 6 consecutive
matches for the indication bit transition. This is particularly important for non-CSA loops
where a lower SNR may be experienced.
3.2 PCB Layout
The following are general considerations for PCB layout using the HDSL Data Pump chip set:
•Refer to Figure 14and Figure 15, and Table 18. Keep all shaded components close to the pins
they connect to
•Use a four-layer or more PCB layout, with embedded power and ground planes
•Break up the power and ground planes into the following regions. Tie these regions together at
the common point where power connects to the circuit:
•Digital Region
•Analog Region
•VCO subregion
•ACC, Line I/F, and IBIAS subregion
•Use larger feed-throughs (“vias”) and tracks for connecting the power and ground planes to the
power and ground pins of the ICs than for signal connections
•Place the decoupling capacitors right at the feed-through power/ground plane ties or on the
tracks to the IC power/ground pins as close to the pins as possible
•On the User Interface Connector, route digital signals to avoid proximity to the TIP, RING,
and CT lines
•Provide at least 100 µF or more of bulk power supply decoupling at the point where power is
connected to the Data Pump circuit
3.2.1 Digital Section
•Keep all digital traces separated from the analog region of the Data Pump layout
•Provide high frequency decoupling capacitors (0.01 µF ceramic or monolithic) around the
HDX as shown in Figures Figure 14 and Figure 15
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 39
•It is possible to replace the NAND gate (shown in Figure 14) with an AND gate
3.2.2 Analog Section
The analog section of the PCB consists of the following subsections:
1. ACC and power supply decoupling capacitors.
2. Bias Current Generator.
3. Voltage Controlled Crystal Oscillator.
4. Line Interface Circuit:
•Route digital signals AD0, AD1, FS, DTR, TSGN, TMAG, TCK3M, and AGCKIK on the
solder side of the PCB, and route all analog signals on the component side as much as possible
•Route the following signal pairs as adjacent traces, but keep the pairs separated from each
other as much as possible:
—TTIP/TRING
—BTIP/BRING
—RTIP/RRING
•Do not run the analog ground plane under the transformer line side to maximize high voltage
isolation
3.2.3 User Interface
The REFCLK and CK6M signals are sensitive to capacitive loading and rise time. Keep the rise
time (from 10%-90%) for these signals less than 5 ns.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
40 Datasheet
Figure 13. PCB Layout Guidelines
NOTE
: The VCC and GND planes for Digital and Analog sides should be
connected at a single point.
R5
Y1
123
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
262728
ACC
SK70704
C7
R1
C2
FS
DTR
CK25M
AGCKIK
AD1
AD0
TCK3M
GND3
TSGN
TMAG
6144
18 19 20 21 22 23 24 25 26 27
HDX
SK70706
17
7
40
39
30
28
RESET2
C1
R6
R9
R10
R7
R8
R12
R13
Digital GND and VCC
Planes
Analog GND and VCC
Planes
DVCC
TVCC
DGND
TGND
No GND and VCC
Planes this side
RVCC
RTIP
RRING
RGND
BTIP
BRING
n/c
D2
D1
R4
C4
C3
R3
R2
C5 C6
R11
TIP RING
VCC GND
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 41
Figure 14. Typical Support Circuitry for HTU-C Applications
Table 18. Components for Suggested Circuitry (Figure 14 and Figure 15)
Ref Description Ref Description Ref Description
C1, 9, 10 0.01 µF, ceramic, 10% R1 5.11 kΩ, 1% R12, 13 5.6 Ω, line feed fuse resistor
(ALFR-2-5.6-1 IRC)
C2 100 µF, electrolytic, 20% low
leakage ≤5 µA @ 25° C
R2 35.7 kΩ, 1%
R3, 4 20.0 kΩ, 1% D1, 2 Varicap diode (Motorola MV209)
C3, 4 1000 pF, ceramic, 20% R5, 6 301 Ω, 1% D3 Silicon rectifier diode (1N4001)
C5, 6 470 pF, COG or mica, 10% R7, 8118.2 Ω, 1% Y1 25.088 MHz crystal
(Hy-Q International 80546/1)
C7, 11-13 0.1 µF, ceramic, 10% R9, 10 604 Ω, 1%
C8 100 µF, electrolytic, 20%
R11 909 Ω, 1%
T1 1:1.8 (Midcom 671-7376 or
Pulse Engineering PE-68614)
R14,R1
510.0 kΩ, 1%
1. R7, R8 should be 20 Ω, when R12 and R13 (the 5.6 Ω fuse links) are not used.
U1
SK70706
HDX
VCC1
GND1
GND2
VCC2
GND3
REFCLK
CK6M
CK6MEN
HTU-C
RFP7
RFST10
RDATA8
ICLK17
TFP12
TDATA11
4 ADDR0
5
6
9
35 READ
34 WRITE
33 CHIPSEL
32 INT
D0..D736..43
TSGN 27
TMAG 26
TCK3M 25
1
RESET1 31
RESET2 18
ADDR1
ADDR2
ADDR3
2344 28
13 14 15 16
U2
SK70704
ACC
TSGN
TMAG
TCK3M
TVCC
TGND
DVCC
DGND
RVCC
2320 24 612
RGND
15
25
26
27
13
14
16
17
21
22
11
RTIP
RRING
BTIP
BRING
TTIP
TRING
IBIAS
VPLL
XI
XO
PGND
98 710
Y1
R11
C5
R7
R8
R10
C6
R5
R6
C3
C4
C1
R4
R3
R12
R13
R14
+5V
+5V
+
C8
J1
NC
CMOS CLOCK
OSCILLATOR
12.544 MHZ
(+/- 32 PPM)
PROCESSOR
I/F
HDSL
DATA
I/F
T1
1:1.8
2
46
10
RESET-
+5V
+5V
R2
C7
R9
D2D1
R1
C2
D3*
C10C9
C12
C13C11
FS
DTR
CK25M
21
20
19
FS
DTR
CK25M
3
4
5
AGCKIK AGCKIK
28
AD1
AD0
23
22
AD1
AD0
1
2
24
NOTES:
1. The HDX and ACC should have independent ground planes connected at a single point.
2. Diode D3 is optional.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
42 Datasheet
Table 19. Transformer Specifications
(Figure 14 and Figure 15, Reference T1)
Measure Value Tolerance
Turns Ratio (IC:Line) 1:1.8 ±1%
Secondary Inductance (Line
Side) 2.75 mH ±6%
Leakage Inductance ≤ 50 µH
Interwinding Capacitance ≤ 60 pF
THD ≤ -70 dB
Longitudinal Balance ≥ 50 dB 5-196 kHz
Return Loss ≥ 20 dB 40-200 kHz
Isolation 2000 VRMS
Primary DC Resistance ≤ 3.2 Ω
Secondary DC Resistance ≤ 6.0 Ω
Operating Temperature -40 to +85° C
Table 20. Crystal Specifications
(Figure 14 and Figure 15, Reference Y1)
Measure Value Tolerance
Calibration Frequency 25.088 MHz
@CL = 20 pF +0 to +40 ppm
Mode Fundamental,
Parallel
Resonance
Pullability
(CL = 24 pF Õ 16 pF) ≥ +160 ppm
Operating Temperature -40 to +85 ° C
Temperature Drift ≤ ±30 ppm
Aging Drift ≤ 5 ppm/year
Series Resistance ≤ 15 Ω
Drive Level 0.5 mW
Holder HC-49
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 43
Figure 15. Typical Support Circuitry for HTU-R Applications
U1
SK70706
HDX
VCC1
GND1
GND2
VCC2
GND3
REFCLK
CK6M
CK6MEN
HTU-C
RFP7
RFST10
RDATA8
ICLK17
TFP12
TDATA11
4 ADDR0
5
6
9
35 READ
34 WRITE
33 CHIPSEL
32 INT
D0..D736..43
1
RESET1 31
RESET2 18
ADDR1
ADDR2
ADDR3
2344 28
13 14 15 16
U2
SK70704
ACC
TVCC
TGND
DVCC
DGND
RVCC
2320 24 612
RGND
15
13
14
16
17
21
22
11
RTIP
RRING
BTIP
BRING
TTIP
TRING
IBIAS
VPLL
XI
XO
PGND
98 710
Y1
R11
C5
R7
R8
R10
C6
R5
R6
C3
C4
C1
R4
R3
R12
R13
+5V
+
C8
J1
CMOS CLOCK
OSCILLATOR
6.272 or 12.544 MHZ
(+/- 32 PPM)
T1
1:1.8
2
46
10
RESET-
+5V
+5V
R2
C7
R9
D2
R1
C2
D3
C10C9
C12
C13C11
PROCESSOR
I/F
HDSL
DATA
I/F
D1
FS
DTR
CK25M
21
20
19
FS
DTR
CK25M
3
4
5
AGCKIK AGCKIK
28
AD1
AD0
23
22
AD1
AD0
1
2
TSGN 27
TMAG 26
TCK3M 25
TSGN
TMAG
TCK3M
25
26
27
24
NOTES:
1. The HDX and ACC should have independent ground planes connected at a single point.
2. Diode D3 is optional.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
44 Datasheet
Figure 16. SK70706 HDX Control and Status Signals (Stand-alone Mode)
U1
SK70706
HDX
ACTREQ
5
QUIET
4
ACTVNG
9
TEXP
32
LOSWT
37
36 LOST/LOS
38
43
39
41
READ
33
WRITE
34 CHIPSEL
35
RCLKU
FELB
40
ILMT
TXTST
RPTR
BELB
42
n/c
NOTE: This figure illustrates the HDX control and status signals in stand-alone mode. All other HDX and ACC signals are
connected as shown in Figure 14 and Figure 15.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 45
4.0 Test Specifications
Note: The minimum and maximum values in Table 21 through Table 31 and Figure 15 through Figure 20
represent the performance specifications of the Data Pump and are guaranteed by test, except
where noted by design.
Table 21. ACC Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Supply voltage1 reference to ground2TVCC, RVCC, DVCC -0.3 +6.0 V
Input voltage2, 3, any input pin TVCC, RVCC, DVCC - 0.3V VCC + 0.3 V
Continuous output current, any output pin ––±25 mA
Storage temperature TSTOR -65 +150 ° C
Caution:Operations at the limits shown may result in permanent damage to the Analog Core Chip. Normal operation at these
limits is neither implied nor guaranteed.
1. No supply input may have a maximum potential of more than ±0.3 V from any other supply input.
2. TGND = 0V; RGND = 0V; DGND = 0V.
3. TVCC = RVCC = DVCC = VCC.
Table 22. ACC Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
DC supply TVCC, DVCC,
RVCC 4.75 5.0 5.25 V
Ambient operating temperature TA-40 +25 +85 ° C
Table 23. ACC DC Electrical Characteristics (Over Recommended Range)
Parameter Sym Min Typ1Max Unit Test Conditions
Supply current (full operation) ICC –92 120 mA 83 Ω resistor across TTIP and TRING
DVCC current –36mA
RVCC current –26 33 mA
TVCC current –63 79 mA Normal Mode 8+3, 8-3, 8+3, ...
–38 48 mA Off Mode
Input Low voltage VIL ––0.5 V
Input High voltage2VIH 4.5 ––V
Output Low voltage3VOL ––0.2 V IOL < 1.6 mA
Output High voltage VOH 4.5 ––VIOH < 40 µA
Input leakage current4IIL ––±50 µA0 < VIN < VCC
Input capacitance (individual pins) CIN –12 –pF
Load capacitance (REFCLK output) CLREF ––20 pF
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. IOL is sinking current.
3. IOH is sourcing current.
4. Applies to pins 3, 4, 25, 26 and 27.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
46 Datasheet
Table 24. ACC Transmitter Electrical Parameters (Over Recommended Range)
Parameters Sym Min Typ Max Unit Test Conditions
Isolated pulse height at TTIP,
TRING1
+2.455 +2.640 +2.825 Vp TDATA High, TFP Low (+3)
-2.825 -2.640 -2.455 Vp TDATA Low, TFP Low (-3)
+0.818 +0.880 +0.941 Vp TDATA High, TFP High (+1)
-0.941 -0.880 -0.818 Vp TDATA Low, TFP High (-1)
Setup time (TSGN, TMAG) tTSMSU 5––ns
Hold time (TSGN, TMAG) tTSMH 12 ––ns
1. Pulse amplitude measured across a 135 Ω resistor on the line side of the transformer using the application circuit shown in
Figure 14 and Table 18.
Figure 17. ACC Normalized Pulse Amplitude Transmit Template
-1.2 T -0.6 T
D = 0.93
B = 1.07
-0.4 T 0.4 T
C = 1.00
1.25 T
E = 0.03
G = -0.16
0.5 T
A = 0.01
F = -0.01
A = 0.01
F = -0.01
H = -0.05
14 T 50 T
Normalized
Levels
Quaternary Symbols (values in Volts)
+3 +1 -1 -3
A.01 0.0264 0.0088 -0.0088 -0.0264
B1.07 2.8248 0.9416 -0.9416 -2.8248
C1.00 2.6400 0.8800 -0.8800 -2.6400
D0.93 2.4552 0.8184 -0.8184 -2.4552
E0.03 0.0792 0.0264 -0.0264 -0.0792
F-0.01 -0.0264 -0.0088 0.0088 0.0264
G-0.16 -0.4224 -0.1408 0.1408 0.4224
H-0.05 -0.1320 -0.0440 0.0440 0.1320
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 47
Figure 18. ACC Transmitter Timing
Figure 19. ACC Transmit Power Spectral Density
Table 25. ACC Receiver Electrical Parameters (Over Recommended Range)
Parameter Sym Min Typ Max Unit Test Conditions
Propagation delay (AD0, AD1) tADD ––25 ns
Total harmonic distortion –-80 –dB V(RTIP, RRING) = 3 Vpp @ 50 kHz
RTIP, RRING, to BTIP, BRING gain ratio –1.0 1% V/V
TMAG
TSGN
TCK3M
A) Transmit Syntax
B) Transmit Timing
t
TSMSU
t
TSMH
TCK3M
TSGN
& TMAG
-20
-40
-60
-80
-100
-120
-140
-1601kHz 10kHz 100kHz 1MHz 10MHz
- 117 dBm/Hz
@ 1.96 MHz
Slope =
-80 dB/Decade
- 37 dBm/Hz
@ 196 kHz
dBm/Hz
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
48 Datasheet
Figure 20. ACC Receiver Syntax and Timing
Table 26. HDX Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Supply voltage1 reference to ground2VCC2, VCC1 -0.3 +6.0 V
Input voltage2, any input pin –- 0.3 VCC2 + 0.3 V
Continuous output current, any output pin ––±25 mA
Storage temperature TSTOR -65 +150 ° C
Caution:Operations at the limits shown may result in permanent damage to the HDSL Digital
Transceiver (HDX).
Normal operation at these limits is neither implied nor guaranteed.
1. The maximum potential between VCC2 and VCC1 must never exceed ±1.2 V.
2. GND3 = 0V; GND2 = 0V; GND1 = 0V.
Table 27. HDX Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
DC supply
VCC113.95 5.0 5.25 V
VCC2 4.75 5.0 5.25 V
VCC2-VCC1 -0.25 –+0.9 V
Ambient operating temperature TA-40 +85 ° C
1. To derive this supply, a 1N4001 (or equivalent) diode may be connected between VCC2 and VCC1 as shown in Figures
Figure 14 and Figure 15. The diode should be selected to meet VCC1 minimum specifications.
AGCKIK
AD1
AD0
FS
CK12.5M
(INTERNAL)
CK25M
AD0,
AD1
AGCKIK
CLK25M
PROP DELAY
B) Receiver Timing
A) Receiver Syntax
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 49
Table 28. HDX DC Electrical Characteristics (Over Recommended Range)
Parameter Sym Min Typ1Max Unit Test Conditions
Supply current (full operation) –100 175 mA
Input Low voltage VIL –– 0.5 V
Input High voltage VIH 4.0 ––V
Output Low voltage2VOL ––GND +0.3 V IOL < 1.6 mA
Output High voltage3VOH VCC2 - 0.5 ––VIOH < 40 µA
Input leakage current4IIL –– ±50 µA0 < VIN < VCC2
Tristate leakage current5ITOL –– ±30 µA 0 < V < VCC2
Input capacitance (individual pins) CIN –12 –pF
Load capacitance (REFCLK output) CLREF –– 15 pF
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. IOL is sinking current.
3. IOH is sourcing current.
4. Applies to pins 4, 5, 11, 12, 14, 16, 18, 19, 22, 23, 24, 29, 31, 33, 34 and 35. Applies to pins 5, 6, 9, 13, and 36-43, when
configured as inputs.
5. Applies to pins 7, 8, 10, 15, 17, 30, 32 and 36-43, when tristated.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
50 Datasheet
Figure 21. HDX/HDSL Data Interface Timing
1
f
ICLK
t
IPW
t
TH
t
TSU
t
TI
t
TD
t
TO
V
IL
V
IH
V
OH
V
OL
V
OH
V
OL
RATA,
RFP, RFST
TDATA,
TFP
ICLK
1
f
ICLK
t
IPW
t
TH
t
TSU
t
TD
t
TO
V
IL
V
IH
V
OH
V
OL
V
OH
V
OL
RATA,
RFP, RFST
TDATA
ICLK
t
TH
t
TI
V
IL
V
IH
TFP
t
TFPW
t
TFIR
B) Repeater Mode
A) Non-Repeater
REFCLK
TFP
t
TSUR
V
IH
V
IL
V
IH
V
IL
C) Repeater Mode
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 51
Table 29. HDX/HDSL Data Interface Timing Specifications (Figure 19)
Parameter Symbol Min Typ1Max Unit
ICLK frequency fICLK –784 –kHz
REFCLK frequency fREFCLK –12.544 –MHz
REFCLK frequency tolerance (HTU-C Mode) tolRCLK -32 0 +32 ppm
CK6M frequency tolerance (HTU-R Mode)2tolCK6M -32 0 +32 ppm
ICLK pulse width high tIPW –638 –ns
Transition time on any digital output3tTO –510ns
Transition time on any digital input tTI ––25 ns
TDATA, TFP setup time to ICLK rising edge tTSU 100 ––ns
TDATA, TFP hold time from ICLK rising edge tTH 100 ––ns
RDATA, RFP, RFST delay from ICLK falling edge tTD 0–150 ns
TFP pulse width4tTFPW 1248 1276 1304 ns
TFP falling edge to ICLK rising edge4tTFIR 480 –610 ns
TFP setup time to REFCLK rising edge4tTSUR 25 ––ns
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. CK6M must meet this tolerance about an absolute frequency of 6.272000 MHz or 12.544000 MHz in HTU-R mode.
3. Measured with 15 pF load.
4. These parameters apply only to an HTU-C mode Data Pump programmed for repeater applications as shown in Figure 29.
Table 30. HDX/Microprocessor Interface Timing Specifications (Figure 21 and Figure 22)
Parameter Symbol Min Typ Max Unit
RESET2 pulse width Low tRPWL 0.1 –1,000 µs
RESET2 to INT clear (10 kW resistor from INT to VCC2) tINTH ––300 ns
RESET2 to data tristate on D0-7 tDTHZ ––100 ns
CHIPSEL pulse width Low tCSPWL 200 ––ns
CHIPSEL Low to data active on D0-7 tCDLZ ––80 ns
CHIPSEL High to data tristate on D0-7 tCDHZ ––80 ns
READ pulse width Low tRSPWL 100 ––ns
READ Low to data active tRDLZ ––80 ns
READ High to data tristate tRDHZ ––80 ns
Address to valid data tPRD ––80 ns
Address setup to WRITE rising edge tASUW 20 ––ns
Address hold from WRITE rising edge tAHW 10 ––ns
WRITE pulse width Low tWPWL 100 ––ns
1. Timing for all outputs assumes a maximum load of 30 pF.
2. “Address” refers to input signals CHIPSEL, A0, A1, A2, and A3. “Data” refers to I/O signals D0, D1, D2, D3, D4, D5, D6, and
D7.
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
52 Datasheet
Data setup to WRITE rising edge tDSUW 20 ––ns
Data hold from WRITE rising edge tDHW 10 ––ns
READ High to INT clear when reading register RD0 tINTR ––400 ns
Table 31. General System and Hardware Mode Timing
Parameter Min Typ1Max Unit
Throughput delay TDATA to TTIP/TRING –10.2 12.5 µs
RTINP/RRING to RDATA –53.6 72 µs
Hardware Mode
“ACTREQ” input transitional
pulse width (High or Low) 5–– µs
“QUIET” transitional pulse width
(High-to-Low) 5–– µs
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 30. HDX/Microprocessor Interface Timing Specifications (Figure 21 and Figure 22)
(Continued)
Parameter Symbol Min Typ Max Unit
1. Timing for all outputs assumes a maximum load of 30 pF.
2. “Address” refers to input signals CHIPSEL, A0, A1, A2, and A3. “Data” refers to I/O signals D0, D1, D2, D3, D4, D5, D6, and
D7.
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 53
Figure 22. RESET and INTERRUPT Timing (µP Control Mode)
A) Reset Timing
B) Interrupt Timing
t
RPWL
t
INTH
t
DTHZ
INT
D0 7
(Output)
V
IH
V
IL
V
OH
V
OL
V
OL
V
OH
RESET2
READ
V
IH
V
IL
t
INTR
ADDR0 - 3
INT
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CHIPSEL
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set
54 Datasheet
Figure 23. Parallel Data Channel Timing
A) Chip Select Timing
B) Data Read Tim-
C) Data Write Tim-
V
IH
V
IL
CHIPSEL
t
CSPWL
V
OH
V
OL
t
CDLZ
t
CDHZ
(READ = 0)
D0 7
(Output)
V
IH
V
IL
CHIPSEL
V
OH
V
OL
t
RDLZ
t
PRD
READ
D0 7
(Output)
V
IH
V
IL
(WRITE = 1)
ADDR0 3
t
RDHZ
t
RSPWL
t
WPWL
V
IH
V
IL
CHIPSEL
V
IH
V
IL
t
DHW
WRITE
D0 7
(Input)
V
IH
V
IL
t
AHW
t
ASUW
(READ = 1)
ADDR0 3
t
TI
t
DSUW
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Datasheet 55
5.0 Mechanical Specifications
Figure 24. Data Pump Package Specifications
Analog Core Chip (ACC)
•28-pin PLCC
•P/N SK70704PE (-40° to + 85° C)
Dim
Inches Millimeters
Min Max Min Max
A 0.165 0.180 4.191 4.572
A1 0.090 0.120 2.286 3.048
A2 0.062 0.083 1.575 2.108
B .050 BSC1 (nominal) 1.27 BSC1 (nominal)
C 0.026 0.032 0.660 0.813
D 0.485 0.495 12.319 12.573
D1 0.450 0.456 11.430 11.582
F 0.013 0.021 0.330 0.533
1. BSC—Basic Spacing between Centers.
HDSL Digital Transceiver (HDX)
•44-pin PLCC
•P/N SK70706PE (-40° to + 85° C)
Dim
Inches Millimeters
Min Max Min Max
A 0.165 0.180 4.191 4.572
A1 0.090 0.120 2.286 3.048
A2 0.062 0.083 1.575 2.108
B .050 BSC1 (nominal) 1.27 BSC1 (nominal)
C 0.026 0.032 0.660 0.813
D 0.685 0.695 17.399 17.653
D1 0.650 0.656 16.510 16.662
F 0.013 0.021 0.330 0.533
1. BSC—Basic Spacing between Centers.
A
2
A
D
F
A
1
C
B
D
1
D
C
L
D
1
D
C
B
C
L
D
F
A
2
A
1
A
Plastic Leaded Chip Carrier
HDSL Digital Transceiver (HDX)
•44-pin PLCC
•P/N SK70706PE (-40° to + 85° C)
Dim
Inches Millimeters
Min Max Min Max
A 0.165 0.180 4.191 4.572
A1 0.090 0.120 2.286 3.048
A2 0.062 0.083 1.575 2.108
B .050 BSC1 (nominal) 1.27 BSC1 (nominal)
C 0.026 0.032 0.660 0.813
D 0.685 0.695 17.399 17.653
D1 0.650 0.656 16.510 16.662
F 0.013 0.021 0.330 0.533
1. BSC—Basic Spacing between Centers.
