M28W320HSU70ZB6E - Numonyx - Product.Network

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PRELIMINARY DATA

May 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M28W320CT

M28W320CB

32 Mbit (2Mb x16, Boot Block) Low Voltage Flash Memory

■SUPPLY VOLTAGE

–V

DD = 2.7V to 3.6V: for Program, Erase and

Read

–V

DDQ = 1.65V or 2.7V: Input/Output option

–V

PP = 12V: optional Supply Voltage for fast

Program

■ACCESS TIME

– 2.7V to 3.6V: 90ns

– 2.7V to 3.6V: 100ns

■PROGRAMMING TIME:

–10µs typical

– Double Word Programming Option

■PROGRAM/ERASE CONTROLLER (P/E.C.)

■COMMON FLASH INTERFACE

■MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

■BLOCK PROTECTION UNPROTECTION

– All Blocks protected at Power Up

– Any combination of blocks can be protected

– WP for block locking

■SECURITY

– 64-bit user Programmable OTP cells

– 64-bit unique device identifier

– One Parameter Block Permanently Lockable

■AUTOMATIC STAND-BY MODE

■PROGRAM and ERASE SUSPEND

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■20 YEARS of DATA RETENTION

– Defectivity below 1ppm/year

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M28W320CT: 88BAh

– Bottom Device Code, M28W320CB: 88BBh

Figure 1. Logic Diagram

AI03521

A0-A20

DQ0-DQ15

VDD

M28W320CT

M28W320CB

VSS

VDDQ VPP

TSOP48 (N)

12 x 20mm µBGA47 (GB)

8 x 6 solder balls

µBGA

M28W320CT, M28W320CB

2/42

Figure 2. µBGA Connections (Top view through package)

AI02686

87654321

A4A7VPP

A8A11A13

A0EDQ8DQ5DQ14A16

VSS

DQ0DQ9DQ3DQ6DQ15VDDQ

DQ1DQ10VDD

DQ7VSS

DQ2

A2A5A17WA10A14

A1A3A6A9A12A15

RP A18

DQ4

DQ13 G

DQ12

DQ11

A19

A20

Figure 3. TSOP Connections

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15

VDD

DQ4

DQ5

DQ7

VPP

AI03522

M28W320CT

M28W320CB

24 25

DQ8

A20

A19

A18

DQ1

DQ11

A12

A13

A16

A11

VDDQ

A15

A14 VSS

VSS

Table 1. Signal Names

A0-A20 Address Inputs

DQ0-DQ7 Data Input/Output, Command Inputs

DQ8-DQ15 Data Input/Output

E Chip Enable

G Output Enable

W Write Enable

RP Reset

WP Write Protect

VDD Supply Voltage

VDDQ Power Supply for

Input/Output Buffers

VPP Optional Supply Voltage for

Fast Program & Erase

VSS Ground

NC Not Connected Internally

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M28W320CT, M28W320CB

DESCRIPTION

The M28W320C is a 32 Mbit non-volatile Flash

memory that canbe erased electricallyattheblock

level and programmed in-system on a Word-by-

Word basis. The device is offered in the TSOP48

(10 x 20mm) and the µBGA47, 0.75mm ball pitch

packages. When shipped, all bits of the

M28W320C are in the 1state.

The array matrix organisation allows eachblock to

be erased and reprogrammed without affecting

other blocks. All blocks are protected against pro-

gramming and erase at Power UP. Blocks can be

unprotected to make changes in the application

and then reprotected. A parameter block ”Security

Block” can be permanently protected against pro-

gramming and erase in order to increase the data

security. Each block can be programmed and

erased over 100,000 cycles. VDDQ allows to drive

the I/O pin down to 1.65V. An optional 12V VPP

power supply is provided to speed up the program

phase at customer production line environment.

An internal Command Interface (C.I.) decodes the

instructions to access/modify the memory content.

The Program/Erase Controller (P/E.C.) automati-

cally executes the algorithms taking care of the

timings necessary for program and erase opera-

tions. Verification is performed too, unburdening

the microcontroller, while the Status Register

tracks the status of the operation.

The following instructions are executed by the

M28W320C: Read Array, Read Electronic Signa-

ture, ReadStatus Register, Clear Status Register,

Program, Double Word Program, Block Erase,

Program/Erase Suspend, Program/Erase Re-

sume, CFI Query, Block Protect, Block Lock, Block

Unprotect, Protection Program.

Organisation

The M28W320C is organised as 2 Mbit by 16 bits.

A0-A20 are the address lines; DQ0-DQ15 are the

Data Input/Output. Memory control is provided by

Chip Enable E, OutputEnable Gand WriteEnable

W inputs. The Program and Erase operations are

managed automatically by the P/E.C. Block pro-

tection against Program or Erase provides addi-

tional data security.

Memory Blocks

The device features an asymmetrical blocked ar-

chitecture. The M28W320C has an array of 71

blocks: 8 Parameter Blocks of 4 KWord and 63

Main Blocks of 32 KWord. M28W320CT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W320CB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Tables 3 and 4.

All Blocks are protected at power up. Instruction

are provided to protect, unprotect any block in the

application. A second register locks the protection

status while WP is low (see Block Protection De-

scription). Each block can be erased separately.

Erase can be suspended in order to perform either

read or program in any other block and then re-

sumed. Program can be suspendedto read data in

any other block and then resumed.

The architecture includes a 128 bits Protection

In the first one, starting from address 81h to 84h,

is written a unique device number, while the sec-

ond one, starting from 85h to 88h, is programma-

ble by the user. The user programmable segment

can be permanently protected programming the

bit.1 of the Protection Lock Register (see protec-

tion register and Security Block). The parameter

block (# 0)is a security block. It canbe permanent-

ly protected by the user programming the bit.2 of

the Protection Lock Register (see protection regis-

ter and Security Block).

Table 2. Absolute Maximum Ratings (1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listedin the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program andother relevant qual-

ity documents.

2. Depends on range.

Symbol Parameter Value Unit

TAAmbient Operating Temperature (2) –40 to 85 °C

TBIAS Temperature Under Bias –40 to 125 °C

TSTG Storage Temperature –55 to 155 °C

VIO Input or Output Voltage –0.6 to VDDQ+0.6 V

VDD,V

DDQ Supply Voltage –0.6 to 4.1 V

VPP Program Voltage –0.6 to 13 V

M28W320CT, M28W320CB

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Table 3. Top Boot Block Addresses,

M28W320CT

#Size

(KWord) Address Range

70 4 1FF000-1FFFFF

69 4 1FE000-1FEFFF

68 4 1FD000-1FDFFF

67 4 1FC000-1FCFFF

66 4 1FB000-1FBFFF

65 4 1FA000-1FAFFF

64 4 1F9000-1F9FFF

63 4 1F8000-1F8FFF

62 32 1F0000-1F7FFF

61 32 1E8000-1EFFFF

60 32 1E0000-1E7FFF

59 32 1D8000-1DFFFF

58 32 1D0000-1D7FFF

57 32 1C8000-1CFFFF

56 32 1C0000-1C7FFF

55 32 1B8000-1BFFFF

54 32 1B0000-1B7FFF

53 32 1A8000-1AFFFF

52 32 1A0000-1A7FFF

51 32 198000-19FFFF

50 32 190000-197FFF

49 32 188000-18FFFF

48 32 180000-187FFF

47 32 178000-17FFFF

46 32 170000-177FFF

45 32 168000-16FFFF

44 32 160000-167FFF

43 32 158000-15FFFF

42 32 150000-157FFF

41 32 148000-14FFFF

40 32 140000-147FFF

39 32 138000-13FFFF

38 32 130000-137FFF

37 32 128000-12FFFF

36 32 120000-127FFF

35 32 118000-11FFFF

34 32 110000-117FFF

33 32 108000-10FFFF

32 32 100000-107FFF

31 32 0F8000-0FFFFF

30 32 0F00000-F7FFF

29 32 0E8000-0EFFFF

28 32 0E0000-0E7FFF

27 32 0D8000-0DFFFF

26 32 0D0000-0D7FFF

25 32 0C8000-0CFFFF

24 32 0C0000-0C7FFF

23 32 0B8000-0BFFFF

22 32 0B0000-0B7FFF

21 32 0A8000-0AFFFF

20 32 0A0000-0A7FFF

19 32 098000-09FFFF

18 32 090000-097FFF

17 32 088000-08FFFF

16 32 080000-087FFF

15 32 078000-07FFFF

14 32 070000-077FFF

13 32 068000-06FFFF

12 32 060000-067FFF

11 32 058000-05FFFF

10 32 050000-057FFF

9 32 048000-04FFFF

8 32 040000-047FFF

7 32 038000-03FFFF

6 32 030000-037FFF

5 32 028000-02FFFF

4 32 020000-027FFF

3 32 018000-01FFFF

2 32 010000-017FFF

1 32 008000-00FFFF

0 32 000000-007FFF

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M28W320CT, M28W320CB

36 32 0E8000-0EFFFF

35 32 0E0000-0E7FFF

34 32 0D8000-0DFFFF

33 32 0D0000-0D7FFF

32 32 0C8000-0CFFFF

31 32 0C0000-0C7FFF

30 32 0B8000-0BFFFF

29 32 0B0000-0B7FFF

28 32 0A8000-0AFFFF

27 32 0A0000-0A7FFF

26 32 098000-09FFFF

25 32 090000-097FFF

24 32 088000-08FFFF

23 32 080000-087FFF

22 32 078000-07FFFF

21 32 070000-077FFF

20 32 068000-06FFFF

19 32 060000-067FFF

18 32 058000-05FFFF

17 32 050000-057FFF

16 32 048000-04FFFF

15 32 040000-047FFF

14 32 038000-03FFFF

13 32 030000-037FFF

12 32 028000-02FFFF

11 32 020000-027FFF

10 32 018000-01FFFF

9 32 010000-017FFF

8 32 008000-00FFFF

7 4 007000-007FFF

6 4 006000-006FFF

5 4 005000-005FFF

4 4 004000-004FFF

3 4 003000-003FFF

2 4 002000-002FFF

1 4 001000-001FFF

0 4 000000-000FFF

Table 4. Bottom Boot Block Addresses,

M28W320CB

#Size

(KWord) Address Range

70 32 1F8000-1FFFFF

69 32 1F0000-1F7FFF

68 32 1E8000-1EFFFF

67 32 1E0000-1E7FFF

66 32 1D8000-1DFFFF

65 32 1D0000-1D7FFF

64 32 1C8000-1CFFFF

63 32 1C0000-1C7FFF

62 32 1B8000-1BFFFF

61 32 1B0000-1B7FFF

60 32 1A8000-1AFFFF

59 32 1A0000-1A7FFF

58 32 198000-19FFFF

57 32 190000-197FFF

56 32 188000-18FFFF

55 32 180000-187FFF

54 32 178000-17FFFF

53 32 170000-177FFF

52 32 168000-16FFFF

51 32 160000-167FFF

50 32 158000-15FFFF

49 32 150000-157FFF

48 32 148000-14FFFF

47 32 140000-147FFF

46 32 138000-13FFFF

45 32 130000-137FFF

44 32 128000-12FFFF

43 32 120000-127FFF

42 32 118000-11FFFF

41 32 110000-117FFF

40 32 108000-10FFFF

39 32 100000-107FFF

38 32 0F8000-0FFFFF

37 32 0F0000-0F7FFF

M28W320CT, M28W320CB

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SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A20). The address signals

are inputs driven with CMOS voltage levels. They

are latched during a write operation.

Data Input/Output (DQ0-DQ15). The data in-

puts, a word to be programmed or a command to

the C.I., are latched on the Chip Enable E or Write

Enable W rising edge, whichever occurs first. The

data outputfrom the memory Array, the Electronic

Signature, the block protection status or Status

Enable G areactive. Theoutputis high impedance

when the chip is deselected, the outputs are dis-

abled or RP is tied to VIL. Commands are issued

on DQ0-DQ7.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. E at VIH deselects

the memory and reduces the power consumption

to thestand-by level. E can also be used tocontrol

writing to the command register and to the memo-

ry array, while W remains at VIL.

Output Enable (G). The Output Enable controls

the data Input/Output buffers.

Write Enable (W). This input controls writing to

the Command Register, Input Address and Data

latches.

Write Protect (WP). This input gives an addition-

al hardware protection level against program or

erase when pulled at VIL, asdescribed intheBlock

Protection description.

Reset Input (RP). The RP input provides hard-

ware reset of the memory. When RP is at VIL,the

memory is in reset mode: the outputs are put to

High-Z and the current consumption is minimised.

When RP is at VIH, the device is in normal opera-

tion. Exiting reset mode the device enters read ar-

ray mode.

VDD Supply Voltage (2.7V to 3.6V). VDD pro-

vides the power supply to the internal core of the

memory device. It is the main power supply for all

operations (Read, Program and Erase). It ranges

from 2.7V to 3.6V.

VDDQ Supply Voltage (1.65V to VDD). VDDQ

provides the power supply to the I/O pins and en-

ables all Outputs to be powered independently

from VDD.V

DDQ can be tied to VDD or it can use a

separate supply. It can be powered either from

1.65V to VDD.

VPP Program Supply Voltage (12V). VPP is both

a control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin.

If VPP is kept in a low voltage range (0V to 3.6V)

VPP is seen as a control input. In this case a volt-

age lowerthan VPPLK gives an absolute protection

against program or erase, while VPP >V

PP1 en-

ables these functions. VPP value is only sampled

at the beginning of a program or erase; a change

in its value after the operation has been started

does not have any effect andprogram or erase are

carried on regularly.

If VPP is used in the range 11.4V to 12.6V acts as

a power supply pin. In this condition VPP value

must be stable until P/E algorithm is completed

(see Table 24 and 25).

VSS Ground. VSS is the reference for all the volt-

age measurements.

7/42

M28W320CT, M28W320CB

DEVICE OPERATIONS

Four control pins rule the hardware access to the

Flash memory: E,G, W, RP. The following opera-

tions can be performed using the appropriate bus

cycles: Read, Write the Command of an Instruc-

tion, Output Disable, Stand-by, Reset (see Table

5).

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register and the CFI. Both Chip

Enable (E) and Output Enable (G) must be at VIL

in order to perform the read operation. The Chip

Enable input should be used to enable the device.

Output Enable should be used to gate data onto

the output independently of the device selection.

The data read depend on the previous command

written to the memory (see instructions RD, RSIG,

RSR, RCFI). Read Array is the default state of the

device when exiting reset or after power-up.

Write. Write operations are used to give Com-

mands to the memory or to latch Input Data to be

programmed. A write operation is initiated when

Chip Enable E and Write Enable W are at VIL with

Output Enable G at VIH. Commands, Input Data

and Addresses arelatched on the rising edge of W

or E, whichever occur first.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is at VIH.

Stand-by. Stand-by disables most of the internal

circuitry allowing a substantial reductionofthe cur-

rent consumption. The memory is in stand-by

when Chip Enable E is at VIH and the device is in

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independentlyfrom the OutputEnable

G or Write Enable W inputs. If E switches to VIH

during program or erase operation, the device en-

ters in stand-by when finished.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high impedance. Thememory is

in Reset mode when RP is atVIL. The power con-

sumption is reduced to the stand-by level, inde-

pendently from the Chip Enable E,Out-put Enable

G or Write Enable W inputs. If RP is pulled to VSS

during a Program orErase, this operation is abort-

ed and the memory content is no longer valid as it

has been compromised by the aborted operation.

Table 5. User Bus Operations (1)

Note: 1. X = VIL or VIH,V

PPH = 12V ±5%.

Table 6. Read Electronic Signature (RSIG Instruction)

Operation E G W RP WP VPP DQ0-DQ15

Read VIL VIL VIH VIH X Don’t Care Data Output

Write VIL VIH VIL VIH XVDD or VPPH Data Input

Output Disable VIL VIH VIH VIH X Don’t Care Hi-Z

Stand-by VIH XX

IH X Don’t Care Hi-Z

Reset X X X VIL X Don’t Care Hi-Z

Code Device E G W A0 A1 A2-A7 A8-A11 A12-A20 DQ0-DQ7 DQ8-DQ15

Manufact.

Code VIL VIL VIH VIL VIL 0 Don’t Care Don’t Care 20h 00h

Device

Code M28W320CT VIL VIL VIH VIH VIL 0 Don’t Care Don’t Care BAh 88h

M28W320CB VIL VIL VIH VIH VIL 0 Don’t Care Don’t Care BBh 88h

M28W320CT, M28W320CB

8/42

Table 7. Read Block Signature (RSIG Instruction)

Note: 1. A Locked Block can be protected ”DQ0 = 1” or unprotected ”DQ0 = 0”; see Block protection section.

Table 8. Read Protection Register and Protection Register Lock (RSIG Instruction)

Block Status E G W A0 A1 A2-A7 A8-A11 A12-A20 DQ0 DQ1 DQ2-DQ15

Protected Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address 1 0 00h

Unprotected Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address 0 0 00h

Locked Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address X(1) 100h

Word E G W A0-A7 A8-A20 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

Lock VIL VIL VIH 80h Don’t Care 0 OTP Prot.

data Security

prot. data 00h 00h

Unique Id 0 VIL VIL VIH 81h Don’t Care ID data ID data ID data ID data ID data

Unique Id 1 VIL VIL VIH 82h Don’t Care ID data ID data ID data ID data ID data

Unique Id 2 VIL VIL VIH 83h Don’t Care ID data ID data ID data ID data ID data

Unique Id 3 VIL VIL VIH 84h Don’t Care ID data ID data ID data ID data ID data

OTP 0 VIL VIL VIH 85h Don’t Care OTP data OTP data OTP data OTP data OTP data

OTP 1 VIL VIL VIH 86h Don’t Care OTP data OTP data OTP data OTP data OTP data

OTP 2 VIL VIL VIH 87h Don’t Care OTP data OTP data OTP data OTP data OTP data

OTP 3 VIL VIL VIH 88h Don’t Care OTP data OTP data OTP data OTP data OTP data

9/42

M28W320CT, M28W320CB

INSTRUCTIONS AND COMMANDS

Sixteen instructions are available (see Tables 9

and 10)to perform Read MemoryArray, ReadSta-

tus Register, Read Electronic Signature, CFI Que-

ry, Erase, Program, Double Word Program, Clear

Status Register, Program/Erase Suspend, Pro-

gram/Erase Resume, Block Protect, Block Unpro-

tect, Block Lock and Protection Register Program.

Status Register output may be read at any time,

during programming or erase, to monitor the

progress of the operation.

An internal Command Interface (C.I.) decodes the

instructions while an internal Program/Erase Con-

troller (P/E.C.) handles all timing and verifies the

correct execution of the Program and Erase in-

structions. P/E.C. provides a Status Register

whose bitsindicate operationand exit status ofthe

internal algorithms.

The Command Interface is reset to Read Array

when power is first applied, when exiting from Re-

set or whenever VDD is lower than VLKO. Com-

mand sequence must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read Array.

Read (RD)

The Read instruction consists of one write cycle

(refer to Device Operations section) giving the

command FFh. Next read operations will read the

addressed location and output the data. When a

device reset occurs, the memory is in Read Array

as default.

Read Status Register (RSR)

The Status Register indicates when a program or

erase operation is complete and the success or

failure of operation itself. Issue a Read Status

ister content. TheRead Status Register instruction

may be issued at any time, also when a Program/

Erase operation is ongoing. The following Read

operations output the content of the Status Regis-

ter. The Status Register is latched on the falling

edge of E or G signals, and can be read until E or

G returns to VIH. Either E or G must be toggled to

update the latched data. Additionally, any read at-

tempt duringprogramor eraseoperation will auto-

matically outputthe content of the Status Register.

Read Electronic Signature (RSIG)

The Read Electronic Signature instruction con-

sists ofonewrite cycle (refer to Device Operations

section) giving the command 90h. A subsequent

read will output the Manufacturer Code, the De-

vice Code,the Block protection Status, orthe Pro-

tection Register. See Tables 6, 7 and 8 for the

valid address. The Electronic Signature can be

read from the memory allowing programming

equipment or applications to automatically match

their interface to the characteristics of

M28W320C.

CFI Query (RCFI)

The Common Flash Interface Query mode is en-

tered bywriting 98h.Next readoperations will read

the CFI data. The CFI data structure contains also

a security area; in this section,a 64 bit unique se-

curity number is written, starting at this address

81h. This area can be accessed onlyin read mode

and there are no ways of changing the code after

it has been written by ST. Write a read instruction

to return to Read mode (refer to the Common

Flash Interface section).

Table 9. Commands

Hex Code Command

00h Invalid/Reserved

10h Alternative Program Set-up

20h Erase Set-up

30h Double Word Program Set-up

40h Program Set-up

50h Clear Status Register

70h Read Status Register

90h or 98h Read Electronic Signature, or

CFI Query

B0h Program/Erase Suspend

D0h Program/Erase Resume, Erase

Confirm or Unprotect Confirm

FFh Read Array

01h Protect Confirm

2Fh Lock Confirm

C0h Protection Program

60h Protection Set-up

M28W320CT, M28W320CB

10/42

Status Register bit b7 returns’0’ whilethe erasure

is in progress and ’1’ when it has completed. After

completion the Status Register bit b5 returns ’1’ if

there has been an Erase Failure. Status register

bit b1 returns ’1’ if the user is attempting to pro-

gram a protected block. Status Register bit b3 re-

turns a ’1’ if VPP is below VPPLK.

Erase aborts if RP turns to VIL. As data integrity

cannot be guaranteed when the erase operation is

aborted, the erase must be repeated. A Clear Sta-

tus Register instruction must beissued to reset b1,

b3, b4 and b5 of the Status Register. During the

execution of the erase by the P/E.C., the memory

accepts only the RSR (Read Status Register) and

PES (Program/Erase Suspend) instructions.

Table 10. Instructions

Note: 1. X = Don’t Care.

2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the memory array or special register. Any

number of read cycle can occur after one command cycle.

3. The signature address recognized are listed in the Tables 6, 7 and 8.

4. Address 1 and Address 2 must be consecutive address differing only for address bit A0.

5. A read cycle after a CLSR instruction will output the memory array.

Mne-

monic Instruction Cycles 1st Cycle 2nd Cycle 3nd Cycle

Operat. Addr. (1) Data Operat. Addr. Data Operat. Addr. Data

RD Read Memory

Array 1+ Write X FFh Read (2) Read

Address Data

RSR Read Status

RSIG Read

Electronic

Signature 1+ Write X 90h or

98h Read (2) Signature

Address (3) Data

RCFI Read CFI 1+ Write 55h 98h or

90h Read (2) CFI

Address Query

EE Erase 2 Write X 20h Write Block

Address D0h

PG Program 2 Write X 40h or

10h Write Address Data

Input

DPG (4) Double Word

Program 3 Write X 30h Write Address 1 Data

Input Write Address 2 Data

Input

CLRS (5) Clear Status

PES Program/

Erase

Suspend 1 Write X B0h

PER Program/

Erase

Resume 1 Write X D0h

BP Block Protect 2 Write X 60h Write Block

Address 01h

BU Block

Unprotect 2 Write X 60h Write Block

Address D0h

BL Block Lock 2 Write X 60h Write Block

Address 2Fh

PRP Protection

Program 2 Write X C0h Write Address Data

Input

Erase (EE)

Block erasure sets all the bits within the selected

block to ’1’. One block at a time can be erased. It

is not necessary to program the block with 00h as

the P/E.C. will do it automatically before erasing.

This instruction uses two write cycles. The first

command written is the Erase Set up command

20h. The second command is the Erase Confirm

command D0h. An address within the block to be

erased is given and latched into the memory dur-

ing the input of the second command. If the sec-

ond command given is not an erase confirm, the

status register bits b4 and b5 are set and the in-

struction aborts.

Read operations output the status register after

erasure has started.

11/42

M28W320CT, M28W320CB

Table 11. Protection States (1)

Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.

2. Current state and Next state gives the protection status of a block. The protection status is defined by thewrite protect pin and by

DQ1 (=1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = VIH

and A0 = VIL.

3. Next state is theprotection statusof a block after aProtect orUnprotect or Lock command hasbeen issued or after WP has changed

its logic value.

4. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Table 12. Status Register Bits

Note: Logic level ’1’is High, ’0’ is Low.

Current State (2) Next State After Event (3)

(WP, DQ1, DQ0) Program/Erase

Allowed Protect Unprotect Lock WP transition

100 yes 101 100 111 000

101 no 101 100 111 001

110 yes 111 110 111 011

111 no 111 110 111 011

000 yes 001 000 011 100

001 no 001 000 011 101

011 no 011 011 011 111 or 110 (4)

Mnemonic Bit Name Logic

Level Definition Note

P/ECS 7 P/E.C. Status

’1’ Ready Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits b4 or b5 for Program or Erase

Success.

’0’ Busy

ESS 6 Erase

Suspend

Status

’1’ Suspended On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’until an

Erase Resume instruction is given.

’0’ In progress or

Completed

ES 5 Erase Status ’1’ Erase Error ES bit is set to ’1’if P/E.C. has applied the

maximum number of erase pulses to the block

without achieving an erase verify.

’0’ Erase Success

PS 4 Program

Status ’1’ Program Error PS bit set to ’1’ if the P/E.C. has failed to program

a word.

’0’ Program Success

VPPS 3 VPP Status

’1’ VPP Invalid, Abort VPPS bit is set if the VPP voltage is below VPPLK

when aProgram or Erase instruction is executed.

VPP is sampled only at the beginning of the

erase/program operation.

’0’ VPP OK

PSS 2 Program

Suspend

Status

’1’ Suspended On a Program Suspend instruction P/ECS and

PSS bits are set to ’1’. PSS remains ’1’until a

Program Resume Instruction is given.

’0’ In Progress or

Completed

BPS 1 Block

Protection

Status

’1’ Program/Erase on

protected Block,

Abort BPS bit is set to ’1’ if a Program or Erase

operation has been attempted on a protected

block.

’0’ No operation to

protected blocks

0 Reserved

M28W320CT, M28W320CB

12/42

Program (PG)

The memory array can be programmed word-by-

word. This instruction uses two write cycles. The

first command written is the Program Set-up com-

mand 40h(or 10h).A second write operation latch-

es the Address and the Data to be written and

starts the P/E.C.

Read operations output the Status Register con-

tent afterthe programming has started. The Status

is inprogress and ’1’ when it has completed. After

completion the Status register bit b4 returns ’1’ if

there has been a Program Failure. Status register

bit b1 returns ’1’ if the user is attempting to pro-

gram a protected block. Status Register bit b3 re-

turns a ’1’ if VPP is below VPPLK. Programming

aborts if RP goes to VIL. As data integrity cannot

be guaranteed when the program operation is

aborted, the memory locationmust be erased and

reprogrammed. A Clear Status Register instruc-

tion must be issued to reset b4, b3 and b1 of the

Status Register.

During the execution of the programby the P/E.C.,

the memory accepts only the RSR (Read Status

structions.

Double Word Program (DPG)

This featureis offered toimprove the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

ed when VPP is not at VPPH. The operation can

also be executed if VPP is below VPPH but result

could be uncertain. This instruction uses three

write cycles. The first command written isthe Dou-

ble Word Program Set-Up command 30h. A sec-

ond write operation latches the Address and the

Data of the first word to be written, the third write

operation latches the Address and the Data of the

second word to be written and starts the P/E.C.

Read operations output the Status Register con-

tent afterthe programming has started. The Status

is inprogress and ’1’ when it has completed. After

completion the Status register bit b4 returns ’1’ if

there has been a Program Failure. Status register

bit b1 returns ’1’ if the user is attempting to pro-

gram a protected block. Status Register bit b3 re-

turns a ’1’ if VPP is below VPPLK. Programming

aborts if RP goes to VIL. As data integrity cannot

be guaranteed when the program operation is

aborted, the memory locationmust be erased and

reprogrammed. A Clear Status Register instruc-

tion must be issued to reset b4, b3 and b1 of the

Status Register.

During the execution ofthe programby the P/E.C.,

the memory accepts only the RSR (Read Status

structions.

Clear Status Register (CLRS)

The Clear Status Register uses a single write op-

eration which clears bits b1, b3, b4 and b5 to 0. Its

use is necessary before any new operation when

an error has been detected.

The Clear Status Register is executed writing the

command 50h.

Program/Erase Suspend (PES)

Program/Erase suspend is accepted only during

the Program Erase instruction execution. When a

Program/Erase Suspend command is written to

the C.I., the P/E.C. freezesthe Program/Erase op-

eration. Program/Erase Resume (PER) continues

the Program/Erase operation. Program/Erase

Suspend consists of writing the command B0h

without any specific address.

The Status Register bit b2 is set to ’1’ (within 5µs)

when the program has been suspended. b2 is set

to ’0’ in case the program is completed or in

progress. The Status Register bit b6 is set to ’1’

(within 30µs) when the erase has been suspend-

ed. b6 is set to ’0’ in case the erase is completed

or in progress. Thevalid commands while erase is

suspended are: Program/Erase Resume, Pro-

gram, Read Array, Read Status Register, Read

Identifier, CFI Query, Block Protect, Block Unpro-

tect, Block Lockand Protection Program. The user

can protect the Block being erased issuing the

Block Protect, Block Lock or Protection Program

commands. In this case the protection status bit

will change immediately, but when theerase is re-

sumed, the operation will complete The valid com-

mands whileprogram is suspended are: Program/

Erase Resume, Read Array, Read Status Regis-

ter, Read Identifier, CFI Query.

During program/erase suspend mode, the chip

can be placed in a pseudo-stand-by mode by tak-

ing E to VIH This reduces active current consump-

tion. Program/Erase is aborted if RP turns to VIL.

Program/Erase Resume (PER)

If a Program/Erase Suspend instruction was previ-

ously executed, the program/erase operation may

be resumed by issuing the command D0h. The

status register bit b2/b6 is cleared when program/

erase resumes. Read operations output the status

13/42

M28W320CT, M28W320CB

The suggested flow charts for programs that use

the programming, erasure and program/erase

suspend/resume features of the memories are

shown from Figures 11, 12, 13, 14 and 15.

Protection Register Program (PRP)

The Protection Register Program uses two write

cycles. The first command written is the protection

program command C0h. The second write opera-

tion latches the Address and the Data to be written

to the Protection Register (see Protection Register

and Security Block) and start the PE/C. Read op-

erations output the Status Register content after

the programming has started. The 64 bits user

programmable Segment (85h to 88h) are pro-

grammed 16 bits at a time, it can be protected by

the user programming bit 1 of the Protection Lock

protect the bit 2 of the Protection Lock Register.

Writing thebit 2 ofthe ProtectionLock Register will

result in a permanent protection of the Security

Block. Attemptingto program apreviously protect-

ed protection Register will result in a status regis-

ter error (bit 1and bit 4 of the status register will be

set to ’1’). The protectionof the Protection Register

and/or the Security Block is not reversible.

The Protection Register Program cannot be sus-

pended.

Block Protect (BP)

The BP instruction use two write cycles. The first

command written is the protection setup 60h. The

second command is block Protect command 01h.

The address within the block being protected must

be given in orderto write theprotection state. If the

second command is not recognized by the C.I the

bit 4 and bit 5 of the status register will be set toin-

dicate a wrong sequence of commands. To read

the status register write the RSR command.

Block Unprotect (BU)

The instruction usetwowrite cycles. The first com-

mand written is the protection setup 60h. The sec-

ond command is block Unprotect command d0h.

The address within the block being unprotected

must be given in order to write the unprotection

state. If the second command is notrecognized by

the C.I the bit 4 and bit 5 of the status register will

be set to indicate a wrong sequence of com-

mands. To read the status register write the RSR

command.

Block Lock (BL)

The instruction usetwowrite cycles. The first com-

mand written is the protection setup 60h. The sec-

ond command is block Lock command 2Fh. The

address within the block being Locked must be

given in orderto write the Lockingstate. If the sec-

ond command is not recognized by the C.Ithe bit 4

andbit 5of the status registerwill beset to indicate

a wrong sequence of commands. To read the sta-

tus register write the RSR command.

Table 13. Program, Erase Times and Program/Erase Endurance Cycles

(TA= 0 to 70°C or –40 to 85°C; VDD = 2.7V to 3.6V)

Note: TA=25°C.

Parameter Test Conditions M28W320C Unit

Min Typ (1) Max

Word Program VPP =V

DD 10 200 µs

Double Word Program VPP = 12V ±5% 10 200 µs

Main Block Program VPP = 12V ±5% 0.16 5 sec

VPP =V

DD 0.32 5 sec

Parameter Block Program VPP = 12V ±5% 0.02 4 sec

VPP =V

DD 0.04 4 sec

Main Block Erase VPP = 12V ±5% 1 10 sec

VPP =V

DD 110 sec

Parameter Block Erase VPP = 12V ±5% 0.8 10 sec

VPP =V

DD 0.8 10 sec

Program/Erase Cycles (per Block) 100,000 cycles

M28W320CT, M28W320CB

14/42

BLOCK PROTECTION

The M28W320C provide a flexible protection of all

the memory providing the protection unprotection

and locking ofany blocks. All blocks are protected

at power-up. Each block of the array has two lev-

els of protection against program or erase opera-

tion. The first level is set by the Block Protect

instruction; a protected block cannot be pro-

grammed or erased until a Block Unprotect in-

struction is given for that block. A second level of

protection isset by the Block Lock instruction, and

requires the use of the WP pin, according to the

following scheme:

– when WP isat VIH, theLock status isoverridden

and all blocks can be protected or unprotected;

– when WP is at VIL, Lock status is enabled; the

locked blocks are protected, regardless of their

previous protect state, and protection status

cannot be changed. Blocks that are not locked

can still change their protection status;

– the lock status is cleared for all blocks at power

up.

The protection and lock status can be monitored

for each blockusing theReadElectronic Signature

(RSIG) instruction. Protected blocks will output a

’1’ on DQ0 and locked blocks will output a ’1’ in

DQ1.

PROTECTION REGISTER

and SECURITY BLOCK

The M28W320C features a 128-bit protection reg-

ister and a security Block in order to increase the

protection of a system design. The Protection

segment (81h to 84h) is a unique device number,

while the second one (85h to 88h) can be pro-

grammed by the user. When shipped the user pro-

grammable segment is read at ’1’. It can be only

programmed at ’0’;

The user programmable segment can be protect-

ed writing the bit 1 of the Protection Lock register

(80h). The bit 1 protect also the bit 2 of the Protec-

tion Lock Register. The M28W320C feature a se-

curity Block. The security Block is located at

1FF000-1FFFFF (M28W320CT) or at 000000-

000FFF (M28W320CB) of the device. This block

can be permanently protected by the user pro-

gramming the bit2 of the Protection LockRegister.

The protection Register and the Protection Lock

subsequent read in the address starting from 80h

to 88h, the user will retrieve respectively the Pro-

tection Lock register, the unique device number

segment and the OTP user programmable register

segment (see Table 8).

Figure 4. Security Block Memory Map

AI03523

Parameter Block # 0

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

88h

85h

84h

81h

80h

15/42

M28W320CT, M28W320CB

POWER CONSUMPTION

The M28W320C puts itself in one of four different

modes depending on the status of the control sig-

nals: Active Power,Automatic Stand-by, Stand-by

and Reset define decreasing levels of current con-

sumption. These allow the memory power to be

minimised, in turn decreasing the overall system

power consumption. As different recovery time are

linked to the different modes, please refer to the

AC timing Table to design your system.

Active Power

When E is at VIL and RP is at VIH, the device is in

active mode. Refer to DC Characteristics to get

the values of the current supply consumption.

Automatic Stand-by

Automatic Stand-by provides a low power con-

sumption state during read mode. Following a

read operation, after a delay close to the memory

access time, the device enters Automatic Stand-

by: the Supply Current is reduced to ICC1 values.

The device keeps the last output data stable, till a

new location is accessed.

Stand-by or Reset

Refer to the Device Operations section.

Power Up

The Supply voltage VDD and the Program Supply

voltage VPP can be applied in any order. The

memory Command Interface is reset on power up

to Read Memory Array, but a negative transition of

Chip Enable E or a change of the addresses is re-

quired to ensure valid data outputs. Care must be

taken to avoid writes to the memory when VDD is

above VLKO. Writes can be inhibited by driving ei-

ther E or W to VIH. The memory is disabled if RP

is at VIL.

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling, each device in a system should

have the VDD and VPP rails decoupled with a

0.1µF capacitor close to the VDD and VPP pins.The

PCB trace widths should be sufficient to carry the

required VPP program and erase currents.

M28W320CT, M28W320CB

16/42

COMMON FLASH INTERFACE (CFI)

The Common Flash Interface (CFI) specification is

a JEDEC approved, standardised data structure

that can be read from the Flash memory device.

CFI allows a system software to query the flash

device to determine various electrical and timing

parameters, density information and functions

supported by the device. CFI allows the system to

easily interface to the Flash memory, to learn

about its features and parameters, enabling the

software to configure itself when necessary.

Tables 14,15, 16, 17, 18and19 show the address

used to retrieve each data.

The CFI data structure gives information on the

device, such as the sectorization, the command

set and some electrical specifications. Tables 14,

15, 16 and 17 showthe addresses used to retrieve

each data. The CFI data structure contains also a

security area; in this section, a 64 bit unique secu-

rity number is written, starting at address 81h. This

area canbe accessed only in read mode and there

are no ways of changing the code after it has been

written by ST. Write a read instruction to return to

Read mode. Refer to the CFI Query instruction to

understand how the M28W320C enters the CFI

Query mode.

Table 14. Query Structure Overview

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 15, 16, 17, 18 and 19. Query data are always presented on the lowest order data outputs.

Table 15. CFI Query Identification String

Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table Additional information specific to the Primary

Algorithm (optional)

A Alternate Algorithm-specific Extended Query table Additional information specific to the Alternate

Algorithm (optional)

Offset Data Description

00h 0020h Manufacturer Code

01h 88BAh - top

88BBh - bottom Device Code

02h-0Fh reserved Reserved

10h 0051h Query Unique ASCII String ”QRY”

11h 0052h Query Unique ASCII String ”QRY”

12h 0059h Query Unique ASCII String ”QRY”

13h 0003h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

14h 0000h

15h offset = P = 0035h Address for Primary Algorithm extended Query table

16h 0000h

17h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor

- specified algorithm supported (note: 0000h means none exists)

18h 0000h

19h value = A = 0000h Address for Alternate Algorithm extended Query table

note: 0000h means none exists

1Ah 0000h

17/42

M28W320CT, M28W320CB

Table 16. CFI Query System Interface Information

Offset Data Description

1Bh 0027h VDD Logic Supply Minimum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV

1Ch 0036h VDD Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV

1Dh 00B4h

VPP [Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Note: This value must be 0000h if no VPP pin is present

1Eh 00C6h

VPP [Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Note: This value must be 0000h if no VPP pin is present

1Fh 0004h Typical timeout per single byte/word program (multi-byte program count = 1), 2nµs

(if supported; 0000h = not supported)

20h 0000h Typical timeout for maximum-size multi-byte program or page write, 2nµs

(if supported; 0000h = not supported)

21h 000Ah Typical timeout per individual block erase, 2nms

(if supported; 0000h = not supported)

22h 0000h Typical timeout for full chip erase, 2nms

(if supported; 0000h = not supported)

23h 0004h Maximum timeout for byte/word program, 2ntimes typical (offset 1Fh)

(0000h = not supported)

24h 0000h Maximum timeout for multi-byte program or page write, 2ntimes typical (offset 20h)

(0000h = not supported)

25h 0003h Maximum timeout per individual block erase, 2ntimes typical (offset 21h)

(0000h = not supported)

26h 0000h Maximum timeout for chip erase, 2ntimes typical (offset 22h)

(0000h = not supported)

M28W320CT, M28W320CB

18/42

Table 17. Device Geometry Definition

Offset Word

Mode Data Description

27h 0016h Device Size = 2nin number of bytes

28h 0001h Flash Device Interface Code description: Asynchronous x16

29h 0000h

2Ah 0000h Maximum number of bytes in multi-byte program or page = 2n

2Bh 0000h

2Ch 0002h Number of Erase Block Regions within device

bit 7 to 0 = x = number of Erase Block Regions

Note:1. x = 0 means no erase blocking, i.e. the device erases at once in ”bulk.”

2. x specifies the number of regions within the device containing one or more con-

tiguous Erase Blocks of the same size. For example, a 128KB device (1Mb)

having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is consid-

ered to have 5 Erase Block Regions. Even though two regions both contain

16KB blocks, the fact that they are not contiguous means they are separate

Erase Block Regions.

3. By definition, symmetrically block devices have only one blocking region.

M28W320CT M28W320CT Erase Block Region Information

bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in

size. The value z = 0 is used for 128 byte block size.

e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K

bit 15 to 0 = y,where y+1 = Number of Erase Blocks of identical size within the Erase

Block Region:

e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]

y = 0 means no blocking (# blocks = y+1 = ”1 block”)

Note: y = 0 value must be used with number of block regions of one as indicated

by (x) = 0

2Dh 001Eh

2Eh 0000h

2Fh 0000h

30h 0001h

31h 0007h

32h 0000h

33h 0020h

34h 0000h

M28W320CB M28W320CB

2Dh 0007h

2Eh 0000h

2Fh 0020h

30h 0000h

31h 001Eh

32h 0000h

33h 0000h

34h 0001h

19/42

M28W320CT, M28W320CB

Table 18. Primary Algorithm-Specific Extended Query Table

Table 19. Security Code Area

Offset Data Description

(P)h = 35h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”0052h

0049h

(P+3)h = 38h 0031h Major version number, ASCII

(P+4)h = 39h 0030h Minor version number, ASCII

(P+5)h = 3Ah 0006h Extended Query table contents for Primary Algorithm

bit 0 Chip Erase supported (1 = Yes, 0 = No)

bit 1 Erase Suspend supported (1 = Yes, 0 = No)

bit 2 Program Suspend (1 = Yes, 0 = No)

bit 3 Lock/Unlock supported (1 = Yes, 0 = No)

bit 4 Quequed Erase supported (1 = Yes, 0 = No)

bit 31 to 5 Reserved; undefined bits are ‘0’

0000h

(P+7)h 0000h

(P+8)h 0000h

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported during Erase or

Program operation

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’

(P+A)h = 3Fh 0000h Block Lock Status

Defines which bits in the Block Status Register section of the Query are implemented.

bit 0 Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No)

bit 1 Block Lock StatusRegister Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

(P+B)h 0000h

(P+C)h = 41h 0027h VDD Logic Supply Optimum Program/Erase voltage (highest performance)

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

(P+D)h = 42h 00C0h VPP Supply Optimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

(P+E)h 0000h Reserved

Offset Data Description

80h 00XX Protection Register Lock

81h XXXX

64 bits: unique device number

82h XXXX

83h XXXX

84h XXXX

85h XXXX

64 bits: User Programmable OTP

86h XXXX

87h XXXX

88h XXXX

M28W320CT, M28W320CB

20/42

Table 20. DC Characteristics

(TA=0to70°C or –40 to 85°C; VDD =V

DDQ = 2.7V to 3.6V)

Symbol Parameter Test Condition Min Typ Max Unit

ILI Input Leakage Current 0V≤VIN ≤VDDQ ±1µA

ILO Output Leakage Current 0V≤ VOUT ≤VDDQ ±10 µA

ICC Supply Current (Read) E=V

SS,G=V

IH, f = 5MHz 10 20 mA

ICC1 Supply Current (Stand-by or

Automatic Stand-by) E=V

DDQ ±0.2V,

RP = VDDQ ±0.2V 15 50 µA

ICC2 Supply Current

(Reset) RP = VSS ±0.2V 15 50 µA

ICC3 Supply Current (Program)

Program in progress

VPP = 12V ±5% 10 20 mA

Program in progress

VPP =V

DD 10 20 mA

ICC4 Supply Current (Erase)

Erase in progress

VPP = 12V ±5% 520mA

Erase in progress

VPP =V

DD 520mA

CC5 Supply Current

(Program/Erase Suspend) E=V

DDQ ±0.2V,

Erase suspended 50 µA

IPP Program Current

(Read or Stand-by) VPP >V

DD 400 µA

IPP1 Program Current

(Read or Stand-by) VPP ≤VDD 5µA

IPP2 Program Current (Reset) RP = VSS ±0.2V 5µA

IPP3 Program Current (Program)

Program in progress

VPP = 12V ±5% 10 mA

Program in progress

VPP =V

DD 5µA

IPP4 Program Current (Erase)

Erase in progress

VPP = 12V ±5% 10 mA

Erase in progress

VPP =V

DD 5µA

VIL Input Low Voltage –0.5 0.4 V

VDDQ ≥2.7V –0.5 0.8 V

VIH Input High Voltage VDDQ –0.4 VDDQ +0.4 V

VDDQ ≥2.7V 0.7 VDDQ VDDQ +0.4 V

VOL Output Low Voltage IOL = 100µA, VDD =V

DD min,

VDDQ =V

DDQ min 0.1 V

VOH Output High Voltage IOH = –100µA, VDD =V

DD min,

VDDQ =V

DDQ min VDDQ –0.1 V

VPP1 Program Voltage (Program or

Erase operations) 1.65 3.6 V

VPPH Program Voltage

(Program or Erase

operations) 11.4 12.6 V

VPPLK Program Voltage

(Program and Erase lock-out) 1V

LKO VDD Supply Voltage (Program

and Erase lock-out) 2V

21/42

M28W320CT, M28W320CB

Figure 6. AC Testing Load Circuit

AI00609B

VDDQ/2

OUT

CL= 50pF

CLincludes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 21. AC Measurement Conditions

Input Rise and Fall Times ≤10ns

Input Pulse Voltages 0toV

DDQ

Input and Output Timing Ref. Voltages VDDQ/2

Figure 5. AC Testing Input Output Waveform

AI00610

VDDQ

VDDQ/2

Table 22. Capacitance (1) (TA=25°C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6pF

OUT Output Capacitance VOUT =0V 12 pF

M28W320CT, M28W320CB

22/42

Table 23. Read AC Characteristics (1)

(TA= 0 to 70°C or –40 to 85°C)

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. G may be delayed by up to tELQV -t

GLQV after the falling edge of E without increasing tELQV.

4. The device Reset is possible but not guaranteed if tPLPH < 100ns.

Symbol Alt Parameter

M28W320C

Unit

90 100

VDD = 2.7V to 3.6V

VDDQ = 2.7V min VDD = 2.7V to 3.6V

VDDQ = 1.65V min

Min Max Min Max

tAVAV tRC Address Valid to Next Address Valid 90 100 ns

tAVQV tACC Address Valid to Output Valid 90 100 ns

tAXQX (2) tOH Address Transition to Output Transition 0 0 ns

tEHQX (2) tOH Chip Enable High to Output Transition 0 0 ns

tEHQZ (2) tHZ Chip Enable High to Output Hi-Z 25 30 ns

tELQV (3) tCE Chip Enable Low to Output Valid 90 100 ns

tELQX (2) tLZ Chip Enable Low to Output Transition 0 0 ns

tGHQX (2) tOH Output Enable High to Output Transition 0 0 ns

tGHQZ (2) tDF Output Enable High to Output Hi-Z 25 30 ns

tGLQV (3) tOE Output Enable Low to Output Valid 30 35 ns

tGLQX (2) tOLZ Output Enable Low to Output Transition 0 0 ns

tPHQV tPWH Reset High to Output Valid 150 150 ns

tPLPH (2,4) tRP Reset Pulse Width 100 100 ns

23/42

M28W320CT, M28W320CB

Figure 7. Read AC Waveforms

DQ0-DQ15

AI02688

VALID

A0-A20

tAXQX

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

tPHQV

POWER-UP

AND STANDBY ADDRESS VALID

AND CHIP ENABLE OUTPUTS

ENABLED DATA VALID STANDBY

tGHQX

tGHQZ

tEHQX

tEHQZ

Note: Write Enable (W) = High.

M28W320CT, M28W320CB

24/42

Table 24. Write AC Characteristics, Write Enable Controlled (1)

(TA= 0 to 70°C or –40 to 85°C)

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. The device Reset is possible but not guaranteed if tPLPH < 100ns.

4. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.

5. Applicable if VPP is seen as alogic input (VPP < 3.6V).

Symbol Alt Parameter

M28W320C

Unit

90 100

VDD = 2.7V to 3.6V

VDDQ = 2.7V min VDD = 2.7V to 3.6V

VDDQ = 1.65V min

Min Max Min Max

tAVAV tWC Write Cycle Time 90 100 ns

tAVWH tAS Address Validto Write Enable High 50 50 ns

tDVWH tDS Data Valid to Write Enable High 50 50 ns

tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns

tPHWL tPS Reset High to Write Enable Low 90 100 ns

tPLPH (2, 3) tRP Reset Pulse Width 100 100 ns

tPLRH (2, 4) Reset Low to Program/Erase Abort 30 30 µs

tQVVPL (2, 5) Output Valid to VPP Low 00ns

QVWPL Data Valid to Write Protect Low 0 0 ns

tVPHWH (2) tVPS VPP High to Write Enable High 200 200 ns

tWHAX tAH Write Enable High to Address Transition 0 0 ns

tWHDX tDH Write Enable High to Data Transition 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High 0 0 ns

tWHGL Write Enable High to Output Enable Low 30 30 ns

tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns

tWLWH tWP Write Enable Low to Write Enable High 50 50 ns

tWPHWH Write Protect High to Write Enable High 50 50 ns

tAVAV tWC Write Cycle Time 90 100 ns

tAVWH tAS Address Validto Write Enable High 50 50 ns

25/42

M28W320CT, M28W320CB

Figure 8. Write AC Waveforms, W Controlled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A20

tAVAV

tQVVPL

tAVWH tWHAX

PROGRAM OR ERASE

tELWL tWHEH

tWHDXtDVWH

tWLWH

tPHWL

tWHWL

tVPHWH

POWER-UP AND

SET-UP COMMAND CONFIRM

COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tWHQV

AI03574

tWPHWH

tWHGL

tQVWPL

M28W320CT, M28W320CB

26/42

Table 25. Write AC Characteristics, Chip Enable Controlled (1)

(TA=0to70°C or –40 to 85°C)

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. The device Reset is possible but not guaranteed if tPLPH < 100ns.

4. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.

5. Applicable if VPP is seen as alogic input (VPP < 3.6V).

Symbol Alt Parameter

M28W320C

Unit

90 100

VDD = 2.7V to 3.6V

VDDQ = 2.7V min VDD = 2.7V to 3.6V

VDDQ = 1.65V min

Min Max Min Max

tAVAV tWC Write Cycle Time 90 100 ns

tAVEH tAS Address Validto Chip Enable High 50 50 ns

tDVEH tDS Data Valid to Chip Enable High 50 50 ns

tEHAX tAH Chip Enable High to Address Transition 0 0 ns

tEHDX tDH Chip Enable High to Data Transition 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low 30 30 ns

tEHGL Chip Enable High to Output Enable Low 30 30 ns

tEHWH tWH Chip Enable High to Write Enable High 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High 50 50 ns

tPHEL tPS Reset High to Chip Enable Low 90 100 ns

tPLPH (2, 3) tRP Reset Pulse Width 100 100 ns

tPLRH (2, 4) Reset Low to Program/Erase Abort 30 30 µs

tQVVPL (2, 5) Output Valid to VPP Low 0 0 ns

tQVWPL Data Valid to Write Protect Low 0 0 ns

tVPHEH (2) tVPS VPP High to Chip Enable High 200 200 ns

tWLEL tCS Write Enable Low to Chip Enable Low 0 0 ns

tWPHEH Write Protect High to Chip Enable High 50 50 ns

tAVAV tWC Write Cycle Time 90 100 ns

tAVEH tAS Address Validto Chip Enable High 50 50 ns

27/42

M28W320CT, M28W320CB

Figure 9. Write AC Waveforms, E Controlled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A20

tAVAV

tQVVPL

tAVEH tEHAX

PROGRAM OR ERASE

tWLEL tEHWH

tEHDXtDVEH

tELEH

tPHEL

tEHEL

tVPHEH

POWER-UP AND

SET-UP COMMAND CONFIRM

COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tEHQV

AI03575

tWPHEH

tEHGL

tQVWPL

M28W320CT, M28W320CB

28/42

Figure 10. Reset AC Waveform

AI03537

tPHQV

tPLPH

≤

tPLPH

Reset during Read Mode

Reset during Program with tPLPH tPLRH

tPLRH tPHWL

tPHEL

Abort

Complete

tPLPH

Reset during Program/Erasewith tPLPH >t

PLRH

tPLRH tPHWL

tPHEL

Abort

Complete Reset

29/42

M28W320CT, M28W320CB

Figure 11. Program Flowchart and Pseudo Code

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

Write 40h or

10h

Command

AI03538

Start

Write

Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP

Invalid

Error (1, 2)

Program

Error (1, 2)

Program

instruction:

– write 40h or 10h

command

– write Address &

Data

(memory enters read status state

after

the Program instruction)

do:

– read status register (E or G must

toggled) if PES instruction given

execute

suspendprogram loop

while b7 = 1

If b3 = 1, VPP invalid

error:

– error handler

If b4 = 1, Program

error:

– error handler

YES

End

YES

b1 = 0 Program to

Protected

Block Error (1, 2) If b1 = 1, Program to protected block

error:

– error handler

Suspend

Loop

YES

M28W320CT, M28W320CB

30/42

Figure 12. Double Word Program Flowchart and Pseudo Code

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for address bit A0.

Write

30h

Command

AI03539

Start

Write Address

& Data 1 (3)

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP

Invalid

Error (1, 2)

Program

Error (1, 2)

DPG

instruction:

– write 30h

command

– write Address 1 & Data 1

(3)

– write Address 2 & Data 2

(3)

(memory enters read status state

after

the Program instruction)

do:

– read status register (E or G must

toggled) if PES instruction given

execute

DPG suspend loop

while b7 = 1

If b3 = 1, VPP invalid

error:

– error handler

If b4 = 1, Program

error:

– error handler

YES

End

YES

b1 = 0 Program to

Protected

Block Error (1, 2) If b1 = 1, Program to protected block

error:

– error handler

Suspend

Loop

YES

Write Address

& Data 2 (3)

31/42

M28W320CT, M28W320CB

Figure 13. Program Suspend & Resume Flowchart and Pseudo Code

Write

70h

Command

AI03540

Read Status

YES

b7=1

YES

b2=1

Program Continues

Write a

read

Command

PES

instruction:

– write B0h command

do:

– read status

(E or G must be toggled)

while b7 = 1

If b2 =0 Program completed

Write

D0h

Command

PER

instruction:

– write D0h command to

resume

the

program

– if the program operation completed

then this is not

necessary.

The device returns to Read Array

normal (as if the

Program/Erase

suspend was not issued).

Read data

from

another address

Start

Write

B0h

Command

Program Complete

Write FFh

Command

Read Data

M28W320CT, M28W320CB

32/42

Figure 14. Erase Flowchart and Pseudo Code

Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

Write

20h

Command

AI03541

Start

Write Block

Address

& D0h Command

Read Status

YES

b7 = 1

YES

b3 = 0

b4, b5 = 0

VPP

Invalid

Error (1)

Command

Sequence Error (1)

instruction:

– write 20h

command

– write Block Address (A12-A20) &

command

D0h

(memory enters read status state

after

the EE instruction)

do:

– read status register (E or G must

toggled) if PES instruction given

execute

suspend erase loop

while b7 = 1

If b3 = 1, VPP invalid

error:

– error handler

If b4, b5 = 1, Command sequence

error:

– error handler

YES

b5 = 0 Erase Error (1)

YES

Suspend

Loop

If b5 = 1, Erase

error:

– error handler

End

YES

b1 = 0 Erase to

Protected

Block Error (1) If b1 = 1, Erase to protected block

error:

– error handler

YES

33/42

M28W320CT, M28W320CB

Figure 15. Erase Suspend & Resume Flowchart and Pseudo Code

Write

70h

Command

AI03542

Read Status

YES

b7=1

YES

b6=1

Erase Continues

PES

instruction:

– write B0h command

do:

– read status

(E or G must be toggled)

while b7 = 1

If b6 = 0, Erase completed

Write

D0h

Command

Read data

from

another

block

Program/Protection

Program

Block Protect/Unprotect/Lock

Start

Write

B0h

Command

Erase Complete

Write FFh

Command

Read Data

PER

instruction:

– write D0h command to

resume

erasure

– if the erase operation completed

then this is not

necessary.

The device returns to Read Array

normal (as if the

Program/Erase

suspend was not issued).

M28W320CT, M28W320CB

34/42

Figure 16. Command Interface and Program Erase Controller Flowchart (a)

Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or

if VDD falls below VLKO, the Command Interface defaults to Read Array mode.

2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

AI03543

READ

SIGNATURE

YES

90h

READ

STATUS

YES

70h NO

CLEAR

STATUS

YES

50h NO

PROGRAM

SET-UP

YES

40h

10h NO

ERASE

SET-UP

YES

20h NO

ERASE

COMMAND

ERROR

YES

FFh

WAIT FOR

COMMAND

WRITE (1)

READ

STATUS

READ

ARRAY

YES

D0h NO

CFI

QUERY

YES

98h NO

YES

60h NO

BP/BU/BL

SET-UP

PRP

SET-UP

YES

C0h NO

DPG

SET-UP

YES

30h NO

01h D0h 2Fh

PRP

READY

(2)

NO NO NO

BP/BU/BL

COMMAND

ERROR

BLOCK

PROTECT

BLOCK

UNPROTECT

BLOCK

LOCK

YES YES YES

YES

35/42

M28W320CT, M28W320CB

Figure 17. Command Interface and Program Erase Controller Flowchart (b)

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

READ

STATUS

YES

70h

ERASE

YES READY

(2)

B0h NO

READ

STATUS

YES READY

(2)

ERASE

SUSPEND

YES

D0h

READ

ARRAY

YES

ERASE

SUSPENDE D

READ

STATUS

(READ STATUS)

YES

NO (READ STATUS)

ERASE

RESUME

90h

READ

SIGNATURE YES

98h

CFI

QUERY YES

40h

10h

PROGRAM

SET-UP YES

30h

DPG

SET-UP YES

60h

BP/BU/BL

SET-UP YES

C0h PRP

SET-UP PRP READY

(2)

YES YES

AI03544

M28W320CT, M28W320CB

36/42

Figure 18. Command Interface and Program Erase Controller Flowchart (c)

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

READ

STATUS

YES

70h

PROGRAM

YES READY

(2)

B0h NO

READ

STATUS

YES READY

(2)

PROGRAM

SUSPEND

YES

D0h

READ

ARRAY

YES

PROGRAM

SUSPENDED

READ

STATUS

(READ STATUS)

YES

NO (READ STATUS)

PROGRAM

RESUME

90h

READ

SIGNATURE YES

98h

CFI

QUERY YES

AI03545

37/42

M28W320CT, M28W320CB

Table 26. Ordering Information Scheme

Devices are shipped from the factory withthe memory content bits erased to ’1’.

Table 27. Daisy Chain Ordering Scheme

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

Example: M28W320CT 90 N 6 T

Device Type

M28

Operating Voltage

W=V

DD = 2.7V to 3.6V; VDDQ = 1.65V or 2.7V

Device Function

320C = 32 Mbit (2 Mb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Random Speed

90 = 90 ns

100 = 100 ns

Package

N = TSOP48: 12 x 20 mm

GB = µBGA47: 0.75 mm pitch

Temperature Range

1=0to70°C

6=–40to85°C

Option

T = Tape & Reel Packing

Example: M28W320C -GB T

Device Type

M28W320C

Daisy Chain

-GB = µBGA47: 0.75 mm pitch

Option

T = Tape & Reel Packing

M28W320CT, M28W320CB

38/42

Table 28. Revision History

Date Revision Details

February 2000 First Issue

04/19/00 Daisy Chain part numbering defined

µBGA Package Outline diagram change (Figure 20)

µBGA Chain diagrams, Package and PCB Connection re-designed (Figure 21, 22)

05/17/00 µBGA Package Outline diagram and Package Mechanical Data change (Figure 20, Table 30)

39/42

M28W320CT, M28W320CB

Table 29. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 1.20 0.0472

A1 0.05 0.15 0.0020 0.0059

A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

α0°5°0°5°

N48 48

CP 0.10 0.0039

Figure 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

Drawing is not to scale.

TSOP-a

N/2

DIE

LA1 α

M28W320CT, M28W320CB

40/42

Table 30. µBGA47 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data

Symbol mm inch

Typ Min Max Typ Min Max

A 1.000 0.0394

A1 0.180 0.0071

A2 0.700 – – 0.0276 – –

b 0.350 0.300 0.400 0.0138 0.0118 0.0157

D 10.500 10.450 10.550 0.4134 0.4114 0.4154

D1 3.750 – – 0.1476 – –

ddd 0.080 0.0031

e 0.750 – – 0.0295 – –

E 6.390 6.340 6.440 0.2516 0.2496 0.2535

E1 5.250 – – 0.2067 – –

FD 3.375 – – 0.1329 – –

FE 0.570 – – 0.0224 – –

Figure 20. µBGA47 - 8 x 6 balls, 0.75 mm pitch, Bottom View Package Outline

Drawing is not to scale.

D1D

BGA-G06

ddd

BALL ”A1”

41/42

M28W320CT, M28W320CB

Figure 21. µBGA47 Daisy Chain - Package Connections (Top view through package)

Figure 22. µBGA47 Daisy Chain - PCB Connections (Top view through package)

AI03295

87654321

AI3296

87654321

START

POINT

END

POINT

M28W320CT, M28W320CB

42/42

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