19-0874; Rev 1; 7/14
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
General Description
The MAX4959/MAX4960 overvoltage protection con-
trollers protect low-voltage systems against high-volt-
age faults of up to +28V. When the input voltage
exceeds the overvoltage lockout (OVLO) threshold,
these devices turn off an external pFET to prevent dam-
age to the protected components. The undervoltage
lockout (UVLO) threshold holds the external pFET off
until the input voltage rises to the correct level. An addi-
tional safety feature latches off the pFET when an incor-
rect low-power adapter is plugged in.
The MAX4959/MAX4960 control an external battery
switchover pFET (P2) (see Figures 4 and 6) that switches
in the battery when the AC adapter is unplugged. The
undervoltage and overvoltage trip levels can be adjusted
with external resistors.
The input is protected against ±15kV HBM ESD when
bypassed with a 1µF ceramic capacitor to ground. All
devices are available in a small 10-pin (2mm x 2mm)
µDFN and are specified for operation over the extend-
ed -40°C to +85°C temperature range.
Applications
Notebooks
Laptops
Camcorders
Ultra-Mobile PCs
Features
oOvervoltage Protection Up to +28V
o± 2.5% Accurate Externally Adjustable
OVLO/UVLO Thresholds
oBattery Switchover pFET Control
oProtection Against Incorrect Power Adapter
oLow (100µA Typ) Supply Current
o25ms Input Debounce Timer
o25ms Blanking Time
o10-Pin (2mm x 2mm) µDFN Packages
Ordering Information
PART
TEMP RANGE
PIN -
PA C K A G E
TOP
MARK
MAX4959ELB+
-40°C to +85°C
10 µDFN AAO
MAX4960ELB+
-40°C to +85°C
10 µDFN AAP
123
10 9 8
45
76
GATE2
GND
VDD
N.C.
GATE1
OVS
IN
N.C.
(SOURCE1)
MAX4959
MAX4960
µDFN
TOP VIEW
CB
UVS
+
( ) MAX4960 ONLY.
Pin Configuration
Typical Operating Circuits appear at end of data sheet.
+
Denotes a lead-free package.
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
2Maxim Integrated
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = +19V, TA= -40°C to +85°C, unless otherwise noted, CVDD = 100nF. Typical values are at TA = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, SOURCE1, GATE1, GATE2, to GND ................-0.3V to +30V
VDD to GND..............................................................-0.3V to +6V
UVS, OVS, CB to GND .............................................-0.3V to +6V
Continuous Power Dissipation (TA= +70°C)
10-pin µDFN (derate 5.0mW/°C above +70°C) ...........403mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IN
Input Voltage Range VIN 428V
Overvoltage Adjustable Trip
Range OVLO (Note 2) 6 28 V
Overvoltage Comp Reference OVREF VIN rising edge 1.18 1.228 1.276 V
OVS Input Leakage Current OVILKG -100 +100 nA
Overvoltage Trip Hysteresis OVHYS 1%
Undervoltage Adjustable Trip
Range UVLO (Note 2) 5 28 V
Undervoltage Comp Reference UVREF VIN falling edge 1.18 1.228 1.276 V
UVS Input Leakage Current UVILKG -100 +100 nA
Undervoltage Trip Hysteresis UVHYS 1%
Internal Undervoltage Trip Level INTUVREF VIN falling edge 4.1 4.4 4.7 V
Internal Undervoltage Trip
Hysteresis INTUVHYS 1%
Power-On Trip Level POTL VDD > +3V, IN rising edge 0.5 0.75 1 V
Power-On Trip Hysteresis POTLHYS 10 %
IN Supply Current IIN VIN = +19V, VOVS < OVREF and
VUVS > UVREF 100 300 µA
VDD
VDD Voltage Range VDD 2.7 5.5 V
VDD Undervoltage Lockout VDDUVLO VDD falling edge 1.55 2.40 V
VDD Undervoltage Lockout
Hysteresis V
D D UV LOHY S 50 mV
VDD Supply Current IVDD VDD = +5V, VIN = 0V 10 µA
GATE_
GATE1 Open-Drain MOS RON
Resistance RON VCB = 0V, VIN = 19V, VOVS < OVREF and
VUVS > UVREF, IGATE_ = 0.5mA (MAX4959) 1kΩ
GATE2 Open-Drain MOS RON
Resistance RON VCB = 3V, IGATE_ = 0.5mA 1 kΩ
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
3
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +19V, TA= -40°C to +85°C, unless otherwise noted, CVDD = 100nF. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE1 Leakage Current G1ILKG V
OV S
> OV
R E F
, V
U V S
< U V
R E F
, or V
C B = + 5V -1 +1 µA
GATE2 Leakage Current G2ILKG VCB = 0V -1 +1 µA
CB
Logic-Level High VIH 1.5 V
Logic-Level Low VIL 0.4 V
CB Pulldown Resistor RCBPD 123MΩ
TIMING
Debounce Time tDEB VOVP > VIN > VUVP for greater than tDEB for
GATE1 to go low 10 25 40 ms
GATE1 Assertion Delay from
CB Pin t1GATE CB = +3V to 0
rise time = fall time = 5ns (Note 3) 50 ns
GATE2 Assertion Delay from
CB Pin t2GATE CB = 0 to +3V
rise time = fall time = 5ns (Note 3) 50 ns
Blanking Time tBLANK 10 25 40 ms
MAX4960
SOURCE1/GATE1 Resistance RSG (MAX4960) 140 200 260 kΩ
GATE1/Ground Resistance RGG GATE1 Asserted (MAX4960) 140 200 260 kΩ
Note 1: All devices are production tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Do not exceed absolute maximum rating; the ratio between the externally set OVLO and UVLO threshold must not exceed 4,
[OVLO/UVLO]MAX ≤4.
Note 3: Assertion delay starts from switching of CB pin to reaching of 80% of GATE1/GATE2 transition. This delay is measured without
external capacitive load.
POWER-UP RESPONSE
(RPULLUP = 1kΩ)
MAX4959/60 toc01
TIME (μs)
VOLTAGE (V)
100500-50-100
0
2
4
6
8
10
12
-2
-150 150
VIN
VDD
VGATE1
OVERVOLTAGE RESPONSE
(RPULLUP = 5kΩ)
MAX4959/60 toc02
TIME (μs)
VOLTAGE (V)
100500-50-100
5
10
15
20
25
30
0
-150 150
VIN
VDD
VGATE1
Typical Operating Characteristics
(VOVLO = 22.2V and VUVLO = 10.1V, R1 = 887kΩ, R2 = 66.5kΩ, R3 = 54.9kΩ, all resistors 1%, OVREF = UVREF = 1.228V.)
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
4Maxim Integrated
LOW-POWER ADAPTER RESPONSE
(VOVLO = 22.3V, VUVLO = 10.1V, pFET = IRF7726)
MAX4959/60 toc04
TIME (s)
VOLTAGE (V)
0.250.20.150.1.05
1
3
5
7
9
11
13
-1
0 0.3
LOAD BECOMES
PRESENT
DRAIN OF P1
VIN VGATE1
BATTERY SWITCHOVER WITH ADAPTER-
PLUGGED RESPONSE
(VIN = 19V, VGATE2-PULLUP = 4.2V, RPULLUP = 5kΩ)
MAX4959/60 toc05
TIME (μs)
VOLTAGE (V)
100500-50-100
0
5
10
15
20
25
-5
-150 150
VGATE1
VGATE2
CB
OVERVOLTAGE AND UNDERVOLTAGE TRIP
DIFFERENCE vs. TEMPERATURE
(RPULLUP = 1kΩ)
MAX4959/60 toc06
TEMPERATURE (°C)
VOLTAGE (V)
70503010-10-30
-4
-3
-2
-1
0
1
2
3
4
5
-5
-50 90
UV TRIP DIFF
OV TRIP DIFF
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX4959/60 toc07
VIN (V)
ISUPP (μA)
252015105
0
40
80
120
160
200
-40
0
LOGIC-INPUT THRESHOLD vs. TEMPERATURE
MAX4959/60 toc08
TEMPERATURE (°C)
LOGIC THRESHOLD (V)
907030 50-10 10-30
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
-50
VTH-LO
VTH-HI
VDD SUPPLY CURRENT vs. TEMPERATURE
MAX4959/60 toc09
TEMPERATURE (°C)
VDD SUPPLY CURRENT (μA)
9070503010-10-30
4
4.5
5
3.5
-50 110
VOLTAGE RANGE vs. INPUT VOLTAGE RANGE
MAX4959/60 toc10
VIN (V)
VDD (V)
1052515 20
1
2
3
4
5
6
0
0
Typical Operating Characteristics (continued)
(VOVLO = 22.2V and VUVLO = 10.1V, R1 = 887kΩ, R2 = 66.5kΩ, R3 = 54.9kΩ, all resistors 1%, OVREF = UVREF = 1.228V.)
Detailed Description
The MAX4959/MAX4960 provide up to +28V overvoltage
protection for low-voltage systems. When the input volt-
age exceeds the overvoltage trip level, the MAX4959/
MAX4960 turn off an external pFET to prevent damage
to the protected components.
The MAX4959/MAX4960 feature a control bit (CB) pin
that controls an external battery-switchover function that
switches in the battery when the adapter is unconnect-
ed. The host system detects when the battery switchover
must take place and pulls CB high to turn on P2. The
load current is not interrupted during battery switchover
as the body diode of P2 conducts until the CB line is dri-
ven high (see the
MAX4959 Typical Operating Circuit 1
,
Figure 4).
An additional safety feature latches off pFET P1 when a
low-power adapter is plugged in. This protects the sys-
tem from seeing repeated adapter insertions and
removals when an incorrect low-power adapter is
plugged in that cannot provide sufficient current.
Undervoltage Lockout (UVLO)
The MAX4959/MAX4960 have an adjustable undervolt-
age lockout threshold ranging from +5V to +28V. When
VIN is less than the VUVLO, the device waits for a blank-
ing time, tBLANK, to see if the fault still exists. If the fault
does not exist at the end of tBLANK, P1 remains on. If
VIN is less than VUVLO for longer than the blanking
time, the device turns P1 off and P1 does not turn on
again until VIN < 0.75V. See Figure 1.
Overvoltage Lockout (OVLO)
The MAX4959/MAX4960 have an adjustable overvolt-
age lockout threshold ranging from +6V to +28V. When
VIN is greater than the VOVLO, the device turns P1 off
immediately. When VIN drops below VOVLO, P1 turns on
again after the debounce time has elapsed.
Device Operation
High-Voltage Adapter (V
IN
> V
OVLO
)
If an adapter with a voltage higher than VOVLO is
plugged in, the MAX4959/MAX4960 is in an OVP condi-
tion, so P1 is kept off or immediately turned off. There is
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
5
Maxim Integrated
Pin Description
PIN
MAX4959
MAX4960
NAME FUNCTION
1 1 GATE1
pFET Gate Drive Output Open Drain. GATE1 is actively driven low, except during fault
(OVP or UVP) condition (the external pFET is turned off). When VUVLO < VIN < VOVLO,
GATE1 is driven low (the external pFET P1 is turned on).
2, 9 9 N.C. No Connection. Not internally connected. (Connect to ground or leave unconnected.)
—2
SOURCE1
pFET Source Output. An internal resistor is connected between SOURCE1 and GATE1.
33IN
Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage
sense input. Bypass IN to GND with a 1µF ceramic capacitor to get a ±15kV protected
input. A minimum 0.1µF ceramic capacitor is required for proper operation.
4 4 UVS Undervoltage Threshold Set Input. Connect UVS to an external resistive divider from IN to
GND to set the undervoltage lockout threshold. (See Typical Operating Circuits.)
5 5 OVS Overvoltage Threshold Set Input. Connect OVS to an external resistive divider from
IN to GND to set the overvoltage lockout threshold. (See Typical Operating Circuits.)
66V
DD Inter nal P ow er - S up p l y Outp ut. Byp ass V
DD to G N D w i th a 0.1µF m i ni m um cap aci tor .
V
DD p ow er s the i nter nal p ow er - on r eset ci r cui ts. ( S ee the V
D D
C ap aci tor S el ecti on secti on.)
77CB
Battery Switchover Control Input. When CB is high, GATE1 is high (P1 is off), and GATE2
is low (P2 is on). When CB is low, GATE1 is controlled by internal logic and GATE2 is
high (P2 is off). GATE1 is controlled by CB only if VUVLO < VIN < VOVLO.
8 8 GND Ground
10 10 GATE2 pFET Gate Drive Output, Open Drain. When CB is high, GATE2 is low (P2 is on).
When CB is low, GATE2 is high impedance (P2 is off).
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
6Maxim Integrated
no blanking time for OVP, but the debounce time
applies once the IN voltage falls below VOVLO but
above VUVLO. When the voltage at IN is higher than
VOVLO, the CB pin does not control P1.
Correct Adapter (V
UVLO
< V
IN
< V
OVLO
)
In this case, when the adapter is plugged in, the device
goes through a 20ms (typ) debounce time and ensures
that the voltage at IN is between VUVLO and VOVLO
before P1 is turned on. In this state, the CB pin controls
both P1 and P2.
Low-Power Adapter or Glitch Condition
If the adapter has the correct voltage but not enough
power (incorrect low-power adapter), the MAX4959/
MAX4960 protect pFET P1 from oscillation. When the
adapter is first plugged in, P1 is off so the voltage is cor-
rect. When P1 is turned on after the debounce time, the
low-power adapter is dragged down to below VUVLO.
The device waits for a 10ms blanking time to make sure
it is not a temporary glitch, and, if a fault still exists, it
latches off P1. P1 does not turn on again until the
adapter is unplugged (VIN < ~0.75V) and plugged in
again. This feature can work without the battery present
MAX4959
+
-
+
-
+
-
+
-
GATE2
CB
GND
UVS
OVS
VDD
N2N1
GATE1
N
IN
VSG
+
-
+
-
LOGIC
DIGITAL
SUPPLY
ANALOG
SUPPLY
BANDGAP
UVLO
OVLO
UVLOINT
POWER
ON
VDD
UVLO
VREF1 = 2V
VREF2 = 0.7V
POWER-ON
RESET AND
OFF STORAGE
Functional Diagram for the MAX4959
Functional Diagrams
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
7
Maxim Integrated
only if the backup capacitor on VDD is large enough to
maintain power for greater than the 10ms blanking time.
The detection that the adapter is unplugged and
plugged in again is implemented by monitoring the VIN
signal. The adapter is unplugged when VIN drops below
VIN = ~0.75V, and it is plugged in when VIN becomes
greater than VIN = ~0.75V. To ensure the monitoring of
this lower threshold, an external storage capacitor at the
VDD pin is necessary. When the input voltage VIN drops
below 4V, power for some internal VIN monitoring circuit-
ry is supplied by the external capacitor at the VDD pin.
This capacitor is supplied by VIN through a diode and is
internally limited to 5.5V.
Adapter Not Present (V
IN
< V
UVLO
)
When the input voltage VIN drops below 4.4V, P1 is
turned off automatically and P1 does not turn on again
until the adapter is unplugged (VIN < ~0.75V) and
plugged in again. When the adapter is not present, P1 is
kept off with the gate-source resistor (which is internal for
the MAX4960 and external for the MAX4959), and the
CB pin controls the battery switchover pFET P2.
MAX4960
+
-
+
-
+
-
+
-
GATE2
CB
GND
UVS
OVS
VDD
N2
N1
GATE1SOURCE1
N
IN
VSG
+
-
+
-
LOGIC
DIGITAL
SUPPLY
ANALOG
SUPPLY
BANDGAP
UVLO
OVLO
UVLOINT
POWER
ON
VDD
UVLO
VREF1 = 2V
VREF2 = 0.7V
POWER-ON
RESET AND
OFF STORAGE
Functional Diagram for the MAX4960
Functional Diagrams (continued)
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
8Maxim Integrated
VIN
VOVLO VOVLO
VUVLO
VDD REGULATED
tDEB tDEB tBLANK tBLANK
tDEB
VUVLO
INTUVREF
VGATE1
VDD
VCB
VGATE2
Figure 1. Timing Diagram
IN RANGE P1 STATE P2 STATE
VIN > VOVLO P1 OFF (not affected by CB)
VUVLO < VIN < VOVLO
(debounce timeout ongoing) P1 OFF (not affected by CB)
VUVLO < VIN < VOVLO
(debounce timeout elapsed)
CB = 1 -> P1 is OFF
CB = 0 -> P1 is ON
VINTUVREF < VIN < VOVLO
(blanking timeout ongoing)
CB = 1 -> P1 is OFF
CB = 0 -> P1 is ON
VINTUVREF < VIN < VOVLO
(blanking timeout elapsed)
P1 OFF (not affected by CB). P1 does not turn on again until
adapter is unplugged (VIN < ~0.75V) and plugged in again.
VIN < VINTUVREF P1 OFF (not affected by CB). P1 does not turn on again until
adapter is unplugged (VIN < ~0.75V) and plugged in again.
CB = 1 -> P2 is ON
CB = 0 -> P2 is OFF
The following table lists the different modes of operations:
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
9
Maxim Integrated
Applications Information
MOSFET Configuration and Selection
The MAX4959/MAX4960 are used with a single MOS-
FET configuration as shown in the
Typical Operating
Circuits
to regulate voltage as a low-cost solution.
The MAX4959/MAX4960 are designed with pFETs. For
lower on-resistance, the external MOSFET can be multi-
ple pFETs in parallel. In most situations, MOSFETs with
RDS(ON) specified for a VGS of 4.5V work well. Also,
MOSFETs (with VDS ≥30V) withstand the full +28V IN
range of the MAX4959/MAX4960.
Resistor Selection for
Overvoltage/Undervoltage Window
The MAX4959/MAX4960 include undervoltage and
overvoltage comparators for window detection (see
Figure 4). GATE1 is enhanced and after the debounce
time, the pFET is turned on when the monitored voltage
is within the selected window.
The resistor values R1, R2, and R3 can be calculated
as follows:
where RTOTAL = R1 + R2 + R3.
Use the following steps to determine the values for R1,
R2, and R3:
1) Choose a value for RTOTAL, the sum of R1, R2, and
R3. Because the MAX4959/MAX4960 have very
high input impedance, RTOTAL can be up to 5MΩ.
2) Calculate R3 based on RTOTAL and the desired
VOVLO trip point:
3) Calculate R2 based on RTOTAL, R3, and the desired
VUVLO trip point:
4) Calculate R1 based on RTOTAL, R2, and R3:
R1 = RTOTAL – R2 – R3
Note that the ratio between the externally set OVLO and
UVLO threshold must not exceed:
4 [VOVLO / VUVLO]MAX ≤4
VDD Capacitor Selection
VDD is regulated to +5V by a linear regulator. Since the
minimum external adjustable UVLO trip threshold is
+5V, the VDD range is +5V to +28V and the value at
VDD is:
VDD = VIN – 0.8V where VIN = 5V to 5.8V
VDD = +5V where VIN > 5.8V
The capacitor at VDD must be large enough to provide
power to the device for an external settable time,
tHOLD, when VIN drops to 0V. The capacitor value to
have a minimum time of tHOLD is:
C = (IVDD x tHOLD) / (VDD - VDDUVLO)
The worst case scenario is where VIN = +5V, VDD = VIN
- 0.8V = +4.2V, IVDD = 10µA (max). For a tHOLD time of
20ms, C = (10µA x 20ms) / (4.2V - 2.2V) = 100nF.
Note: The capacitor must be greater than 100nF for the
internal regulator to be stable, and needs to have low
ESR and low leakage current, for example, a ceramic
capacitor.
IN Bypass Considerations
For most applications, bypass IN to GND with a 1µF
ceramic capacitor. If the power source has significant
inductance due to long lead length, take care to pre-
vent overshoots due to the LC tank circuit, and provide
protection if necessary to prevent exceeding the +30V
absolute maximum rating on VIN.
The MAX4959/MAX4960 provide protection against volt-
age faults up to+28V, but this does not include negative
voltages. If negative voltages are a concern, connect a
Schottky diode from IN to GND to clamp negative input
voltages.
ESD Test Conditions
The MAX4959/MAX4960 are protected from ±15kV
Human Body Model ESD on IN when IN is bypassed to
ground with a 1µF ceramic capacitor.
Human Body Model
Figure 2 shows the Human Body Model and Figure 3
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest
that is then discharged into the device through a 1.5kΩ
resistor.
RUR
REF TOTAL
UVLO
23=×
⎡
⎣
⎢⎤
⎦
⎥−
V
VR
ROR
REF TOTAL
OVLO
3=×V
V
VU
R
R
VO
R
UVLO REF TOTAL
OVLO REF TOTAL
=
()
+
⎛
⎝
⎜⎞
⎠
⎟
=
()
⎛
⎝
⎜⎞
⎠
⎟
VR
VR
23
3
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
10 Maxim Integrated
Chip Information
PROCESS: BiCMOS
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MΩ
RD
1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 2. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 3. Human Body Current Waveform
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
11
Maxim Integrated
Typical Operating Circuits
P1
CB
VREF
GND
R1
R2
R3
N2
VDD
1-CELL (4.2V) TO
4-CELL (16.8V)
RD1
N1
RU1
C1
D1
C2
RU2
P2
RD2
GATE2
GATE1IN
UVLO
OVLO
UVS
OVS
AC ADAPTER
HOLD-UP
POWER SUPPLY
LOGIC
DC-DC
CONVERTER
BATTERY
CHARGER
VSUPPLY
Figure 4. MAX4959 Typical Operating Circuit 1
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
12 Maxim Integrated
Typical Operating Circuits (continued)
CB
3.3V
GND
R1
R2
R3
N2
VDD
1-CELL (4.2V) TO
4-CELL (16.8V)
N1
GATE2
GATE1IN
UVLO
RD1
OVLO
UVS
OVS
AC ADAPTER
HOLD-UP
POWER SUPPLY
LOGIC
DC-DC
CONVERTER
SYSTEM LOAD
EN
VREF
VSUPPLY
28V
PROTECTED
CHARGER
Figure 5. MAX4959 Typical Operating Circuit 2
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
13
Maxim Integrated
Typical Operating Circuits (continued)
P1
CB
GND
R1
R2
R3
N2
VDD
1-CELL (4.2V) TO
4-CELL (16.8V)
N1
C1
C2
RU2
P2
RD2
GATE2
GATE1SOURCE1IN
UVLO
OVLO
UVS
OVS
AC ADAPTER
HOLD-UP
POWER SUPPLY
LOGIC
DC-DC
CONVERTER
BATTERY
CHARGER
VREF
VSUPPLY
Figure 6. MAX4960 Typical Operating Circuit 1
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
14 Maxim Integrated
Typical Operating Circuits (continued)
CB
GND
R1
R2
R3
N2
VDD
1-CELL (4.2V) TO
4-CELL (16.8V)
N1
GATE2
GATE1IN
UVLO
OVLO
UVS
OVS
AC ADAPTER
HOLD-UP
POWER SUPPLY
LOGIC
DC-DC
CONVERTER
BATTERY
CHARGER
SYSTEM LOAD
P1
C1
SOURCE1
VREF
VSUPPLY
Figure 7. MAX4960 Typical Operating Circuit 2
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND
PATTERN NO.
10 µDFN L1022+1 21-0164 90-0006
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________
15
© 2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 7/07 Initial release —
1 7/14 Removed µMAX products for MAX4959 and MAX4960
Mouser Electronics
Authorized Distributor
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