LM4921
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LM4921 Low Voltage I
2
S 16-Bit Stereo DAC with Stereo
Headphone Power Amplifiers and Volume Control
Check for Samples: LM4921
1FEATURES APPLICATIONS
2• 16-Bit Resolution Stereo DAC • Mobile Phones
• I2S Digital Audio Data Serial Interface • PDAs
• SPI Serial Interface (Control Register) • Portable Electronic Devices
• Volume Control (32 steps; 1.5 dB Increments) DESCRIPTION
• Up to 50mW/Channel Stereo Headphone The LM4921 combines a 16-bit resolution stereo I2S
Amplifier input digital-to-analog converter (DAC) with a stereo
• Zero Crossing Detection for Silent Attenuation headphone audio power amplifier. It is primarily
Steps designed for demanding applications in mobile
phones and other portable communication device
• 2.6VDC to 5.0VDC Digital Supply Voltage Range applications. The LM4921 features an I2S serial
• 2.6VDC to 5.5VDC Analog Supply Voltage Range interface for the digital audio information and a 16-bit
(See (1))SPI serial interface for internal register control and
• Unity-Gain Stable Headphone Amplifiers communication. With AVDD and DVDD = 3.0VDC and
driving a 32Ωsingle-ended load to a 26mWRMS
• Available in the 20-bump DSBGA Package output level the distortion (THD+N) of the LM4921 will
be less than 0.5%. The LM4921 also features a
KEY SPECIFICATIONS programmable 32-step digital volume control
• PSRR at 217Hz, A/DVDD = 3V, (See Figure 1): accessed through an SPI interface.
52dB (typ) Boomer audio power amplifiers were designed
• POUT at AVDD = 3.0V, 32Ωspecifically to provide high quality output power with a
– < 0.05% THD: 13mW (typ) minimal amount of external components. It is,
therefore, ideally suited for mobile phone and other
– < 0.05% THD: 26mW (typ) low voltage applications where minimal power
• Supply Voltage Range consumption is a primary requirement.
– DVDD: 2,6V to 5.0V The LM4921 features a low-power consumption
– AVDD: (See (1)) 2.6V to 5.5V shutdown mode, and also has an internal thermal
• Shutdown Current: 1µA (typ) shutdown protection mechanism.
(1) Best operation is achieved by maintaining 3.0V ≤AVDD ≤5.0V
and 3.0V ≤DVDD ≤5.0V.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
-
+-
Digital
Interpolation
Filter
SPI Control
Serial
Interface
VREF
Generator
Clock Logic
LPF
-
+
LPF
GNDD
AGND
SPI_DATA
SPI_ENABLE
I2S_DATA
I2S_LRCLK
I2S_CLK
HP_L
HP_R
MCLK/XTAL_IN
XTAL_OUT
BYPASS
32:
32:
+
NC
NC
V X
GNDX
NC
AVDD
100 PF
100PF
L Amp
Digital Volume
Control
R- Amp
1- Bit DAC
1- Bit DAC
AVDD
1PF2PF
DVDD
1PF
DVDD
S Digital Audio Serial InterfaceI2
+
SPI_CLK
DD
LM4921
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Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
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MCLK/
XTAL_
IN
GNDX
CLK
DATA
NCBYPASS
AVDD
HP_R
ENABLE
NCHP_LAGND
OUTDATALRCLK
NC
VDDX
DVDD
CLK
GNDD
SPI_
SPI_
SPI_
XTAL_I2S_I2S_
I2S_
OPEN
A B C D E
1
2
3
4
LM4921
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SNAS178E –JULY 2003–REVISED MAY 2013
Connection Diagrams
(1) NC - No Connection
Figure 2. LM4921 20-Bump DSBGA Pin Configuration – Top View
See Package Number YZR0020
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LM4921 I/O PIN DESCRIPTIONS
PIN # (ITL) PIN NAME PIN TYPE PIN DESCRIPTION
Input-I, Output-O,
Power-P, No Connect-
NC
B1 I2S_CLK I/O I2S Clock
C2 I2S_DATA I I2S data
B2 I2S_WS I/O I2S L/R word select
E3 SPI_CLK I SPI clcock
E4 SPI_DATA I SPI data
D3 SPI_ENABLE I SPI Enable
E2 MCLK/XTAL_IN I Master Clock / Xtal input
D2 XTAL_OUT O Xtal output
C4 BYPASS I/O Analog VDD/2 bypass capacitor connection point
B4 AVDD P Analog supply
A3 AGND P Analog Ground
C1 DVDD P Digital Supply
A1 GNDD P Digital ground
D1 VDDX P XTAL Oscillator circuit supply
E1 GNDX P XTAL Oscillator circuit ground
B3 HP_L O HP left output
A4 HP_R O HP right output
A2 No Connect O Must let float
C3 No Connect NC NC
D4 No Connect NC NC
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage 6.0V
Storage Temperature −65°C to +150°C
Input Voltage -0.3V to VDD + 0.3V
Power Dissipation(3) Internally Limited
Human body model(4) 2000V
ESD Susceptibility Machine model(5) 200V
Junction Temperature 150°C
Thermal Resistance θJA 60°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the GND pin, unless otherwise specified.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower.
(4) Human body model, 100pF discharged through a 1.5kΩresistor.
(5) Machine Model, 220pF – 240pF discharged through all pins.
Operating Ratings
Temperature Range
TMIN ≤TA≤TMAX −40°C ≤TA≤85°C
DVDD 2.6V ≤DVDD ≤5.0V
Supply Voltage AVDD 2.6V ≤AVDD ≤5.5V
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Electrical Characteristics DVDD = 3.0V, AVDD = 5.0V, RL= 32Ω(1)(2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA= 25°C.
LM4921 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(5)
DVDD Digital Power Supply Voltage See (6) 3.0 V
AVDD Analog Power Supply Voltage See (6) 5.0 V
DIDD Digital Power Supply Quiescent RLoad =∞, fMLCK = 11.2896MHz 3.5 7.5 mA (max)
Current
AIDD Analog Power Supply Quiescent RLoad =∞, fMCLK = 0MHz 6 10 mA (max)
Current
ISD Total Shutdown Power Supply SHUTDOWN SPI bits 1 & 2 set to
Current logic 0, 1 5 uA(max)
SPI, MCLK and I2S inputs at GND
ISB Standby Current Analog and Digital together 25 uA
All clocks off
VFS Full-Scale Output Voltage Gain set at max 3.5 VP-P
THD+N Total Harmonic Distortion + Noise fIN = 1kHz, POUT = 12mW
(Vol Control = 11111, I2S input adj to 0.03 %
get 12mW at output)
POHeadphone Amplifier Output Power THD = (0.5%), fOUT = 1kHz 50 40 mW (min)
AVDD CBYPASS = 2.0µF
PSRR Power Supply Rejection Ratio 62 45 dB (min)
VRIPPLE = 200mVP-P 217Hz
SNR Signal-to-Noise Ratio fIN = 1kHz sinewave at -60dBFS, 82 dB
A-weighted-fCONV = 44.1kHz
DR Dynamic Range fIN = 1kHz sinewave at -60dBFS, 84 dB
A-weighted
ΔACH-CH Channel-to-Channel Gain Mismatch fIN = 1kHz 0.06 dB
XTALK Channel-to-Channel Crosstalk fCONV = 44.1kHz, 72 dB
fIN = 1kHz sinewave at -3dBFS
Volume Control Range Minimum Attenuation +3.0 dB
Maximum Attenuation -43.5 dB
Volume Control Control Step Size 1.5 dB
Mute Attenuation -102 dB
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the GND pin, unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(6) Best operation is achieved by maintaining 3.0V ≤AVDD ≤5.0V and 3.0V ≤DVDD ≤5.0V.
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Electrical Characteristics DVDD = 3.0V, AVDD = 3.0V, RL= 32Ω(1)(2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA= 25°C.
LM4921 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(5)
DVDD Digital Power Supply Voltage See (6) 3.0 V
AVDD Analog Power Supply Voltage See (6) 3.0 V
DIDD Digital Power Supply Quiescent RLoad =∞, fMLCK = 11.2896MHz 3.5 7.5 mA (max)
Current
AIDD Analog Power Supply Quiescent RLoad =∞, fMCLK = 0MHz 5 9.0 mA (max)
Current
ISD Total Shutdown Power Supply SHUTDOWN SPI bits 1 & 2 set to
Current logic 0, 1 uA(max)
SPI, MCLK and I2S inputs at GND
ISB Standby Current Analog and Digital together 15 uA
All clocks off
VFS Full-Scale Output Voltage Gain set at max 2.6 VP-P
THD+N Total Harmonic Distortion + Noise fIN = 1kHz, POUT = 12mW
(Vol Cont = 11011, I2S input adj to 0.05 %
get 12mW at output)
POHeadphone Amplifier Output Power THD = (0.5%), fOUT = 1kHz 26 mW (min)
AVDD CBYPASS = 2.0µF
PSRR Power Supply Rejection Ratio 52 dB (min)
VRIPPLE = 200mVP-P 217Hz
SNR Signal-to-Noise Ratio fIN = 1kHz sinewave at -60dBFS, 79 dB
A-weighted-fCONV = 44.1kHz
DR Dynamic Range fIN = 1kHz sinewave at -60dBFS, 81 dB
A-weighted
ΔACH-CH Channel-to-Channel Gain Mismatch fIN = 1kHz 0.06 dB
XTALK Channel-to-Channel Crosstalk fCONV = 44.1kHz, 72 dB
fIN = 1kHz sinewave at -3dBFS
Volume Control Range Minimum Attenuation 0 dB
Maximum Attenuation -43.5 dB
Volume Control Control Step Size 1.5 dB
Mute Attenuation -100 dB
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the GND pin, unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(6) Best operation is achieved by maintaining 3.0V ≤AVDD ≤5.0V and 3.0V ≤DVDD ≤5.0V.
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LM4921
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Electrical Characteristics-Digital Inputs DVDD = 3.0V(1)(2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA= 25°C.
LM4921 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(5)
Resolution 16 Bits
I2S Audio Data Interface Format Standard, I2S, Left Justified
fMCLK Master Clock Frequency 11.2896 MHz
(256FS)
fCONV Sampling Clock Frequency Range 44.1 48 kHz
VIL Digital Input: Logic Low Voltage 0.3 X DVDD V (max)
Level
VIH Digital Input: Logic High Voltage 0.7 X DVDD V (min)
Level
tES SPI_ENB Setup Time 20 ns (min)
tEH SPI_ENB Hold Time 20 ns (min)
tEL SPI_ENB Low Time 30 ns (min)
tDS SPI_Data Setup Time 20 ns (min)
tDH SPI_Data Hold Time 20 ns (min)
tCS SPI_CLK Setup Time 20 ns (min)
tCH SPI_CLK High Pulse Width 100 ns (min)
tCL SPI_CLK Low Pulse Width 100 ns (min)
fCLK SPI_CLK Frequency 5 MHz (max)
tCLKI2SI2S_CLK Period 50 ns (min)
tHII2SI2S_CLK High Pulse Width 20 ns (min)
I2S_CLK Low Pulse Width 20 ns (min)
tLOI2SI2S_LRCLK Duty Cycle 50 %
tSLRCLK I2S_LRCLK to I2S_CLK Setup Time 20 ns (min)
tHLRCLK I2S_LRCLK to I2S_CLK Hold Time 20 ns (min)
tSDI2SI2S_Data to I2S_CLK Setup Time 20 ns (min)
tHDI2SI2S_Data to I2S_CLK Hold Time 20 ns (min)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the GND pin, unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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20 100 1k 10k 20k
.01
.1
1.0
10
TOTAL HARMONIC DISTORTION (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
.01
.1
1.0
10
TOTAL HARMONIC DISTORTION (%)
FREQUENCY (Hz)
1m 10m 20m 100m
.01
.1
1.0
10
TOTAL HARMONIC DISTORTION (%)
POWER (W)
50m5m
20 100 1k 10k 20k
.01
.1
1.0
10
TOTAL HARMONIC DISTORTION (%)
FREQUENCY (Hz)
10
1m 10m 20m 100m
.01
.1
1.0
TOTAL HARMONIC DISTORTION (%)
POWER (W)
50m5m
1m 10m 20m 100m
.01
.1
1.0
10
TOTAL HARMONIC DISTORTION (%)
POWER (W)
50m5m
LM4921
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SNAS178E –JULY 2003–REVISED MAY 2013
Typical Performance Characteristics
THD+N vs Output Power THD+N vs Output Power
1. Analog VDD = 5V, Digital VDD = 3V Analog VDD = 3V, Digital VDD = 3V
RL= 32Ω, 44.1 kHz Sample Rate RL= 32Ω, 44.1 kHz Sample Rate R & L Channels Shown
R & L Channels, Vol = 3dB, Frequency in = 1kHz Vol = 3dB, Frequency in = 1kHz
Figure 3. Figure 4.
THD+N vs Output Power THD+N vs Frequency
Analog VDD = 2.6V, Digital VDD = 2.6V Analog VDD = 5V, Digital VDD = 3V
RL= 32Ω, 4.1 kHz Sample Rate RL= 32Ω, Power Level = 50mW,
R & L Channels Shown, Vol = 3dB, Frequency in = 1kHz R & L Channels Shown , 44.1kHz Sample Rate
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
Analog VDD = 2.6V, Digital VDD = 2.6V
Analog VDD = 3V, Digital VDD = 3V RL= 32Ω, Power Level = 12mW
RL= 32Ω, Power Level = 12mW R & L Channels Shown, 44.1kHz Sample Rate
R & L Channels Shown, 44.1kHz Sample Rate
Figure 7. Figure 8.
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20 100 1k 10k 20k
-130
-100
-60
-40
0
AMPLITUDE (dB)
FREQUENCY (Hz)
-80
-20
20 100 1k 10k 20k
-130
-100
-60
-40
0
AMPLITUDE (dB)
FREQUENCY (Hz)
-80
-20
-90 -70 -40 -10 0
-100
-80
-40
-20
10
ANALOG OUTPUT SIGNAL AMPLITUDE (dB)
-60
0
-20-30-50
-60
-80
DIGITAL INPUT SIGNAL AMPLITUDE (dB)
-90 -70 -40 -10 0
-100
-80
-40
-20
10
ANALOG OUTPUT SIGNAL AMPLITUDE (dB)
-60
0
-20-30-50
-60
-80
DIGITAL INPUT SIGNAL AMPLITUDE (Db)
20 100 1k 10k 20k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
CROSSTALK (dB)
FREQUENCY (Hz)
20 100 1k 10k 20k
-100
-80
-60
-20
10
AMPLITUDE (dB)
FREQUENCY (Hz)
0
-40
LM4921
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Typical Performance Characteristics (continued)
Crosstalk Frequency Response
Analog VDD = 5V, Digital VDD = 3V
Analog VDD = 3V, Digital VDD = 3V RL = 32Ω, Vol = 0dB
RL = 32Ω, Vol = 3dB 44.1kHz Sample Rate, 0dB FFS
44.1kHz Sample Rate, -3dB FFSFigure 9. Figure 10.
Linearity Linearity
Analog VDD = 5V, Digital VDD = 3V Analog VDD = 3V, Digital VDD = 3V
RL= 32Ω, 44.1kHz Sample Rate RL= 32Ω, 44.1kHz Sample Rate
Figure 11. Figure 12.
Noise Floor Noise Floor
Analog VDD = 5V, Digital VDD = 3V Analog VDD = 3V, Digital VDD = 3V
RL= 32Ω, Vol = 3dB RL= 32Ω, Vol = 0dB
44.1kHz Sample Rate 44.1kHz Sample Rate
Figure 13. Figure 14.
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20 100 1k 10k 20k
-130
-100
-80
-40
0
AMPLITUDE (dB)
FREQUENCY (Hz)
-20
-60
20 100 1k 10k 20k
-130
-100
-70
-40
0
AMPLITUDE (dB)
FREQUENCY (Hz)
20 100 1k 10k 20k
-130
-100
-80
-40
0
AMPLITUDE (dB)
FREQUENCY (Hz)
-60
-20
20 100 1k 10k 20k
-130
-100
-70
-40
0
AMPLITUDE (dB)
FREQUENCY (Hz)
20 100 1k 10k 20k
-100
-80
-40
-20
0
AMPLITUDE (dB)
FREQUENCY (HZ)
-60
20 100 1k 10k 20k
-100
-80
-40
-20
0
AMPLITUDE (dB)
FREQUENCY (Hz)
-60
LM4921
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Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
Analog VDD = 5V, Digital VDD = 3V Analog VDD = 3V, Digital VDD = 3V
RL= 32Ω, Vol = 3dB RL= 32Ω, Vol = 0dB
44.1kHz Sample Rate 44.1kHz Sample Rate
Figure 15. Figure 16.
FFT @ 1kHz -60dB FFT @ 1kHz 0dB
Analog VDD = 5V, Digital VDD = 3V Analog VDD = 5V, Digital VDD = 3V
RL= 32Ω, Vol = 3dB RL = 32Ω, Vol = 3dB
44.1kHz Sample Rate 44.1 kHz Sample Rate
Figure 17. Figure 18.
FFT @ 1kHz -60dB FFT @ 1kHz 0dB
Analog VDD = 3V, Digital VDD = 3V Analog VDD = 3V, Digital VDD = 3V
RL= 32Ω, Vol = 0dB RL= 32Ω, Vol = 0dB
44.1kHz Sample Rate 44.1kHz Sample Rate
Figure 19. Figure 20.
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APPLICATION INFORMATION
SPI OPERATIONAL DESCRIPTION
The serial data bits are organized into a field which contains 16 bits of data defined by Table 1. Bits 1 & 2
determine the output mode of the LM4921 as shown in Table 2. Bits 7 through 11 determine the volume level
setting as illustrated by Table 3. Bit 12 sets the Bypass capacitor charging time.
Table 1. Bit Allocation
BIT # Default Val Function Description
0 (LSB) 0 RESET_B RESET_B = 0, Resets the DAC
Must be high for the part to run.
1 0 MODE CONTROL See Table 2
2 0
3 0 MASTER/SLAVE 0 = SLAVE, 1 = MASTER
4 0 RESOLUTION 0 = 16 bit, 1 = 32 bit
5 0 RESERVED Should always be set to '1'
6 0 ZERO CROSSING SET 0 = ZXD ENABLE, 1 = ZXD DISABLE
7 0 VOLUME CONTROL See Table 3
8 0
9 0
10 0
11 0
12 0 BYP CHARGE RATE 0 = 1X, 1 = 2X
13 0 RESERVED
14 0 RESERVED
15 (MSB) 0 RESERVED Should always be set to '0'
MODE CONTROL
Sets the modes as outlined in Table 2.
Table 2. Output Mode Selection (Bits 1 & 2 above)
Output Mode # BIT 2 BIT 1 MODE
0 0 0 SD
1 0 1 STANDBY
2 1 0 MUTE
3 1 1 ACTIVE
Shutdown turns off the part completely for maximum power savings. The Standby mode turns off the clock but
still consumes more power than the shutdown mode. However, coming out of standby mode allows the part to
turn back on faster than from shutdown. In Mute mode the clocks remain on which uses more power but allows
faster recovery and the ability to supply clock signals to other devices which is important when the part is used in
master mode. Active mode turns the part on for normal operation.
MASTER/SLAVE SELECT
Allows the part to act as a master and supply the clock for the rest of the system or be a slave to the system
clock.
RESOLUTION SET
Sets the resolution to be either 16 or 32 bits of stereo audio information. For most applications this will be set at
16 bits.
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ZERO CROSSING DETECT SET
This pin turns on the zero crossing detection circuit. With this circuit enabled the part will not allow a volume step
change, or shutdown mode, or standby mode to occur until the audio input signal passes through zero. This pin
should be set to on for most applications.
VOLUME CONTROL
The internal Stereo Volume Control is set by changing bits 7 through 11 in the SPI interface, as shown in Table 3
below. The zero dB setting is for 3V VDD operation and the +3dB is for 5V VDD.
Table 3. Volume Control Settings
Gain (dB) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
HP_L & HP_R
-43.5 0 0 0 0 0
-42.0 0 0 0 0 1
-40.5 0 0 0 1 0
-39.0 0 0 0 1 1
-37.5 0 0 1 0 0
-36.0 0 0 1 0 1
-34.5 0 0 1 1 0
-33.0 0 0 1 1 1
-31.5 0 1 0 0 0
-30.0 0 1 0 0 1
-28.5 0 1 0 1 0
-27.0 0 1 0 1 1
-25.5 0 1 1 0 0
-24.0 0 1 1 0 1
-22.5 0 1 1 1 0
-21.0 0 1 1 1 1
-19.5 1 0 0 0 0
-18.0 1 0 0 0 1
-16.5 1 0 0 1 0
-15.0 1 0 0 1 1
-13.5 1 0 1 0 0
-12.0 1 0 1 0 1
-10.5 1 0 1 1 0
-9.0 1 0 1 1 1
-7.5 1 1 0 0 0
-6.0 1 1 0 0 1
-4.5 1 1 0 1 0
-3.0 1 1 0 1 1
-1.5 1 1 1 0 0
0.0 1 1 1 0 1
1.5 1 1 1 1 0
3.0 1 1 1 1 1
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BYPASS CHARGE RATE BIT 12
This control pin allows the user to change the Bypass Capacitor's charge rate by a factor of two. Setting this bit
at zero will set the circuit to it's normal 1x rate. Setting the bit to High will double the charge rate and allow the
part to turn on faster with a slight degradation in turn on click/pop noise.
BITS 5, 13, 14, and 15
Bits 13, 14, and 15 are all reserve bits and must be set to low/zero/ground.
Bit 5 must be set High.
SPI CONTROL INTERFACE BUS (J1)
SPI DATA: This is the serial data pin.
SPI CLK: This is the clock input pin.
SPI ENABLE: This is the SPI enable pin.
SPI TIMING DIAGRAM
SPI OPERATIONAL REQUIREMENTS
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (tCH ) after the rising edge of CLK, and CLK must remain logic-
low for at least 100ns (tCL ) after the falling edge of CLK.
3. Data bits are written to the DATA pin with the least significant bit (LSB) first.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 20ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 20ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5. ENABLE should be logic-high only during serial data transmission.
6. ENABLE must be logic-high at least 20ns (tES ) before the first rising edge of CLK, and ENABLE has to remain
logic-high at least 20ns (tEH ) after the sixteenth rising edge of CLK.
7. If ENABLE remains logic-low for more than 10ns before all 16 bits are transmitted then the data latch will be
aborted.
8. If ENABLE is logic-high for more than 16 CLK pulses then only the first 16 data bits will be latched and
activated at rising edge of sixteenth CLK.
9. ENABLE must remain logic-low for at least 30ns (tEL ).
10. Coincidental rising or falling edges of CLK and ENABLE are not allowed. If CLK is to be held logic-high after
the data transmission, the falling edge of CLK must occur at least 20ns (tCS ) before ENABLE transitions to logic-
high for the next set of data.
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SNAS178E –JULY 2003–REVISED MAY 2013
I2S INTERFACE BUS (J2 - See Figure 21 )
The I2S standard provides a uni-directional serial interface designed specifically for digital audio. For the
LM4921, the interface provides access to a 48kHz, 16 bit full-range stereo audio DAC. This interface uses a
three wire system of clock (I2S_CLK), data (I2S_DATA), and word select (I2S_WS, sometimes called Right/Left
Select).
A bit clock (I2S_CLK) at 32 or 64 times the sample frequency is established by the I2S system master and the
word select (I2S_WS) line is driven at a frequency equal to the sampling rate of the audio data, in this case
48kHz. The word line is registered to change on the positive edge of the bit clock. The serial data (I2S_DATA) is
sent MSB first, again registers on the positive edge of the bit clock, delayed by 1 bit clock cycle relative to the
changing of the word line (typical I2S format).
MCLK/XTAL_IN (S1 MCLK SEL - See Figure 21)
This is the input for an external Master Clock. The jumper at S1 must be removed (disconnecting the onboard
crystal from the circuit) when using an external Master Clock.
STEREO HEADPHONE OUTPUT JACK (J3 - See Figure 21)
This is the stereo headphone output. Each channel is single-ended, with 100uF DC output blocking capacitors
mounted on the demo board (C6 and C7). These capacitors are necessary to block the 1/2 VDD DC bias and
prevent it from flowing through the headphone speakers (DC current will destroy most audio speakers) while
allowing the audio ac signal to pass through. The jack features a typical stereo headphone pinout.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM4921
2
3
4
5
6
7
8
9
10
J2
1
2
3
4
5
6
J1
NC KEY
VDDD
1
2
P
1
MCLK
IN
SPI
Interface
I2S
Interface
CA
P
C2
CA
P
C1
R1
1M
S
1
MCL
K
SE
L
CRYSTA
L
Y
1
MCLK/XTAL
IN
XTAL
OUT
SPI_DAT
A
SPI_ENABL
E
SPI_CL
K
I2S_DAT
A
I2S_CL
K
I2S_WS
(LRCLK)
U1
LM4921ITL
BYPAS
S
E
2
D2
E
4
D3
E
3
C2
B
1
B
2
C4
C8
2.2 PF
C3
1 PFC4
1 PFC5
1 PF
Red Banana
Plug
Analog VDD
VDDAB
4
VDDA VDDD
VDDD
VDDXD1
C1
Red Banana
Plug
Digital VDD
Black Banana
Plug Black Banana
Plug
A
3
E
1
A
1
GND
A
GND
X
GND
D
Analo
g
Ground
Digita
l
Ground
N
C
C3
N
C
N
C
D4
N
C
N
C
A
2
N
C
1
J3
HEADPHONE
JACK
B
3
A
4
HP
L
HP
R
C7
100 PF
C6
100 PF
Left Out Test
Jack
Red Banana
Plug
Left Out Test Jack
Ground
Black Banana
Plug
Right Out Test Jack
Ground
Black Banana
Plug
Right Out Test
Jack
Red Banana
Plug
LM4921
SNAS178E –JULY 2003–REVISED MAY 2013
www.ti.com
LM4921ITL DEMO BOARD OPERATION
The LM4921ITL demo board is a complete evaluation platform (Parallel Port SPI Interface Card and control
software available), designed to give easy access to the control pins of the part and comprise all the necessary
external passive components. There are separate analog and digital supply connectors, SPI interface bus (J1)
for the control lines, I2S interface bus (J2) for full-range digital audio, stereo headphone output (J3), and an
external MCLK input (P1) for use in place of the crystal on the demoboard.
(1) Parallel Port SPI Interface Card and control software available.
Figure 21. LM4921ITL Demo Board Schematic
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SNAS178E –JULY 2003–REVISED MAY 2013
DEMO BOARD BILL OF MATERIALS
Texas Instruments Bill of Material
Analog Audio LM4921ITL20 Eval Board
Assembly Part Number: 980011973-100
Revision A
Item Part Number Part Description Qty Ref Designator
1 551011973-001 LM4921 Eval Board PCB etch 001 1
2 LM4921 ITL20 DSBGA 20 Bumps 1 U1
3 Cer Cap 22pF 50V 10%, size 1206 2 C1, C2
4 Cer Cap 0.1pF 50V 10%, size 1206 1 C4
5 Tant Cap 1µF 16V 10%, 3216 3 C3, C5, C8
6 Tant Cap 220µF 16V 10%, 7243 2 C6, C7
7 1 meg ohm 1 R1
8 Crystal 11.2896MHz 1 Y1
9 Phone Jack 3.5mm Stereo 1 J3
10 Jumper Header 1X2 2 P1, S1
11 Jumper Header 1X3 2 J1
12 Jumper Header 1X5 2 J2
13 PCB Banana Jack, 4 A GND, D GND, GND (2)
Black-Mouser 164-6218
14 PCB Banana Jack, 4 A VDD, D VDD, HP L, HP R
Red-Mouser 164-6219
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
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LM4921
SNAS178E –JULY 2003–REVISED MAY 2013
www.ti.com
DEMO BOARD ARTWORKS
Figure 22. Silkscreen Layer
Figure 23. Top Layer
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LM4921
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SNAS178E –JULY 2003–REVISED MAY 2013
Figure 24. Mid Layer 1
Figure 25. Mid Layer 2
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
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LM4921
SNAS178E –JULY 2003–REVISED MAY 2013
www.ti.com
Figure 26. Bottom Layer
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SNAS178E –JULY 2003–REVISED MAY 2013
REVISION HISTORY
Changes from Revision D (May 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 20
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM4921
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4921ITL/NOPB DSBGA YZR 20 250 178.0 8.4 2.34 2.85 0.76 4.0 8.0 Q1
LM4921ITLX/NOPB DSBGA YZR 20 3000 178.0 8.4 2.34 2.85 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4921ITL/NOPB DSBGA YZR 20 250 210.0 185.0 35.0
LM4921ITLX/NOPB DSBGA YZR 20 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
MECHANICAL DATA
YZR0020xxx
www.ti.com
TLA20XXX (Rev D)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
4215053/A 12/12
NOTES:
D: Max =
E: Max =
2.772 mm, Min =
2.238 mm, Min =
2.711 mm
2.177 mm
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