DATA SH EET
Preliminary specification
Supersedes data of 1998 Mar 27
File under Integrated Circuits, IC02
1998 Oct 15
INTEGRATED CIRCUITS
TDA8787
10-bit, 3.0 V analog-to-digital
interface for CCD cameras
1998 Oct 15 2
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
FEATURES
•Correlated Double Sampling (CDS), Automatic Gain
Control (AGC), 10-bit Analog-to-Digital Converter (ADC)
and reference regulator included
•Fully programmable via a 3-wire serial interface
•Sampling frequency up to 18 MHz
•AGC gain range of 36 dB (in steps of 0.1 dB)
•Low power consumption of only 190 mW (typ.)
•Power consumption in standby mode of 4.5 mW (typ.)
•3.0 V operation and 2.5 to 3.6 V operation for the digital
outputs
•Active control pulses polarity selectable via serial
interface
•8-bit DAC included for analog settings
•TTL compatible inputs, CMOS compatible outputs.
APPLICATIONS
•Low-power, low-voltage CCD camera systems.
GENERAL DESCRIPTION
The TDA8787 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit ADC
together with its reference voltage regulator.
AGC gain is controlled via the serial interface.
The ADC input clamp level is controlled via the serial
interface.
An additional DAC is provided for additional system
controls; its output voltage range is 1.0 V (p-p) which is
available at pin OFDOUT.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCCA analog supply voltage 2.7 3.0 3.6 V
VCCD digital supply voltage 2.7 3.0 3.6 V
VCCO digital outputs supply voltage 2.5 2.6 3.6 V
ICCA analog supply current all clamps active −55 70 mA
ICCD digital supply current −811mA
I
CCO digital outputs supply current fpix = 18 MHz; CL=20pF;
input ramp response time is 800 µs−12mA
ADCres ADC resolution −10 −bits
Vi(CDS)(p-p) maximum CDS input voltage
(peak-to-peak value) VCC = 2.85 V 650 −−mV
VCC ≥3.0 V 800 −−mV
fpix(max) maximum pixel rate 18 −−MHz
fpix(min) minimum pixel rate 5 −−MHz
DRAGC AGC dynamic range −36 −dB
Ntot(rms) total noise from CDS input to
ADC output AGC gain = 0 dB; see Fig.8 −0.25 −LSB
Ptot total power consumption VCCA =V
CCD =V
CCO =3V −190 −mW
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8787HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 ×7×1.4 mm SOT313-2
1998 Oct 15 3
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
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BLOCK DIAGRAM
Fig.1 Block diagram.
o
ok, full pagewidth
MGM541
10-bit ADC
REGULATOR
CDS CLOCK GENERATOR
PRE-
BLANKING OUTPUT
BUFFER
26
27
28
29
30
31
32
33
34
35
36
37
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
25 VCCO
44 DCLPC
38 VCCD2
39 DGND2
19 VCCD1
20 DGND1
41
AGND3
42
VCCA3
8
CPCDS2
7
CPCDS1
4
IN
5
AGND1
9
OFDOUT
6
VCCA1
OE
11
PBK
40
CLK
43
AGND5
17
AGND2
2
DGND3
1
VCCD3
18
VCCA2
12
CLPDM
13
CLPOB
47
SHP
SHIFTERSHIFT
COMPARATOR
CORRELATED
DOUBLE
SAMPLING
7-BIT
REGISTER
9-BIT
REGISTER
8-BIT
REGISTER
46
45
OAGC OAGCC
16
15
14 3
TEST1 AGND4
TEST2 TEST3
48
SHD
SERIAL
INTERFACE
21
22
23
SEN SCLK SDATA
24
VSYNC
10
STDBY
AGC
DAC
CLAMP
Vref
OFD DAC
DATA
FLIP-
FLOP
CLAMP
TDA8787
1998 Oct 15 4
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
PINNING
SYMBOL PIN DESCRIPTION
VCCD3 1 digital supply voltage 3
DGND3 2 digital ground 3
AGND4 3 analog ground 4
IN 4 input signal from CCD
AGND1 5 analog ground 1
VCCA1 6 analog supply voltage 1
CPCDS1 7 clamp storage capacitor pin 1
CPCDS2 8 clamp storage capacitor pin 2
OFDOUT 9 analog output of the additional 8-bit control DAC
STDBY 10 standby mode control input (LOW: TDA8787 active; HIGH: TDA8787 standby)
PBK 11 pre-blanking control input
CLPDM 12 clamp pulse input at dummy pixel
CLPOB 13 clamp pulse input at optical black
TEST1 14 test pin input 1 (should be connected to AGND2)
TEST2 15 test pin input 2 (should be connected to AGND1)
TEST3 16 test pin input 3 (should be connected to AGND2)
AGND2 17 analog ground 2
VCCA2 18 analog supply voltage 2
VCCD1 19 digital supply voltage 1
DGND1 20 digital ground 1
SDATA 21 serial data input for serial interface control
SCLK 22 serial clock input for serial interface
SEN 23 strobe pin for serial interface
VSYNC 24 vertical sync pulse input
VCCO 25 output supply voltage
OGND 26 digital output ground
D0 27 ADC digital output 0 (LSB)
D1 28 ADC digital output 1
D2 29 ADC digital output 2
D3 30 ADC digital output 3
D4 31 ADC digital output 4
D5 32 ADC digital output 5
D6 33 ADC digital output 6
D7 34 ADC digital output 7
D8 35 ADC digital output 8
D9 36 ADC digital output 9 (MSB)
OE 37 output enable control input (LOW: outputs active; HIGH: outputs in high impedance)
VCCD2 38 digital supply 2
DGND2 39 digital ground 2
CLK 40 data clock input
1998 Oct 15 5
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
AGND3 41 analog ground 3
VCCA3 42 analog supply 3
AGND5 43 analog ground 5
DCLPC 44 regulator decoupling pin
OAGC 45 AGC output (test pin)
OAGCC 46 AGC complementary output (test pin)
SHP 47 preset sample-and-hold pulse input
SHD 48 data sample-and-hold pulse input
SYMBOL PIN DESCRIPTION
Fig.2 Pin configuration.
1
2
3
4
5
6
7
8
9
10
11
36
35
34
33
32
31
30
29
28
27
26
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
12
24 37
25
TDA8787
MGM542
D9
D8
D7
D6
D4
D3
D2
D1
D0
OGND
VCCO
VCCD3
DGND3
AGND4
IN
AGND1
VCCA1
CPCDS2
OFDOUT
PBK
CLPDM
D5
SHP
OAGCC
OAGC
DCLPC
AGND5
VCCA3
CLK
DGND2
OE
VCCD2
SHD
AGND3
CPCDS1
STDBY
TEST1
TEST2
TEST3
AGND2
VCCA2
VCCD1
DGND1
SCLK
SEN
VSYNC
CLPOB
SDATA
1998 Oct 15 6
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCCA analog supply voltage note 1 −0.3 +7.0 V
VCCD digital supply voltage note 1 −0.3 +7.0 V
VCCO output stages supply voltage note 1 −0.3 +7.0 V
∆VCC supply voltage difference
between VCCA and VCCD −1.0 +1.0 V
between VCCA and VCCO −1.0 +1.0 V
between VCCD and VCCO −1.0 +1.0 V
Viinput voltage referenced to AGND −0.3 +7.0 V
Iodata output current −±10 mA
Tstg storage temperature −55 +150 °C
Tamb operating ambient temperature −20 +75 °C
Tjjunction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 76 K/W
1998 Oct 15 7
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
CHARACTERISTICS
VCCA =V
CCD = 3.0 V; VCCO = 2.6 V; fpix = 18 MHz; Tamb =25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VCCA analog supply voltage 2.7 3.0 3.6 V
VCCD digital supply voltage 2.7 3.0 3.6 V
VCCO digital outputs supply
voltage 2.5 2.6 3.6 V
ICCA analog supply current all clamps active −55 70 mA
ICCD digital supply current −811mA
I
CCO digital outputs supply
current CL= 20 pF on all data
outputs; input ramp
frequency
−12mA
Digital inputs
INPUTS: SHP, SHD, STDBY, CLPDM, CLPOB, SCLK, SDATA, SEN, VSYNC, OE AND PBK
VIL LOW-level input voltage 0 −0.6 V
VIH HIGH-level input voltage 2.2 −VCCD V
Iiinput current 0 ≤Vi≤VCCD −2−+2 µA
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp) clamp active pulse width
in number of pixels AGC code = 383 for
maximum 4 LSB error 18 −−pixels
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS) CDS input clamp
transconductance 1.5 2.7 3.5 mS
OPTICAL BLACK CLAMP (DRIVEN BY CLPOB)
Gshift gain from CPCDS1 and 2
to AGC inputs −0.27 −−
I
LSB(cp) charge pump current for
±1 LSB error at ADC
output
AGC code = 0 −±350 −µA
AGC code = 383 −±10 −µA
I
push(cp) available push current of
the charge pump −650 −µA
I
pull(cp) available pull current of
the charge pump −−650 −µA
1998 Oct 15 8
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
Correlated Double Sampling (CDS)
Vi(CDS)(p-p) maximum peak-to-peak
CDS input amplitude
(video signal)
VCC = 2.85 V 650 −−mV
VCC ≥3.0 V 800 −−mV
Vreset(max) maximum CDS input reset
pulse amplitude 500 −−mV
Ii(IN) input current into pin IN
(pin 4) at floating gate level −1−+1 µA
tCDS(min) CDS control pulses
minimum active time video input = Vi(CDS)(p-p);
2 LSB error at ADC output 11 15 −ns
th(IN-SHP) CDS input hold time
(pin IN) compared to
control pulse SHP
VCCA =V
CCD =30V;
T
amb =25°C; see Fig.9 35 7ns
t
h(IN-SHD) CDS input hold time
(pin IN) compared to
control pulse SHD
VCCA =V
CCD =30V;
T
amb =25°C; see Fig.9 35 7ns
Amplifier
DRAGC AGC dynamic range −36 −dB
∆GAGC maximum AGC gain step −0.3 −+0.3 dB
Analog-to-Digital Converter (ADC)
LEiintegral linearity error fpix = 18 MHz; ramp input −±1.3 ±2.5 LSB
LEddifferential linearity error fpix = 18 MHz; ramp input −±0.5 ±0.9 LSB
Total chain characteristics (CDS + AGC + ADC)
fpix(max) maximum pixel frequency 18 −−MHz
tCLKH CLK pulse width HIGH 15 −−ns
tCLKL CLK pulse width LOW 15 −−ns
td(SHD-CLK) time delay between
SHD and CLK see Fig.9 10 −−ns
tsu(PBK-CLK) set-up time of PBK
compared to CLK 10 −−ns
Vi(IN) video input dynamic signal
for ADC full-scale output AGC code = 00 800 −−mV
AGC code = 383 12.7 −−mV
Ntot(rms) total output noise (RMS
value) see Fig.8
AGC gain=0dB −0.25 −LSB
AGC gain=9dB −0.8 −LSB
OCCD(max) maximum offset between
CCD floating level and
CCD dark pixel level
−70 −+70 mV
Vn(i)(eq)(rms) equivalent input noise
voltage (RMS value) −110 −µV
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1998 Oct 15 9
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control
DAC (OFD) output voltage
(peak-to-peak value)
Ri=1MΩ−1.0 −V
VOFDOUT(0) DC output voltage for
code 0 −AGND −V
VOFDOUT(255) DC output voltage for
code 255 −AGND + 1.0 −V
TCDAC DAC output range
temperature coefficient −250 −ppm/°C
ZOFDOUT DAC output impedance −2000 −Ω
I
OFDOUT OFD output current drive static −− 100 µA
Digital outputs (fpix = 18 MHz; CL=22pF)
V
OH HIGH-level output voltage IOH =−1mA V
CCO −0.5 −VCCO V
VOL LOW-level output voltage IOL = 1 mA 0 −0.5 V
IOZ output current in 3-state
mode 0.5V<V
o<V
CCO −20 −+20 µA
th(o) output hold time see Fig.9 11 −−ns
td(o) output delay time CL= 22 pF; VCCO = 3.0 V −28 tbf ns
CL= 22 pF; VCCO = 2.7 V −27 tbf ns
CLoutput load capacitance −− 22 pF
Serial interface
fSCLK(max) maximum frequency of
serial interface 5−−MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1998 Oct 15 10
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
handbook, full pagewidth
N
0.6 V
2.2 V
N + 1N + 2N + 3
tCDS(min)
tCLKH
th(IN-SHP)
0.6 V
0.6 V 0.6 V
0.6 V
th(IN-SHD)
0.6 V
2.2 V
2.2 V
tCDS(min)
td(SHD-CLK)
tsu(PBK-CLK)
2.2 V
MGM764
IN
SHP
SHD
CLK
SDATA
PBK
th(o) td(o)
N − 1 N
50%
1998 Oct 15 11
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
handbook, full pagewidth
N
2.2 V
2.2 V
N + 1N + 2N + 3
tCDS(min)
tCLKL
th(IN-SHP)
0.6 V
0.6 V
0.6 V
th(IN-SHD)
0.6 V
2.2 V
tCDS(min)
td(SHD-CLK)
tsu(PBK-CLK)
2.2 V
2.2 V 2.2 V
FCE088
IN
SHP
SHD
CLK
SDATA
PBK
th(o) td(o)
N − 1 N
50%
Fig.5 DAC voltage output as a function of DAC input code.
handbook, full pagewidth
MGM543
0
OFDOUT DAC
voltage
output
(V)
1.0
0255
OFDOUT control DAC input code
1998 Oct 15 12
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
(1) In case the number of clamp pixels is limited to 18tW(clamp); otherwise this timing interval can be smaller.
(2) When dummy pixels are not available.
Fig.6 Line frequency timing diagram.
handbook, full pagewidth
MGM544
CLPDM
(active HIGH)
PBK
(active HIGH)
CLPOB
(active HIGH)
AGCOUT
4 pixels(1)
VIDEO OPTICAL BLACK
CLPOB
WINDOW
HORIZONTAL FLYBACK DUMMY VIDEO
PBK window
4 pixels(1)
CLPDM
WINDOW
(2)
Fig.7 AGC gain as a function of AGC input code.
handbook, halfpage
0 64 192 320
AGC input code
128
AGC
gain
(dB)
256 384
42
30
6
−6
0
12
24
36
18
FCE057
1998 Oct 15 13
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
Fig.8 Total noise performance as a function of AGC gain.
Noise measurement at ADC outputs:
Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 18 Mpixels with line of 1024 pixels
whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this,
the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account as no signal is inputted.
handbook, halfpage
640 192 320128 AGC code
256 383
FCE098
Ntot(rms)
(LSB)
10
8
6
4
2
0
1998 Oct 15 14
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
Fig.9 Serial interface block diagram.
handbook, full pagewidth
OFDOUT DAC
LATCHES AGC GAIN
LATCHES ADC CLAMP
LATCHES
CONTROL PULSE
POLARITY
LATCHES
LATCH
SELECTION
D0
LSB MSB
SDATA
SCLK
SEN
8-bit DAC
MGM546
AGC control ADC clamp
control control pulses
polarity settings
D1 D2 D3 D4 D5
10
D6
SHIFT REGISTER
D7 D8 D9 A0 A1
8 9 7 6
Fig.10 Loading sequence of control input data via the serial interface.
tsu1 =t
su2 =t
su3 = 10 ns (min.); thd3 =t
hd4 = 10 ns (min.).
handbook, full pagewidth
MGM547
SDATA
SCLK
SEN
A1 A0 D9 D7 D6 D5 D4 D3
MSB LSB
D2 D1 D0
thd3
tsu3
tsu1
thd4
tsu2
D8
1998 Oct 15 15
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
Table 1 Serial interface programming
Table 2 Polarity settings
Note
1. Bit D4 is not used.
Table 3 Standby selection
ADDRESS BITS DATA BITS D9 TO D0
A1 A0
0 0 AGC gain control (D8 to D0); bit D9 should be set to logic 0
0 1 DAC OFDOUT output control (D7 to D0); bits D8 and D9 should be set to logic 0
1 0 ADC clamp reference control (D6 to D0); bits D7, D8 and D9 should be set to logic 0
1 1 control pulses (pins SHP, SHD, CLPDM, CLPOB, PBK and CLK) polarity settings
SYMBOL PIN SERIAL CONTROL BIT(1) ACTIVE EDGE OR LEVEL
SHP and SHD 47 and 48 D0 1 = HIGH; 0 = LOW
CLK 40 D1 1 = rising; 0 = falling
CLPDM 12 D2 1 = HIGH; 0 = LOW
CLPOB 13 D3 1 = HIGH; 0 = LOW
PBK 11 D5 1 = HIGH; 0 = LOW
VSYNC 24 D6 0 = rising; 1 = falling
STDBY ADC DIGITAL OUTPUTS D9 TO D0 ICCA +I
CCO +I
CCD (TYP.)
1 logic state LOW 1 mA
0 active 64 mA
1998 Oct 15 16
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
APPLICATION DIAGRAM
Fig.11 Application diagram.
(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN-SHP) and th(IN-SHD) (see Chapter “Characteristics”).
handbook, full pagewidth
MGM548
1
2
3
4
5
6
7
8
9
10
11
36
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
35
34
33
32
31
30
29
28
27
26
12 25
TDA8787HL
D9
D8
D7
D6
D4
D3
D2
D1
D0
OGND
VCCO
VCCD3
DGND3
AGND4
IN
AGND1
VCCA1
CPCDS2
OFDOUT
PBK
CLPDM
D5
SHP
OAGCC
OAGC
DCLPC
AGND5
VCCA3
CLK
DGND2
OE
VCCD2
SHD
AGND3
CPCDS1
STDBY
TEST1
TEST2
TEST3
AGND2
VCCA2
VCCD1
DGND1
SCLK
SEN
VSYNC
CLPOB
SDATA
serial
interface
VCCA
VCCD
CCD(2)
VCCD
VCCD
VCCD
VCCA
100
nF
VCCD
100
nF
VCCD
100
nF
100
nF
100
nF
VCCA
100
nF
1 µF
1 µF
1 µF
1 µF
1 µF
(1)
(2) (2)
1998 Oct 15 17
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
PACKAGE OUTLINE
UNIT A
max. A1A2A3bpcE
(1) eH
E
LL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 1.60 0.20
0.05 1.45
1.35 0.25 0.27
0.17 0.18
0.12 7.1
6.9 0.5 9.15
8.85 0.95
0.55 7
0
o
o
0.12 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT313-2 94-12-19
97-08-01
D(1) (1)(1)
7.1
6.9
HD
9.15
8.85
E
Z
0.95
0.55
D
bp
e
E
B
12
D
H
bp
E
H
vMB
D
ZD
A
ZE
e
vMA
1
48
37
36 25
24
13
θ
A1
A
Lp
detail X
L
(A )
3
A2
X
y
c
wM
wM
0 2.5 5 mm
scale
pin 1 index
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
1998 Oct 15 18
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
•The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1998 Oct 15 19
Philips Semiconductors Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras TDA8787
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands 545104/750/02/pp20 Date of release: 1998 Oct 15 Document order number: 9397 750 04259
