SFH 5712
2010-03-31 3
Addressing for basic operation
I2C interface
• 1.8V IO-logic level for SDA and SCL
• IO-pins are open drain type and logic high level is set with external pull-up resistor
•SFH 5712-1/2 operates always as slave, address is 0x29 (7bits). Bit 0 is used to change between
Read (R/W bit =1) and Write mode (R/W bit =0)..
• Designed for the I2C-High Speed modes (3.4Mbit/s)
• see I2C Bus specification UM10204 from NXP for detailed information
•Spikes up to 10 ns are suppressed on SDA & SCL
Address 0x29
Bit 7 6 5 4 3 2 1 0
Address R/W bit
default 0101001X
SAddress 0x29 W
Communication from master to SFH 5712
Communication from SFH 5712 to master
W= Master writes
R = Master reads
A = acknow ledge
LS B = least significant byte
Register 0x80A A 0x03 A P
SAddress 0x29 WRegister 0x8CA A P
SAddress 0x29 RLSB DATAANA P
SAddress 0x29 WRegister 0x8DA A P
SAddress 0x29 RMSB DATAANA P
SAddress 0x29 WRegister 0x80A A 0x00 A P
NA= not acknowledge
S = START condit ion
P = STOP conditio n
MSB = most sign ificant byte
SAddress 0x29 W
Communication from master to SFH 5712
Communication from SFH 5712 to master
W= Master writes
R = Master reads
A = acknow ledge
LS B = least significant byte
Register 0x80A A 0x03 A P
SAddress 0x29 WRegister 0x8CA A P
SAddress 0x29 RLSB DATAANA P
SAddress 0x29 WRegister 0x8DA A P
SAddress 0x29 RMSB DATAANA P
SAddress 0x29 WRegister 0x80A A 0x00 A P
NA= not acknowledge
S = START condit ion
P = STOP conditio n
MSB = most sign ificant byte