TTSI144641BL-2-DB - LSI CORPORATION

Product Descri ption

February 2005

TTSI-144 Scalable Time-Slot Interchanger

Product Description

Introduction

This document is a high-level description for the

scalable time-slot interchanger (TTSI-144) device.

The features and functions of the device are listed

and explained at a level intended to meet the needs

of the system design and component selection pro-

cesses. Any standards governing the operation of

the device are referenced, and the level of compli-

ance is stated as appropriate. Broad definitions of its

intend ed app lic at ion s are give n.

Relat ed Docume nts

More information on the TTSI-144 is contained in the

following documents:

■The hardware design guide contains all information

relevant to the use of the device in a board design.

Pin descriptions, dc electrical characteristics, tim-

ing diagrams, ac timing parameters, packaging,

and operating conditions are included.

■The register description defines the address map

for the TTSI-144, and describes the purpose and

operation of each register bit, its dependencies

and initial state.

■The systems design guide describes how to design

software and hardware to support the device in

various applications. The initialization procedure

as well as some fundamental test setups for loop-

backs and pattern generation are also described.

Features

■147,456 input channels x 16,384 output channels

nonblocking DS0 time-slot interchange switch fab-

ric.

■Linearly expandable architecture that provides a

144k x 144k switch fabric with as few as nine TTSI-

144 devices.

■16 high-speed serial links (HSL) operating at an

STS-12 data rate (622.08 Mbits/s) utilizing pseudo-

SONET framing, each transporting 8,192 time slots

between TTSI-144 devices.

■64 full-dup le x, seri al tim e -div i si on mult ip lex er

(TDM) concentration highway interfaces.

■Compatible with GCI, SLD interfaces, and H.110.

■Data rate selection of 2.048 Mbits/s,

4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s per

highway.

■Bit and byte offset to 1/4 bit resolution per highway.

■Frame integrity mode to ensure intact transfer of

wideband data (N x DS0, ISDN H-channels).

■Low-latency mode for minimum delay on voice

channels.

■16-bit synchronous microprocessor interface for

access to connection data and device registers.

■16 programmable translation look-up tables allow

for real-time digital transform of TDM data. These

are selected per connection to provide fixed gain/

loss, A-law to µ-law conversion, etc.

■IEEE® 1149.1 boundary-scan test port (JTAG).

■Pattern generation and checking for on-line system

testing (pseudorandom bit sequence (PRBS), qua-

sirandom signal sequence (QRSS), or user-

defined byte).

■Low-power 1.5 V core power supply with 3.3 V dig-

ital I/O compatibility.

■388-pin ball grid array (PBGA) package, 27 mm

square with 1.0 mm ball pitch.

■–40 °C to +85 °C industrial temperature range.

22 Agere Systems Inc.

Product Description

February 2005

Product Description

TTSI-144 Scal able Time-Slot Interchanger

Applications

The TTSI-144 is suited to a wide variety of medium-to-

large sized DS0 TDM switch applications. Large

centralized or distributed switch fabrics can be

constr ucted by int er co nnec ting mul tip le TTS I- 144

devices using the HSLs. Typical applications include:

■Medium to large central office TDM switches.

■Digit al loop carriers.

■Digital cross connects.

■Remote access concentrators with voice/IP.

■Remote acce ss servers.

■Voice/IP gateways.

■Multiservice access platforms.

■Wireless switching center.

Description

The TTSI-144 time-slot interchanger is a scalable

time/space switch with DS0 granularity. The TTSI-144

receives and transmits TDM traffic via multiple

concentration highway interfaces (CHI) and multiple

high-speed serial links (HSLs). The high-speed serial

links permit the creation of large centralized or

distributed switch fabrics. Each CHI is independently

programmed, and the output CHIs support multidriver

busing. Each CHI has a programmable data rate (up to

16.384 Mbits/ s), virt u al fra me offsets, and

independently controlled transmit and receive

configurations. The TTSI-144 has internal circuitry to

ensure frame integrity. Frame integrity is a requisite

feature for applications that switch wideband data (i.e.,

N x DS0 or ISDN H-channels). Low-latency mode is

available for voice applications where reduced latency

is an advantage. The TTSI-144 is configured via a 16-

bit synchronous microprocessor interface, which is

used to control the connection data and to access

device regis te rs.

The TTSI-144 time-slot interchanger is a 144k x 16k

nonblocking time-slot (DS0) switch for use with serial

TDM data streams. The TTSI-144 comprises several

major design elements as follows: switch fabric, micro-

processor interface, receive CHI logic, transmit CHI

logic, receive HSL logic, transmit HSL logic, test pat-

tern generation and monitoring logic, translation table

lookup logic, clock and reset logic, and JTAG logic.

Figure 1 represents a high-level block diagram of the

TTSI-144.

The TTSI-144 switches DS0 data received from two

types of TDM inputs, CHIs and HSLs. The receive

CHIs are very flexible inputs that can be programmed

to interface to most serial TDM data streams. Each of

these CHIs can contain a minimum of 32 time slots at

2.048 Mbits/s to a maximum of 256 time slots at

16.384 Mbits/s.

Each of the 16 receive HSLs and 16 transmit HSLs

operate at an STS-12 data rate (622.08 Mbits/s) and

carry 8,192 time slots. The HSLs can be programmed

to broadcast either unswitched or switched TDM data.

Moreover, the high-speed serial data links allow the

TTSI-144 to be scaled linearly from a 144k x 16k switch

to a 144k x 144k switch for use in large centralized or

distributed switch fabrics.

The receive HSL and receive CHI blocks format the

TDM data for storage in the data store of the switch

fabric. The connection store in the switch fabric is

programmed with the per-time-slot connection

parameters. The switch fabric can rearrange time-slot

data in time (order within a frame) and space (among

data links).

The transmit HSL and transmit CHI blocks perform the

inverse function of the receive interface. They format

the byte-wide time-slot data for transmission on the

CHI or HSL interfaces.

The microprocessor interface provides fast access to

the device's registers and connection store. The micro-

processor interface is a 16-bit synchronous interface

compatible with most general-purpose microproces-

sors.

Agere Systems Inc. 3

Product Description

February 2005 Product Description

TTSI-144 Scalable Time-Slot Interchanger

Description (c on tin ued)

Block Diagram

Figure 1. Functional Diagram of Time-Slot Interchanger

TEST ACCESS

PORT

CLOCK

GENERATOR

CONNECTION

STORE

DATA

STORE

MICROPROCESSOR

INTERFACE

TRANSMIT

CHI

TRANSLATION

TABLE LOOKUP

TEST PATTER N

GENERATOR

TEST PATTER N

MONITOR

SWITCH

FABRIC

RECEIVE

HSL

TRANSMIT

HSL

RECEIVE

CHI

64 64

WRITE

ADDRESS

COUNTER

READ

ADDRESS

COUNTER

44 Agere Systems Inc.

Product Description

February 2005

Product Description

TTSI-144 Scal able Time-Slot Interchanger

Switch Fabric

The switch fabric performs the nonblocking switching

function. It can switch any of the 147,456 possible

incoming time slots to any of the 16,384 possible out-

going time slots. It uses the classic configuration of two

memories, one containing the traffic data and the sec-

ond containing the switching configuration. The switch

fabric performs this switching function without regard to

the physical link from which the time slot was taken;

hence, the TTSI-144 TSI is a time-space switch. Time

slots are rearranged in order within a frame (time) and

among physi c al por ts (space).

Time-slot data from the input TDM highways is con-

verted to a common-rate parallel format by the CHI

blocks. These data are written into the data store

sequentially. The write address for the address for the

data store is generated from the system clock (CHI-

CLK) and frame synchronization (FSYNC) pulse; the

clock is multiplied up to 164 MHz by a PLL in the clock

generator block so that all 147,456 input time slots can

be written into the data store during a 125 µs frame.

The entire switching operation from the input to output

CHIs is synchronous to the CHICLK and frame locked

to FSYNC.

Connections are established by programming the con-

nection store. Each time slot on the output highways

has an associated address in the connection store;

each of those locations may be programmed with the

input highway and time slot to which a connection is

required. The connection store is also used to program

all other per-time-slot options, such as frame integrity,

translation table look-up, and test pattern insertion.

The switch fabric has the ability to select one of the fol-

lowing two latency modes for each connection:

■Frame integrity. Frame integrity mode ensures

proper operation with wideband data by getting all of

the time slots in an output frame from the same input

frame.

■Low latency. Low latency mode minimizes delay for

voice applications.

The time-slot interchanger core is a memory-based

implementation consisting of a data store and a

connection store. The data store provides temporary

storage for each of the 147,456 input TDM time slots.

Received serial data is converted to parallel format,

stored sequentially in the data store, and read to output

time slots under control of data in the connection store.

The connection store contains setup information for

each of the 16,384 output time slots.

Expansion

Multiple TTSI-144s can be combined into a larger fab-

ric using the HSLs to interconnect the DS0s between

the TTSI-144 devices. The rectangular architecture of

the TTSI-144 allows linear scaling of a nonblocking

switching fabric of n (from one to nine) TTSI-144s to a

size of 144k x (n x 16k). Figure 4 on page 8 illustrates

the largest linearly scaled, nonblocking switching sys-

tem employing nine TTSI-144s. Beyond a nine

TTSI-144 switching fabric, a nonblocking architecture,

while possible, is more difficult since the number of

TTSI-144s required in the fabric increases geometri-

cally. Customers with needs for larger switching fabrics

are encouraged to contact their Agere field applications

engineer.

Table 1. Scalable Fabric Size

Although the maximum linearly scalable fabric capacity

of 144k x 144k can be achieved with as few as nine

devices, up to 17 TTSI-144 devices can be intercon-

nected using a single HSL between each pair of

devices. The HSLs provide a very efficient interconnect

scheme to support a widely distributed architecture.

Microprocessor Interface

The TTSI-144 has a versatile 16-bit microprocessor

interface that provides access to its registers and

connection store. It is designed to connect directly to

the address and data buses of a synchronous general-

purpose microprocessor and is compatible with

Motorola ®, Intel ®, and other nonmultiplexed bus

structures. The required microprocessor signals are as

follows:

■16-bit data bus (DATA[15:00]).

■16-bit address bus (ADDR[15:00]).

Fabric (Maximum DS0s) Number of TTSI-144s

16k x 16k 1*

* Recommend using the TSI-16.

32k x 32k 2

48k x 48k 3

64k x 64k 4

80k x 80k 5

96k x 96k 6

112k x 112k 7

128k x 128k 8

144k x 144k 9

Agere Systems Inc. 5

Product Description

February 2005 Product Description

TTSI-144 Scalable Time-Slot Interchanger

Microprocessor Interface (continued)

■Four control lines (chip select (CS), address strobe

(AS), read/write (R/W), and data transfer

acknowledge (DT)).

■A processor clock (MPUCLK).

■Interrupt output (INT).

The connection store and device configuration registers

are directly addressed.

The TTSI-144 generates interrupts on certain error con-

ditions—illegal address, CHI timings errors, for exam-

ple. These may all be masked individually.

Concentration Highway Interface (CHI)

The TTSI-144 transmits and receives time-slot data via

64 transmit CHIs and 64 receive CHIs, which are

single-ended serial TDM links. A programmable clock

signal and a global frame synchronization pulse signal

provide the required timing references to the CHI

interface. The TTSI-144 supports CHIs with unaligned

framing; that is, each CHI's offset from the frame

synchronization signal is independently programmable.

Although the frame offsets can be different, they must

be locked to a common frame reference. The transmit

CHIs may be placed into the high-impedance (Hi-Z)

state to allow busing of multiple drivers. Each CHI may

be independently configured for direct connection to a

variety of serial TDM interfaces operating at a variety of

data rates, including GCI, SLD, and H.110. Each CHI

supports data rates of 2.048 Mbits/s (32 time slots),

4.096 Mbits/s, 8.192 Mbits/s, and 16.384 Mbits/s (256

time slots).

The receive CHI block reformats the serial CHI input

data into a parallel format so that it can be written as

8-bit words into the data store. A 164 MHz clock is

used for those transfers. This clock is derived using an

internal phase-locked loop.

The transmit CHIs are similar in number, format, and

flexibility to the receive CHIs. A parallel-serial conver-

sion process is performed, and the time-slot data are

slowed down from the 164 MHz internal clock rate to

the required CHI output rate (2.048 Mbits/s,

4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s). The

output CH I block als o makes any time slot or bit offset

adjustments that have been programmed.

The receive CHIs are single-ended serial TDM

interfaces. The transmit CHIs can be configured as

bidirectional. In this case, the CHI receive (Rx) input is

disabled and the input CHI data comes from the

bidirectional TXD signal. The transmit drivers can be

set to a high-impedance state, and the device output

pin can be driven with input CHI data. This output

enable can be configured independently for each time

slot t o support m ultiplex ed TDM bus ar chitectur es such

as H.110. Thirty-two hot-swapable bidirectional TDM

ports can be configured for compatibility with H.110.

CHI Frame Offset Selection

TTSI-144 supports unaligned (but synchronous) TDM

data streams. Each input CHI and each output CHI has

a programmable offset ranging from 0 to virtually a full

frame. The TDM streams can be timed to align with the

connecting device rather than having to be absolutely

aligned with the TTSI-144 frame synchronization input.

See Table 2.

Table 2. Fractional Bit Offset Resolution

CHI Data Rate CHICLK Receive Offse t Resolutio n Trans m it Offset Resolu tion

2.048 Mbits/s 8.192 MHz 1/4 bit (122.1 ns) 1/4 bit (122.1 ns)

2.048 Mbits/s 16.384 MHz 1/4 bit (122.1 ns) 1/4 bit (122.1 ns)

4.096 Mbits/s 8.192 MHz 1/4 bit (61.0 ns) 1/4 bit (61.0 ns)

4.096 Mbits/s 16.384 MHz 1/4 bit (61.0 ns) 1/4 bit (61.0 ns)

8.192 Mbits/s 8.192 MHz 1/4 bit (30.5 ns) 1/2 bit (61.0 ns)

8.192 Mbits/s 16.384 MHz 1/4 bit (30.5 ns) 1/4 bit (30.5 ns)

16.384 Mbits/s 16.384 MHz 1/4 bit (15.25 ns) 1/2 bit (30.5 ns)

66 Agere Systems Inc.

Product Description

February 2005

Product Description

TTSI-144 Scal able Time-Slot Interchanger

High-Speed Serial Link (HSL)

The HSLs distribute receive DS0 data for any one

TTSI-144 device to all other sibling devices in a multi-

chip application. This allows incoming TDM streams to

terminate on a single TTSI-144 device, yet be available

to all devices for output on their respective TXDs.

The HSL provides a robust interface for high-speed

serial communication between TTSI-144 devices. This

interconnect can drive data across boards, backplanes,

or cables. With appropriate buffering, virtually any

length cable can be supported, including fiber. The

HSL provides multichannel clock/data timing recovery

with serial-to-parallel demultiplexing for inbound data

and parallel-to-serial multiplexing for outbound data.

Outbound parallel data from the switch fabric will be

inserted into pseudo-SONET frames and transmitted

over the HSLs. Inbound data from the HSLs is received

by the HSL, the framing and overhead are removed,

and the parallel data is sent to the switch fabric. The

use of pseudo-SONET framing for the high-speed

serial format provides robust framing and error

detection.

Test Pattern Generator and Monitor

The test pattern generator (TPG) and test pattern mon-

itor (TPM) are a set of selectable test logic for support

of transmission facility testing and maintenance. This

block can supply and check any one of the test pat-

terns defined in ITU-T O.150, O.151, or O.152, as well

as user-defined patterns. Any combination of DS0s can

be concatenated as a single broadband stream to test

high-speed facilities. Additionally, the TPG/TPM pro-

vides the ability to perform diagnostic tests at both the

system and device levels of operation.

System-level troubleshooting is facilitated with full

narrowband/wideband test pattern generation and

detection. Extensive device-level testing can quickly be

performed with specialized test pattern generation and

monitoring functions targeted at the CHI interfaces,

HSL interfaces, and the switch fabric itself. An effective

self-test can be performed by configuring a test path

and using the TPG/TPM and the internal loopback

capabilities of the CHIs and HSLs.

Test pattern generation and monitoring options are

configured using the connection store. Only one type of

test pattern can be transmitted at once, but it may be

concatenated on any number of channels. The test

pattern monitor may only check a single pattern on one

time slot or wideband channel.

Translation Table Look-Up Logic

The translation table look-up (TTL) logic is a set of 16

look-up tables that can optionally be inserted in the

TDM path at the output of the switch fabric. This allows

the end user to perform real-time digital transforms on

the outgoing TDM data. These look-up tables are user

programmable and are useful for various TDM related

transform functions such as µ-law to A-law conversion,

gain adjustment, or message conversion for static (i.e.,

robbed bit) signaling schemes. The various transforms

can be selected on a per-time-slot basis by program-

ming the connection store.

Delay Through the TTSI-144

For each connection written to the connection store,

the switch fabric is set to operate in low latency mode

or frame integrity mode. Low latency mode operates

with minimum delay of a DS0 byte from an input to

output time slot and is typically selected for voice

applications. Frame integrity mode ensures intact

switching of wideband data so that all the bonded time

slots in one 125 µs input frame are switched to the

same 125 µs output frame. Assuming the most

favorable conditions, the minimum switch time (first bit

in to first bit out) is two time-slot periods. The longest

delay in low latency mode is about one frame plus

three time slots. The longest delay in frame integrity

mode is about three frames plus three time slots.

Additional delay is encountered when traversing the

HSLs (3.2 µs of additional delay plus application

interconnect delay).

Agere Systems Inc. 7

Product Description

February 2005 Product Description

TTSI-144 Scalable Time-Slot Interchanger

Clocks

The TTSI-144 has three clock domains: one used for

TDM data, one used for the high-speed links, and the

third used for the microprocessor interface.

The input and output CHIs are in the TDM timing

domain. The CHICLK input, which may be 16.384 MHz

or 8.192 MHz, is the reference source for the TDM

timing. Internally, this clock is multiplied up to 164 MHz

for internal data transfer. An on-chip PLL is used for

this purpose. An 8 kHz frame synchronization pulse is

also required that must be synchronous with CHICLK.

This is used as a reference for all the time-slot

locations in the transmit and receive CHIs.

The high-speed links are in the second timing domain.

The reference clock for this domain is either CK78MHZ

or CK155MHZ[P,N] and is selected by HSLRFSEL.

Thi s clock is mul tipli ed up to 62 2.08 MHz by an inter nal

PLL.

The third timing domain is used for the microprocessor

interface. The MPUCLK input should be supplied along

with the microprocessor data, address and control sig-

nals. Typically this is available as an output on most

microprocessors, and is often referred to as the periph-

eral clock.

Typical TTSI-144 Applications

The HSLs interconnect multiple TTSI-144 devices,

allowing the creation of high capacity switch fabric in a

linear as opposed to geometric fashion. Figure 2

shows a 32k x 32k nonblocking TDM fabric comprised

of only two TTSI-144 devices. Figure 3 shows a 64k x

64k nonblocking TDM fabric comprised of only four

TTSI-144 devices. This progression can be extended

to develop a 144k x 144k nonblocking TDM fabric com-

prised of only nine TTSI-144 devices, as shown in

Figure 4.

Figure 2. 32k x 32k TSI Fabric with Two TTSI-144s

Figure 3. 64k x 64k TSI Fabric with Four TTSI-144s

TTSI-144

INPUT CHI TDM BUSES

HIGH-SPEED

SERIAL LINKS TTSI-144

OUTPUT CHI TDM BUSES

. . .

TTSI-144

INPUT C H I TDM B US E S

HIGH-SPEED

SERIAL LINKS

UTPUT CHI TDM BUSES

TTSI-144

INPUT CHI TDM BUSES

OUTPUT CHI TDM BUSE

TTSI-144

INPUT CHI TDM BUSES

UTPUT CHI TDM BUSES

TTSI-144

INPUT CHI TDM BUSES

OUTPUT CHI TDM BUSE

. . . . . .

8Agere Systems Inc.

Product Description

February 2005

Product Description

TTSI-144 Scal able Time-Slot Interchanger

Typical TTSI-144 Applications (continued)

Figure 4 shows nine TTSI-144 devices fully interconnected to form a 144k x 144k switch. All of the customer pay-

load is carried over 576 input and 576 output CHIs. The HSL interconnect mesh passes the input CHI data from

each device to all other devices.

Note: Each HSL interconnect mesh line represents two point-to-point HSLs in each direction (four total per line).

Figure 4. Combining TTSI-144s to Form Larger Switch Fabrics

TTSI-144

HSL

INTERCONNECT

64 CHIs

TTSI-14464 CHIs

TTSI-144

64 CHIs

TTSI-144

64 CHIs

TTSI-144

64 CHIs

TTSI-144

64 CHIs

TTSI-144

64 CHIs

TTSI-14464 CHIs

TTSI-144

64 CHIs

MESH

Agere Systems Inc. 9

Product Description

February 2005 Product Description

TTSI-144 Scalable Time-Slot Interchanger

Ordering Information

Device Part Number Ball Count Package Comcode

TTSI-144 TTSI144641BL-2-DB 388 PBGAM1T 700046828

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Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc.

February 2005

DS05-065STSI (Replaces DS04-212SWCH)

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

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