PRoCTM BLE: CYBL1XX7X Family Datasheet Programmable Radio-on-Chip With Bluetooth Low Energy ns General Description es ig PRoCTM BLE is a 32-bit, 48-MHz ARM(R) Cortex(R)-M0 BLE solution with CapSense(R), 12-bit ADC, four timer, counter, pulse-width modulators (TCPWM), Direct memory access (DMA), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I2S. PRoC BLE includes a royalty-free BLE stack compatible with Bluetooth(R) 4.2 and provides a complete, programmable, and flexible solution for HID, remote controls, toys, beacons, and wireless chargers. In addition to these applications, PRoC BLE provides a simple, low-cost way to add BLE connectivity to any system. Features Clock, Reset, and Supply 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz 256-KB flash memory 32-KB SRAM memory Emulated EEPROM using flash memory Watchdog timer with dedicated internal low-speed oscillator (ILO) Eight-channel direct memory access (DMA) controller Ultra-Low-Power 1.5-A Deep-Sleep mode with watch crystal oscillator (WCO) on 150-nA Hibernate mode current with SRAM retention 60-nA Stop mode current with GPIO wakeup om m CapSense(R) Touch Sensing with Two-Finger Gestures Up to 36 capacitive sensors for buttons, sliders, and touchpads One-finger gestures: finger tracking, scroll, inertial scroll, edge-swipe, click, double-click Two-finger gestures: scroll, inertial scroll, zoom-in, zoom-out Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance Automatic hardware-tuning algorithm (SmartSenseTM) ot R ec en de d Wide supply-voltage range: 1.9 V to 5.5 V 3-MHz to 48-MHz internal main oscillator (IMO) with 2% accuracy 24-MHz external clock oscillator (ECO) without load capacitance 32-kHz WCO fo r ARM Cortex-M0 CPU Core D Bluetooth 4.2 single-mode device 2.4-GHz BLE radio and baseband with integrated balun TX output power: -18 dBm to +3 dBm Received signal strength indicator (RSSI) with 1-dB resolution RX sensitivity: -92 dBm TX current: 15.6 mA at 0 dBm RX current: 16.4 mA Two serial communication blocks (SCBs) supporting I2C (Master/Slave), SPI (Master/Slave), or UART Four dedicated 16-bit TCPWMs Additional four 8-bit or two 16-bit PWMs Programmable LVD from 1.8 V to 4.5 V I2S Master interface ew N Bluetooth(R) Smart Connectivity Programmable GPIOs Programming and Debug * Easy-to-use IDE to configure, develop, program, and test a BLE application Option to export the design to Keil, IAR, or Eclipse Bluetooth Low Energy Protocol Stack Cypress Semiconductor Corporation Document Number: 001-95464 Rev. *K Operating temperature range: -40 C to +105 C Available in 56-pin QFN (7 mm x 7 mm) and 76-ball WLCSP (3.52 mm x 3.91 mm) packages PSoC(R) CreatorTM Design Environment N 12-bit, 1-Msps SAR ADC with internal reference, sample-and-hold (S/H), and channel sequencer Ultra-low-power LCD segment drive for 128 segments with operation in Deep-Sleep mode 2-pin SWD In-system flash programming support Temperature and Packaging Peripherals 36 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z, or strong output Any GPIO pin can be CapSense, LCD, or analog, with flexible pin routing 198 Champion Court Bluetooth Low Energy protocol stack supporting generic access profile (GAP) Central, Peripheral, Observer, or Broadcaster roles Switches between Central and Peripheral roles on-the-go Standard Bluetooth Low Energy profiles and services for interoperability Custom profile and service for specific use cases * San Jose, CA 95134-1709 * 408-943-2600 Revised March 27, 2017 PRoCTM BLE: CYBL1XX7X Family Datasheet More Information AN95089: PSoC 4/PRoC BLE Crystal Oscillator Selection and Tuning Techniques AN92584: Designing for Low Power and Estimating Battery Life for BLE Applications Technical Reference Manual (TRM) is in two documents: Architecture TRM details each PRoC BLE functional block Registers TRM describes each of the PRoC BLE registers Development Kits: CY8CKIT-042-BLE Pioneer Kit, is a flexible, Arduino-compatible, Bluetooth LE development kit for PSoC 4 BLE and PRoC BLE. CY5676, PRoC BLE 256KB Module, features a PRoC BLE 256KB device, two crystals for the antenna matching network, a PCB antenna and other passives, while providing access to all GPIOs of the device. CY8CKIT-142, PSoC 4 BLE Module, features a PSoC 4 BLE device, two crystals for the antenna matching network, a PCB antenna and other passives, while providing access to all GPIOs of the device. CY8CKIT-143, PSoC 4 BLE 256KB Module, features a PSoC 4 BLE 256KB device, two crystals for the antenna matching network, a PCB antenna and other passives, while providing access to all GPIOs of the device. The MiniProg3 device provides an interface for flash programming and debug. N ew D es ig ns fo r Cypress provides a wealth of data at http://www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the introduction page for Bluetooth(R) Low Energy (BLE) Products. Following is an abbreviated list for PRoC BLE: Overview: PSoC Portfolio, PSoC Roadmap Product Selectors: PSoC 1, PSoC 3, PSoC 4, PRoC BLE, PSoC 4 BLE, PSoC 5LP In addition, PSoC Creator includes a device selection tool. Application Notes: Cypress offers a large number of PSoC application notes converting a broad range of topics, from basic to advanced level. Recommended application notes for getting started with PRoC BLE are: AN94020: Getting Started with PRoC BLE AN97060: PSoC 4 BLE and PRoC BLE - Over-The-Air (OTA) Device Firmware Upgrade (DFU) Guide AN91184: PSoC 4 BLE - Designing BLE Applications AN91162: Creating a BLE Custom Profile AN91445: Antenna Design and RF Layout Guidelines AN96841: Getting Started With EZ-BLE Module AN85951: PSoC 4 CapSense Design Guide en de d PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100 pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can: 1. Drag and drop component icons to build your hardware 3. Configure components using the configuration tools system design in the main design workspace 4. Explore the library of 100+ components 2. Codesign your application firmware with the PSoC hardware, 5. Review component datasheets using the PSoC Creator IDE C compiler R ec om m Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents 1 4 N ot 2 Document Number: 001-95464 Rev. *K 3 5 Page 2 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Contents 29 30 33 33 34 36 38 40 40 41 42 42 42 42 42 42 N ew D es ig ns Memory ..................................................................... System Resources .................................................... Ordering Information...................................................... Ordering Code Definitions ......................................... Packaging........................................................................ WLCSP Compatibility ................................................ Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Revision History ............................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC(R) Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... N ot R ec om m en de d fo r Blocks and Functionality ................................................. 4 CPU Subsystem .......................................................... 5 BLE Subsystem........................................................... 5 System Resources Subsystem ................................... 6 Peripheral Blocks ........................................................ 7 Pinouts .............................................................................. 9 Power............................................................................... 14 Low-Power Modes..................................................... 14 Development Support .................................................... 16 Documentation .......................................................... 16 Online ........................................................................ 16 Tools.......................................................................... 16 Kits ............................................................................ 16 Electrical Specifications ................................................ 17 Absolute Maximum Ratings....................................... 17 BLE Subsystem......................................................... 17 Device-Level Specifications ...................................... 20 Analog Peripherals .................................................... 25 Digital Peripherals ..................................................... 26 Document Number: 001-95464 Rev. *K Page 3 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Blocks and Functionality The CYBL1XX7X block diagram is shown in Figure 2. There are five major subsystems: CPU subsystem, BLE subsystem, system resources, peripheral blocks, and I/O subsystem. CPU Subsystem P0.6 P0.7 ARM Cortex-M0 SWD FLASH 256 KB CONFIG 512 B ROM 8 KB ew System Interconnect BLE Subsystem N System Resources Power BOD LVD XRES WDT Clock Control IMO ILO WCO ECO fo r Link Layer Engine XTAL32I/P6.1 XTAL32O/P6.0 XTAL24I XTAL24O RF PHY ANT SCB0 I2C/UART/SPI GPIOs SCB1 I2C/UART/SPI GPIOs en de d XRES DMA Controller D NVIC SRAM 32 KB es ig ns Figure 2. Block Diagram Peripherals GPIOs GPIOs m 4x TCPWM GPIOs om R ec GPIOs 4x PWM Peripheral Interconnect 12-Bit SAR ADC I2S CAPSENSE GPIOs GPIOs I/O Subsystem The PSoC Creator IDE provides fully integrated programming and debug support for PRoC BLE devices. The SWD interface is fully compatible with industry-standard third-party tools. PRoC BLE also supports disabling the SWD interface and has a robust flash-protection feature. N ot The PRoC BLE family includes extensive support for programming, testing, debugging, and tracing both hardware and firmware. The complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. LCD Document Number: 001-95464 Rev. *K Page 4 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet BLE Subsystem Flash ns The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50- antenna terminal through a pi-matching network. The output power is programmable from -18 dBm to +3 dBm to optimize the current consumption for different applications. fo r The device has a 256-KB flash memory with a flash accelerator, tightly coupled to the CPU to improve average access times from flash. The flash is designed to deliver 1-wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash can be used to emulate EEPROM operation, if required. es ig The CPU also includes a 2-pin interface, the serial wire debug (SWD), which is a 2-wire form of JTAG. The debug circuits are enabled by default and can only be disabled in firmware. If disabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with the new firmware that enables debugging. In addition, it is possible to use the debug pins as GPIO too. The device has four breakpoints and two watchpoints for effective debugging. The physical layer consists of a modem and an RF transceiver that transmits and receives BLE packets at the rate of 1 Mbps over the 2.4-GHz ISM band. In the transmit direction, this block performs GFSK modulation and then converts the digital baseband signal of these BLE packets into radio frequency before transmitting them to air through an antenna. In the receive direction, this block converts an RF signal from the antenna to a digital bit stream after performing GFSK demodulation. D The CYBL1XX7X device is based on an energy-efficient ARM Cortex-M0 32-bit processor, offering low power consumption, high performance, and reduced code size using 16-bit thumb instructions. The Cortex-M0's ability to perform single-cycle 32-bit arithmetic and logic operations, including single-cycle 32-bit multiplication, helps in better performance. The inclusion of the tightly-integrated Nested Vectored Interrupt Controller (NVIC) with 32 interrupt lines enables the Cortex-M0 to achieve a low latency and a deterministic interrupt response. The BLE subsystem consists of the link layer engine and physical layer. The link layer engine supports both master and slave roles. The link layer engine implements time-critical functions such as encryption in the hardware to reduce the power consumption, and provides minimal processor intervention and a high performance. The key protocol elements, such as host control interface (HCI) and link control, are implemented in firmware. The direct test mode (DTM) is included to test the radio performance using a standard Bluetooth tester. ew CPU N CPU Subsystem en de d The Bluetooth Low Energy protocol stack uses the BLE subsystem and provides the following features: Link Layer (LL) Master and Slave roles 128-bit AES engine Encryption Low-duty-cycle advertising LE Ping LE Data Packet Length Extension (Bluetooth 4.2 feature) Link Layer Privacy (with extended scanning filter policy) (Bluetooth 4.2 feature) Bluetooth Low Energy 4.2 single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols Master and slave roles API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP L2CAP connection-oriented channel GAP features Broadcaster, Observer, Peripheral, and Central roles Security mode 1: Level 1, 2, 3, and 4 Security mode 2: Level 1 and 2 User-defined advertising data Multiple-bond support GATT features GATT client and server Supports GATT subprocedures 32-bit universally unique identifiers (UUID) Security Manager (SM) LE Secure Connections (Bluetooth 4.2 feature) Pairing methods: Just Works, Passkey Entry, Out of Band, and Numeric Comparison Authenticated man-in-the-middle (MITM) protection and data signing Supports all SIG-adopted BLE profiles m During flash erase and programming operations (the maximum erase and program time is 20 ms per row), the IMO will be set to 48 MHz for the duration of the operation. This also applies to the emulated EEPROM. System design must take this into account because peripherals operating from different IMO frequencies will be affected. If it is critical that peripherals continue to operate with no change during flash programming, always set the IMO to 48 MHz and derive the peripheral clocks by dividing down from this frequency. om SRAM The low-power 32-KB SRAM memory retains its contents even in Hibernate mode. R ec ROM The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are accessed through supervisory calls (SVC) and enable in-system programming of the flash memory. DMA N ot DMA controller provides DataWrite (DW) and Direct Memory Access (DMA). The DMA controller has following features Supports up to 8 DMA channels with two independent descriptors per channel Four levels of priority for each channel Byte, half-word (2 bytes), and word (4 bytes) transfers Three modes of operation supported for each channel Configurable interrupt generation Output trigger on completion of transfer (transfer sizes up to 65536 data elements) Document Number: 001-95464 Rev. *K Page 5 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Figure 3. Clock Control System Resources Subsystem BLE Subsystem Power The power block includes internal LDOs that supply required voltage levels for different blocks. The power system also includes POR, BOD, and LVD circuits. The POR circuit holds the device in the reset state until the power supplies have stabilized at appropriate levels and the clock is ready. The BOD circuit resets the device when the supply voltage is too low for proper device operation. The LVD circuit generates an interrupt if the supply voltage drops below a user-selectable level. Divider /2 n (n=0..3) IMO An external active-LOW reset pin (XRES) can be used to reset the device. The XRES pin has an internal pull-up resistor and, in most applications, does not require any additional pull-up resistors. The power system is described in detail in the "Power" section on page 14. Divider 0 (/16) PER0_CLK Divider 9 (/16) D EXTCLK WCO Fractional Divider 1 (/16.5) N ILO ew Fractional Divider 0 (/16.5) Clock Control PER15_CLK LFCLK External Crystal Oscillator (ECO) fo r The PRoC BLE clock control is responsible for providing clocks to all subsystems and also for switching between different clock sources without glitching. The clock control for PRoC BLE consists of the IMO and the internal low-speed oscillator (ILO). It uses the 24-MHz external crystal oscillator (ECO) and the 32-kHz WCO. In addition, an external clock may be supplied from a pin. SYSCLK es ig Prescaler ns HFCLK ECO The ECO is used as the active clock for the BLE subsystem to meet the 50-ppm clock accuracy requirement of the Bluetooth Low Energy Specification. The internal tunable load capacitor is provided to tune the crystal clock frequency. The high-accuracy ECO clock can also be used as a system clock. en de d The device has 12 dividers with 16 divider outputs. Two dividers have additional fractional division capability. The HFCLK signal is divided down, as shown in Figure 3, to generate the system clock (SYSCLK) and peripheral clock (PERx_CLK) for different peripherals. The system clock (SYSCLK) driving buses, registers, and the processor must be higher than all the other clocks in the system that are divided off HFCLK. The ECO and WCO are present in the BLE subsystem and the clock outputs are routed to the system resources. Internal Main Oscillator (IMO) om m The IMO is the primary system clock source, which can be adjusted in the range of 3 MHz to 48 MHz in steps of 1 MHz. The IMO accuracy is 2%. Internal Low-Speed Oscillator (ILO) The WCO is used as the sleep clock for the BLE subsystem to meet the 500-ppm clock accuracy requirement of the Bluetooth Low Energy Specification. The sleep clock provides accurate sleep timing and enables wakeup at specified advertisement and connection intervals. With the WCO and firmware, an accurate real-time clock (within the bounds of the 32.768-kHz crystal accuracy) can be realized. Voltage Reference The internal bandgap reference circuit with 1% accuracy provides the voltage reference for the 12-bit SAR ADC. To enable better SNRs and absolute accuracy, it will be possible to bypass the internal bandgap reference using a REF pin and to use an external reference for the SAR. Watchdog Timer (WDT) A watchdog timer is implemented in the system resources subsystem running from the ILO; this allows watchdog operations during Deep-Sleep mode and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the `Reset Cause' register. N ot R ec The ILO is a very-low-power 32-kHz oscillator, which is primarily used to generate clocks for peripheral operations in Deep-Sleep mode. The ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Watch Crystal Oscillator (WCO) Document Number: 001-95464 Rev. *K Page 6 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Peripheral Blocks 4x PWM Control Configure Registers AHB, DSI VPLUS SARMUX Data Sequencer VMINUS The hardware I2C block implements a full multimaster and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast-Mode Plus) and has flexible buffering options to reduce the interrupt overhead and latency for the CPU. The I2C function is implemented using the Cypress-provided software Component (EzI2C) that creates a mailbox address range in the memory of PRoC BLE and effectively reduces the I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-byte FIFO for receive and transmit, which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. en de d SARREF Analog Mux Bus A/B I2C mode: The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-Mode-Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIOs in open-drain modes. fo r SARADC The SCB can be configured as an I2C, UART, or SPI interface. It supports an 8-byte FIFO for receive and transmit buffers to reduce CPU intervention. A maximum of two SCBs (SCB0, SCB1) are available. N P3.0 - P3.7 SARSEQ Serial Communication Block (SCB0/SCB1) ew Figure 4. SAR ADC System Diagram ns Preceding the SAR ADC is the SARMUX, which can route external pins and internal signals (analog mux bus and temperature sensor output) to the eight internal channels of the SAR ADC. The sequencer controller (SARSEQ) is used to control the SARMUX and SAR ADC to do an automatic scan on all enabled channels without CPU intervention and for preprocessing tasks such as averaging the output data. A Cypress-supplied software driver (Component) is used to control the ADC peripheral. es ig The ADC is a 12-bit, 1-Msps SAR ADC with a built-in sample-and-hold (S/H) circuit. The ADC can operate with either an internal voltage reference or an external voltage reference. These PWMs are in addition to the TCPWMs. The PWM peripheral can be configured as 8-bit or 16-bit resolution. The PWM provides compare outputs to generate single or continuous timing and control signals in hardware. It also provides an easy method of generating complex real-time events accurately with minimal CPU intervention. A maximum of four 8-bit PWMs or two 16-bit PWMs are available. D 12-Bit SAR ADC Vrefs Ref-bypass When SCB0 is used, Serial Data (SDA) and Serial Clock (SCL) of I2C can be connected to P0.4 and P0.5, or P1.4 and P1.5, or P3.0 and P3.1. 4x Timer Counter PWM (TCPWM) Configurations for I2C are as follows: SCB1 is fully compliant with the Standard-mode (100 kHz), Fast-mode (400 kHz), and Fast-Mode-Plus (1 MHz) I2C signaling specifications when routed to GPIO pins P5.0 and P5.1, except for hot-swap capability during I2C active communication. SCB1 is compliant only with Standard mode (100 kHz) when not used with P5.0 and P5.1. SCB0 is compliant with Standard mode (100 kHz) only. m A diode based, on-chip temperature sensor is used to measure the die temperature. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using the Cypress-supplied software that includes calibration and linearization. R ec om The 16-bit TCPWM module can be used to generate the PWM output or to capture the timing of edges of input signals or to provide a timer functionality. TCPWM can also be used as a 16-bit counter that supports up, down, and up/down counting modes. N ot Rising edge, falling edge, combined rising/falling edge detection, or pass-through on all hardware input signals can be used to derive counter events. Three routed output signals are available to indicate underflow, overflow, and counter/compare match events. A maximum of four TCPWMs are available. Document Number: 001-95464 Rev. *K When SCB1 is used, SDA and SCL can be connected to P0.0 and P0.1, or P3.4 and P3.5, or P5.0 and P5.1. UART mode: This is a full-feature UART operating up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols. In addition, it supports the 9-bit multiprocessor mode, which allows addressing of peripherals connected over common RX and TX lines. The UART hardware flow control is supported to allow slow and fast devices to communicate with each other over UART without the risk of losing data. Refer to Table 4 on page 13 for possible UART connections to the GPIOs. Page 7 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet system under software control. A software Component in PSoC Creator is provided for the CapSense block to make it easy for the user. The shield voltage can be driven on another mux bus to provide liquid-tolerance capability. Driving the shield electrode in phase with the sense electrode keeps the shield capacitance from attenuating the sensed input. Inter-IC Sound Bus (I2S) The CapSense trackpad/touchpad with gestures has the following features: Supports 1-finger and 2-finger touch applications Supports up to 36 X/Y sensor inputs Includes a gesture-detection library: 1-finger touch: Finger tracking, scroll, inertial scroll, click, double-click, edge swipe 2-finger touch: Scroll, inertial scroll, zoom-in, zoom-out LCD es ig The I/O subsystem, which comprises the GPIO block, implements the following: Eight drive-strength modes: Analog input mode (input and output buffers disabled) Input only Weak pull-up with strong pull-down Weak pull-up with weak pull-down Strong pull-up with weak pull-down Strong pull-up with strong pull-down Open drain with strong pull-down Open drain with strong pull-up Port pins: 36 Input threshold select (CMOS or LVTTL) Individual control of input and output buffers (enabling/disabling) in addition to drive-strength modes Hold mode for latching the previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes) Selectable slew rates for dV/dt to improve EMI The GPIO pins P5.0 and P5.1 are overvoltage-tolerant The GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the system. fo r The LCD controller can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments providing ultra-low power consumption. The two methods used are referred to as digital correlation and PWM. I/O Subsystem D I2S operates only in the Master mode, supporting the transmitter (TX) and the receiver (RX), which have independent data byte streams. These byte streams are packed with the most significant byte first. The number of bytes used for each sample (a sample for the left or right channel) is the minimum number of bytes to hold a sample. ew Inter-IC Sound Bus S) is a serial bus interface standard used for connecting digital audio devices. The specification is from Philips(R) Semiconductor (I2S bus specification; February 1986, revised June 5, 1996). N (I2 ns SPI Mode: The SPI mode supports full Motorola(R) SPI, Texas Instruments(R) Secure Simple Pairing (SSP) (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The block supports an 8-byte FIFO for receive and transmit. Refer to Table 4 on page 13 for the possible SPI connections to the GPIOs. en de d The digital correlation method modulates the frequency and signal levels of the commons and segments to generate the highest RMS voltage across a segment to light it up or to maintain the RMS signal as zero. This method is good for STN displays but may result in reduced contrast in TN (cheaper) displays. The PWM method drives the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but provides better results in driving TN displays. om CapSense m LCD operation is supported during Deep-Sleep mode by refreshing a small display buffer (four bits; one 32-bit register per port). N ot R ec CapSense is supported on all GPIOs through a Capacitive Sigma-Delta (CSD) block, which can be connected to any GPIO through an analog mux bus. Any GPIO pin can be connected to the analog mux bus via an analog switch. The CapSense function can thus be provided on any pin or group of pins in a Document Number: 001-95464 Rev. *K Page 8 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Pinouts Table 1 shows the pin list for the CYBL1XX7X device. 1 VDDD POWER 1.71-V to 5.5-V digital supply 2 XTAL32O/P6.0 CLOCK 32.768-kHz crystal 3 XTAL32I/P6.1 CLOCK 32.768-kHz crystal or external clock input 4 XRES RESET Reset, active LOW 5 P4.0 GPIO Port 4 Pin 0, analog/digital/lcd/csd 6 P4.1 GPIO Port 4 Pin 1, analog/digital/lcd/csd 7 P5.0 GPIO Port 5 Pin 0, analog/digital/lcd/csd 8 P5.1 GPIO Port 5 Pin 1, analog/digital/lcd/csd 9 VSSD GROUND 10 VDDR POWER 1.9-V to 5.5-V radio supply Digital ground GANT1 GROUND Antenna shielding ground ANT ANTENNA Antenna pin 13 GANT2 GROUND Antenna shielding ground 14 VDDR POWER 1.9-V to 5.5-V radio supply 15 VDDR POWER 1.9-V to 5.5-V radio supply 16 XTAL24I CLOCK 24-MHz crystal or external clock input 17 XTAL24O 18 VDDR 19 P0.0 20 P0.1 21 P0.2 22 P0.3 23 VDDD 24 P0.4 25 P0.5 fo r N 11 12 24-MHz crystal 1.9-V to 5.5-V radio supply en de d CLOCK POWER GPIO Port 0 Pin 0, analog/digital/lcd/csd GPIO Port 0 Pin 1, analog/digital/lcd/csd GPIO Port 0 Pin 2, analog/digital/lcd/csd GPIO Port 0 Pin 3, analog/digital/lcd/csd m POWER 1.71-V to 5.5-V digital supply GPIO Port 0 Pin 4, analog/digital/lcd/csd Port 0 Pin 5, analog/digital/lcd/csd GPIO Port 0 Pin 6, analog/digital/lcd/csd P0.7 GPIO Port 0 Pin 7, analog/digital/lcd/csd P1.0 GPIO Port 1 Pin 0, analog/digital/lcd/csd 29 P1.1 GPIO Port 1 Pin 1, analog/digital/lcd/csd 30 P1.2 GPIO Port 1 Pin 2, analog/digital/lcd/csd 31 P1.3 GPIO Port 1 Pin 3, analog/digital/lcd/csd 32 P1.4 GPIO Port 1 Pin 4, analog/digital/lcd/csd 33 P1.5 GPIO Port 1 Pin 5, analog/digital/lcd/csd 34 P1.6 GPIO Port 1 Pin 6, analog/digital/lcd/csd 27 ot R ec 28 om GPIO P0.6 26 N Description es ig Type D Name ew Pin ns Table 1. CYBL1XX7X Pin List (QFN Package) 35 P1.7 GPIO 36 VDDA POWER 37 P2.0 GPIO Port 2 Pin 0, analog/digital/lcd/csd 38 P2.1 GPIO Port 2 Pin 1, analog/digital/lcd/csd 39 P2.2 GPIO Port 2 Pin 2, analog/digital/lcd/csd/WAKEUP 40 P2.3 GPIO Port 2 Pin 3, analog/digital/lcd/csd Document Number: 001-95464 Rev. *K Port 1 Pin 7, analog/digital/lcd/csd 1.71-V to 5.5-V analog supply Page 9 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 1. CYBL1XX7X Pin List (QFN Package) (continued) Type 41 P2.4 GPIO Port 2 Pin 4, analog/digital/lcd/csd 42 P2.5 GPIO Port 2 Pin 5, analog/digital/lcd/csd 43 P2.6 GPIO Port 2 Pin 6, analog/digital/lcd/csd 44 P2.7 GPIO Port 2 Pin 7, analog/digital/lcd/csd VREF REF 46 VDDA POWER 1.024-V reference 1.71-V to 5.5-V analog supply P3.0 GPIO Port 3 Pin 0, analog/digital/lcd/csd P3.1 GPIO Port 3 Pin 1, analog/digital/lcd/csd 49 P3.2 GPIO Port 3 Pin 2, analog/digital/lcd/csd 50 P3.3 GPIO Port 3 Pin 3, analog/digital/lcd/csd 51 P3.4 GPIO Port 3 Pin 4, analog/digital/lcd/csd 52 P3.5 GPIO Port 3 Pin 5, analog/digital/lcd/csd 53 P3.6 GPIO Port 3 Pin 6, analog/digital/lcd/csd 54 P3.7 GPIO Port 3 Pin 7, analog/digital/lcd/csd 55 VSSA GROUND 56 VCCD POWER 57 EPAD GROUND Analog ground N ew 47 48 D 45 Description ns Name es ig Pin fo r Regulated 1.8-V supply; connect to 1.3-F capacitor Ground paddle for the QFN package en de d Table 2 shows the pin list for the CYBL1XX7X device (WLCSP package). Table 2. CYBL1XX7X Pin List (WLCSP Package) Name A1 NC A2 VREF A3 VSSA A4 P3.3 A5 P3.7 A6 VSSD Type Do not connect REF 1.024-V reference GROUND GPIO GPIO Description Analog ground Port 3 Pin 3, analog/digital/lcd/csd Port 3 Pin 7, analog/digital/lcd/csd Digital ground VSSA GROUND Analog ground VCCD POWER Regulated 1.8-V supply, connect to 1-F capacitor VDDD POWER 1.71-V to 5.5-V digital supply B1 NB NO BALL No Ball B2 P2.3 GPIO B3 VSSA GROUND B4 P2.7 GPIO Port 2 Pin 7, analog/digital/lcd/csd B5 P3.4 GPIO Port 3 Pin 4, analog/digital/lcd/csd B6 P3.5 GPIO Port 3 Pin 5, analog/digital/lcd/csd Port 3 Pin 6, analog/digital/lcd/csd A8 ot R ec A9 om GROUND A7 N NC m Pin Port 2 Pin 3, analog/digital/lcd/csd Analog ground B7 P3.6 GPIO B8 XTAL32I/P6.1 CLOCK 32.768-kHz crystal or external clock input B9 XTAL32O/P6.0 CLOCK 32.768-kHz crystal C1 NC NC Do not connect C2 VSSA GROUND Analog ground Document Number: 001-95464 Rev. *K Page 10 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 2. CYBL1XX7X Pin List (WLCSP Package) (continued) C3 P2.2 GPIO Port 2 Pin 2, analog/digital/lcd/csd C4 P2.6 GPIO Port 2 Pin 6, analog/digital/lcd/csd C5 P3.0 GPIO Port 3 Pin 0, analog/digital/lcd/csd C6 P3.1 GPIO Port 3 Pin 1, analog/digital/lcd/csd C7 P3.2 GPIO Port 3 Pin 2, analog/digital/lcd/csd C8 XRES RESET C9 P4.0 GPIO D1 NC NC D2 P1.7 GPIO D3 VDDA POWER D4 P2.0 GPIO Port 2 Pin 0, analog/digital/lcd/csd D5 P2.1 GPIO Port 2 Pin 1, analog/digital/lcd/csd D6 P2.5 GPIO Port 2 Pin 5, analog/digital/lcd/csd D7 VSSD GROUND D8 P4.1 GPIO Port 4 Pin 1, analog/digital/lcd/csd D9 P5.0 GPIO Port 5 Pin 0, analog/digital/lcd/csd E1 NC NC E2 P1.2 GPIO Port 1 Pin 2, analog/digital/lcd/csd E3 P1.3 GPIO Port 1 Pin 3, analog/digital/lcd/csd E4 P1.4 GPIO Port 1 Pin 4, analog/digital/lcd/csd E5 P1.5 GPIO Port 1 Pin 5, analog/digital/lcd/csd E6 P1.6 GPIO Port 1 Pin 6, analog/digital/lcd/csd E7 P2.4 GPIO Port 2 Pin 4, analog/digital/lcd/csd E8 P5.1 GPIO Port 5 Pin 1, analog/digital/lcd/csd E9 VSSD Port 1 Pin 7, analog/digital/lcd/csd fo r Digital ground N ew 1.71-V to 5.5-V analog supply m en de d Do not connect GROUND Digital ground NC Do not connect Digital ground P0.7 GPIO Port 0 Pin 7, analog/digital/lcd/csd P0.3 GPIO Port 0 Pin 3, analog/digital/lcd/csd F5 P1.0 GPIO Port 1 Pin 0, analog/digital/lcd/csd F6 P1.1 GPIO Port 1 Pin 1, analog/digital/lcd/csd F7 VSSR GROUND Radio ground F8 VSSR GROUND Radio ground ot R ec F4 N Do not connect GROUND F3 NC Reset, active LOW Port 4 Pin 0, analog/digital/lcd/csd VSSD F2 om F1 Description ns Type es ig Name D Pin F9 VDDR POWER G1 NC NC G2 P0.6 GPIO G3 VDDD POWER 1.9-V to 5.5-V radio supply Do not connect Port 0 Pin 6, analog/digital/lcd/csd 1.71-V to 5.5-V digital supply G4 P0.2 GPIO G5 VSSD GROUND Digital ground G6 VSSR GROUND Radio ground Document Number: 001-95464 Rev. *K Port 0 Pin 2, analog/digital/lcd/csd Page 11 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 2. CYBL1XX7X Pin List (WLCSP Package) (continued) Type Description G7 VSSR GROUND Radio ground G8 GANT GROUND Antenna shielding ground G9 VSSR GROUND Radio ground H1 NC NC H2 P0.5 GPIO Port 0 Pin 5, analog/digital/lcd/csd Port 0 Pin 1, analog/digital/lcd/csd ns Name Do not connect P0.1 GPIO H4 XTAL24O CLOCK 24-MHz crystal H5 XTAL24I CLOCK 24-MHz crystal or external clock input H6 VSSR GROUND H7 VSSR GROUND Radio ground H8 ANT ANTENNA Antenna pin J1 NC NC J2 P0.4 GPIO D H3 ew Radio ground Do not connect es ig Pin N Port 0 Pin 4, analog/digital/lcd/csd P0.0 GPIO J4 VDDR POWER 1.9-V to 5.5-V radio supply Port 0 Pin 0, analog/digital/lcd/csd J7 VDDR POWER 1.9-V to 5.5-V radio supply J8 NO CONNECT - fo r J3 - en de d The I/O subsystem consists of a high-speed I/O matrix (HSIOM), which is a group of high-speed switches that routes GPIOs to the resources inside the device. These resources include CapSense, TCPWMs, I2C, SPI, UART, and LCD. HSIOM_PORT_SELx are 32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are assigned to each GPIO in the port. This provides up to 16 different options for GPIO routing as shown in Table 3. Table 3. HSIOM Port Settings Value Description Firmware-controlled GPIO 1 Reserved 2 Reserved 3 Reserved 4 Pin is a CSD sense pin 5 Pin is a CSD shield pin 6 Pin is connected to AMUXA 8 9 om Pin is connected to AMUXB Pin-specific Active function #0 Pin-specific Active function #1 Pin-specific Active function #2 ot 10 R ec 7 m 0 Reserved 12 Pin is an LCD common pin N 11 13 Pin is an LCD segment pin 14 Pin-specific Deep-Sleep function #0 15 Pin-specific Deep-Sleep function #1 Document Number: 001-95464 Rev. *K Page 12 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet The selection of peripheral functions for different GPIO pins is given in Table 4. Table 4. Port Pin Connections[1] Digital Analog GPIO Active #0 Active #1 Active #2 Deep Sleep #0 P0.0 - GPIO TCPWM0_P[3] SCB1_UART_RX[1] - SCB1_I2C_SDA[1] SCB1_SPI_MOSI[1] P0.1 - GPIO TCPWM0_N[3] SCB1_UART_TX[1] - SCB1_I2C_SCL[1] SCB1_SPI_MISO[1] P0.2 - GPIO TCPWM1_P[3] SCB1_UART_RTS[1] - - TCPWM1_N[3] SCB1_UART_CTS[1] - ns Name es ig Deep Sleep #1 SCB1_SPI_SCLK[1] - GPIO TCPWM1_P[0] SCB0_UART_RX[1] EXT_CLK[0]/ ECO_OUT[0] SCB0_I2C_SDA[1] SCB0_SPI_MOSI[1] P0.5 - GPIO TCPWM1_N[0] SCB0_UART_TX[1] - SCB0_I2C_SCL[1] SCB0_SPI_MISO[1] P0.6 - GPIO TCPWM2_P[0] SCB0_UART_RTS[1] - SWDIO[0] SCB0_SPI_SS0[1] P0.7 - GPIO TCPWM2_N[0] SCB0_UART_CTS[1] P1.0 - GPIO TCPWM0_P[1] - P1.1 - GPIO TCPWM0_N[1] - P1.2 - GPIO TCPWM1_P[1] - P1.3 - GPIO TCPWM1_N[1] P1.4 - GPIO P1.5 - P1.6 SWDCLK[0] SCB0_SPI_SCLK[1] - - WCO_OUT[2] - - SCB1_SPI_SS1 - - SCB1_SPI_SS2 - - - SCB1_SPI_SS3 TCPWM2_P[1] SCB0_UART_RX[0] - SCB0_I2C_SDA[0] SCB0_SPI_MOSI[1] GPIO TCPWM2_N[1] SCB0_UART_TX[0] - SCB0_I2C_SCL[0] SCB0_SPI_MISO[1] - GPIO TCPWM3_P[1] SCB0_UART_RTS[0] - - SCB0_SPI_SS0[1] P1.7 - GPIO TCPWM3_N[1] SCB0_UART_CTS[0] - - SCB0_SPI_SCLK[1] P2.0 - GPIO - - - - SCB0_SPI_SS1 P2.1 - GPIO - - - - SCB0_SPI_SS2 P2.2 - GPIO - - - WAKEUP SCB0_SPI_SS3 P2.3 - GPIO - - - - WCO_OUT[1] P2.4 - GPIO - - - - - - GPIO - - - - - - GPIO - - - - - - GPIO - - EXT_CLK[1]/ ECO_OUT[1] - - en de d m om P2.5 P2.6 R ec P2.7 fo r - N ew - P0.4 D SCB1_SPI_SS0[1] GPIO P0.3 SARMUX_0 GPIO TCPWM0_P[2] SCB0_UART_RX[2] - SCB0_I2C_SDA[2] - P3.1 SARMUX_1 GPIO TCPWM0_N[2] SCB0_UART_TX[2] - SCB0_I2C_SCL[2] - P3.2 SARMUX_2 GPIO TCPWM1_P[2] SCB0_UART_RTS[2] - - - P3.3 SARMUX_3 GPIO TCPWM1_N[2] SCB0_UART_CTS[2] - - - P3.4 SARMUX_4 GPIO TCPWM2_P[2] SCB1_UART_RX[2] - SCB1_I2C_SDA[2] - P3.5 SARMUX_5 GPIO TCPWM2_N[2] SCB1_UART_TX[2] - SCB1_I2C_SCL[2] - P3.6 SARMUX_6 GPIO TCPWM3_P[2] SCB1_UART_RTS[2] - - - P3.7 SARMUX_7 GPIO TCPWM3_N[2] SCB1_UART_CTS[2] - - WCO_OUT[0] P4.0 CMOD GPIO TCPWM0_P[0] SCB1_UART_RTS[0] - - SCB1_SPI_MOSI[0] N ot P3.0 Note 1. For devices with only 1 SCB, use pins corresponding to SCB1. Document Number: 001-95464 Rev. *K Page 13 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 4. Port Pin Connections[1] (continued) Digital Name Analog GPIO Active #0 Active #1 P4.1 CTANK GPIO TCPWM0_N[0] SCB1_UART_CTS[0] P5.0 - GPIO TCPWM3_P[0] SCB1_UART_RX[0] P5.1 - GPIO TCPWM3_N[0] SCB1_UART_TX[0] P6.0_XTAL32 O - GPIO - P6.1_XTAL32I - GPIO - Deep Sleep #1 - - SCB1_SPI_MISO[0] EXTPA_EN SCB1_I2C_SDA[0] SCB1_SPI_SS0[0] EXT_CLK[2]/ ECO_OUT[2] SCB1_I2C_SCL[0] SCB1_SPI_SCLK[0] - - - - - - - - ns Deep Sleep #0 D es ig Active #2 Power VDDD 0.1-F ceramic at each pin plus bulk capacitor 1-F to 10-F VDDR 0.1-F ceramic at each pin plus bulk capacitor 1-F to 10-F VCCD 1.3-F ceramic capacitor at the VCCD pin VREF (optional) m en de d Bypass capacitors must be used from VDDx (x = A, D, or R) to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-F range in parallel with a smaller capacitor (for example, 0.1 F). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design to obtain optimal bypassing. om 0.1-F ceramic at each pin plus bulk capacitor 1-F to 10-F N VDDA Bypass Capacitors ew Power Supply fo r PRoC BLE can be supplied from batteries with a voltage range of 1.9 V to 5.5 V by directly connecting to the digital supply (VDDD), analog supply (VDDA), and radio supply (VDDR) pins. The internal LDOs in the device regulate the supply voltage to required levels for different blocks. The device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation. The analog circuits run directly from the analog supply (VDDA) input. The device uses separate regulators for Deep Sleep and Hibernate modes to minimize the power consumption. The radio stops working below 1.9 V, but the rest of the system continues to function down to 1.71 V without RF. The internal bandgap may be bypassed with a 1-F to 10-F capacitor Low-Power Modes PRoC BLE supports five power modes. Refer to Table 5 for more details on the system status. The PRoC BLE device consumes the lowest current in Stop mode; the device wakeup from stop mode is with a system reset through the XRES or WAKEUP pin. It can retain the SRAM data in Hibernate mode and is capable of retaining the complete system status in Deep-Sleep mode. Table 5 shows the different power modes and the peripherals that are active. Table 5. Power Modes System Status Current Consumption Code Execution Digital Peripherals Available Analog Peripherals Available Clock Sources Available Wake Up Sources Wake-Up Time 850 A + 260 A per MHz[2] Yes All All All - - 1.1 mA at 3 MHz No All All All Any interrupt source 0 1.5 A No WDT, LCD, I2C/SPI, Link-Layer POR, BOD WCO, ILO GPIO, WDT, I2C/SPI Link Layer 25 s Hibernate 150 nA No No POR, BOD No GPIO 0.7 ms Stop 60 nA No No No No Wake-Up pin, XRES 2.2 ms Active ot Sleep R ec Power Mode N Deep Sleep Note 2. For CPU subsystem. Document Number: 001-95464 Rev. *K Page 14 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet A typical system application connection diagram for the 56-QFN package is shown in Figure 5. Figure 5. PRoC BLE Applications Diagram ns VDDA C1 1.3 uF 1.0 VDDD 1 2 L1 VDDR en de d C5 N VDDR C6 PRoC BLE 56-QFN VDDR XTAL24I XTAL24O VDDR P0.0 P0.1 P0.2 P0.3 VDDD P0.4 P0.5 P0.6 P0.7 P1.0 1 2 ANTENNA VDDD XTAL32O/P6.0 XTAL32I/P6.1 XRES P4.0 P4.1 P5.0 P5.1 VSS VDDR GANT1 ANT GANT2 VDDR fo r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32.768KHz ew 1 D EPAD VCCD VSSA P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 VDDA VREF P2.7 P2.6 Y2 2 es ig U1 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 C4 24 pF 18 pF P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 VDDA P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C3 4736 pFpF C2 1.0 uF 1 VDDD 2 N ot R ec om m 3 Y1 24MHz 4 SWDIO SWDCLK VDDR Document Number: 001-95464 Rev. *K Page 15 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Component Datasheets: PSoC Creator Components provide hardware abstraction using APIs to configure and control peripheral activity. The Component datasheet covers Component features, its usage and operation details, API description, and electrical specifications. This is the primary documentation used during development. These Components can represent peripherals on the device (such as a timer, I2C, or UART) or high-level system functions (such as the BLE Component). ns Tools With industry-standard cores, programming, and debugging interfaces, the CYBL1XX7X family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy-to-use PSoC Creator IDE, supported third-party compilers, programmers, and debuggers. Kits Cypress provides a portfolio of kits to accelerate time-to-market. Visit us at www.cypress.com/procble. N ot R ec om m en de d fo r Application Notes: Application notes help you to understand how to use various device features. They also provide guidance on how to solve a variety of system design challenges. es ig A suite of documentation supports the CYBL1XX7X family to ensure that you find answers to your questions quickly. This section contains a list of some of the key documents. In addition to the print documentation, Cypress forums connect you with fellow users and experts from around the world, 24 hours a day, 7 days a week. D Documentation Online ew The CYBL1XX7X family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/procble to find out more. Technical Reference Manual (TRM): The TRM describes all peripheral functionality in detail, with register-level descriptions. This document is divided into two parts: the Architecture TRM and the Register TRM. N Development Support Document Number: 001-95464 Rev. *K Page 16 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Exposure to absolute maximum conditions for extended periods of time may affect device reliability. This section provides detailed electrical characteristics. Absolute maximum rating for the CYBL1XX7X devices is listed in Table 6 through Table 50. Usage above the absolute maximum conditions may cause permanent damage to the device. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions, but above normal operating conditions, the device may not operate to the specification. Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Parameter Description Min Typ Max - 6 VDDD_ABS Analog, digital, or radio supply relative to VSS (VSSD = VSSA) -0.5 SID2 VCCD_ABS Direct digital core voltage input relative to VSSD -0.5 SID3 VGPIO_ABS GPIO voltage -0.5 SID4 IGPIO_ABS Maximum current per GPIO -25 - SID5 IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS -0.5 BID57 ESD_HBM Electrostatic discharge human body model 2200[3] BID58 ESD_CDM Electrostatic discharge charged device model BID61 LU Pin current for latch up Parameter Details/ Conditions V Absolute max V Absolute max 1.95 - VDD +0.5 V Absolute max 25 mA Absolute max - 0.5 mA Absolute max, current injected per pin - - V - 500 - - V - -200 - 200 mA - fo r N - Min Typ Max Units Details/ Conditions RX sensitivity with idle transmitter - -89 - dBm - RX sensitivity with idle transmitter excluding Balun loss - -91 - dBm Guaranteed by design simulation Description om Spec ID# en de d Table 7. BLE Subsystem m BLE Subsystem ew SID1 Units D Spec ID# es ig ns Electrical Specifications RF Receiver Specifications SID340 R ec SID340A RXS, IDLE RXS, DIRTY RX sensitivity with dirty transmitter - -87 -70 dBm RF-PHY Specification (RCV-LE/CA/01/C) SID342 RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter - -91 - dBm - SID343 PRXMAX Maximum input power -10 -1 - dBm RF-PHY Specification (RCV-LE/CA/06/C) CI1 Co-channel interference, Wanted signal at -67 dBm and Interferer at FRX - 9 21 dB RF-PHY Specification (RCV-LE/CA/03/C) N ot SID341 SID344 Note 3. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 001-95464 Rev. *K Page 17 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 7. BLE Subsystem (continued) Description Min Typ Max Units Details/ Conditions dB RF-PHY Specification (RCV-LE/CA/03/C) CI2 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 1 MHz - 3 15 SID346 CI3 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 2 MHz - -29 - SID347 CI4 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 3 MHz - -39 - CI5 Adjacent channel interference Wanted Signal at -67 dBm and Interferer at Image frequency (FIMAGE) - -20 - SID349 CI6 Adjacent channel interference Wanted signal at -67 dBm and Interferer at Image frequency (FIMAGE 1 MHz) - SID350 OBB1 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 30-2000 MHz -30 SID351 OBB2 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2,003-2,399 MHz SID352 OBB3 SID353 OBB4 RF-PHY Specification (RCV-LE/CA/03/C) dB RF-PHY Specification (RCV-LE/CA/03/C) D RF-PHY Specification (RCV-LE/CA/03/C) dB RF-PHY Specification (RCV-LE/CA/03/C) -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) -35 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2,484-2,997 MHz -35 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) Out-of-band blocking, Wanted signal a -67 dBm and Interferer at F = 3,000-12,750 MHz -30 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) Intermodulation performance Wanted signal at -64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel -50 - - dBm RF-PHY Specification (RCV-LE/CA/05/C) dBm 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 N - en de d -30 fo r dB IMD R ec SID354 om m SID348 dB es ig SID345 SID355 RXSE1 Receiver spurious emission 30 MHz to 1.0 GHz RXSE2 Receiver spurious emission 1.0 GHz to 12.75 GHz - - -47 dBm 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 N ot SID356 ns Parameter ew Spec ID# - - -57 RF Transmitter Specifications SID357 TXP, ACC RF power accuracy - 1 - dB - SID358 TXP, RANGE RF power control range - 20 - dB - SID359 TXP, 0 dBm Output power, 0-dB gain setting (PA7) - 0 - dBm - Document Number: 001-95464 Rev. *K Page 18 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 7. BLE Subsystem (continued) Parameter Description Min Typ Max Units Details/ Conditions - TXP, MAX Output power, maximum power setting (PA10) - 3 - dBm SID361 TXP, MIN Output power, minimum power setting (PA1) - -18 - dBm SID362 F2AVG Average frequency deviation for 10101010 pattern 185 - - SID363 F1AVG Average frequency deviation for 11110000 pattern 225 250 275 SID364 EO Eye opening = F2AVG/F1AVG 0.8 - - SID365 FTX, ACC Frequency accuracy -150 - 150 kHz RF-PHY Specification (TRM-LE/CA/06/C) SID366 FTX, MAXDR Maximum frequency drift -50 - 50 kHz RF-PHY Specification (TRM-LE/CA/06/C) SID367 FTX, INITDR Initial frequency drift -20 - 20 kHz RF-PHY Specification (TRM-LE/CA/06/C) SID368 FTX,DR Maximum drift rate -20 - 20 kHz/ 50 s RF-PHY Specification (TRM-LE/CA/06/C) SID369 IBSE1 In-band spurious emission at 2-MHz offset - - -20 dBm RF-PHY Specification (TRM-LE/CA/03/C) SID370 IBSE2 In-band spurious emission at 3-MHz offset - - -30 dBm RF-PHY Specification (TRM-LE/CA/03/C) SID371 TXSE1 Transmitter spurious emissions (average), <1.0 GHz - - -55.5 dBm FCC-15.247 SID372 TXSE2 Transmitter spurious emissions (average), >1.0 GHz - - -41.5 dBm FCC-15.247 Receive current in normal mode - 18.7 - mA - Receive current in normal mode - 16.4 - mA Receive current in high-gain mode - 21.5 - mA - es ig - kHz RF-PHY Specification (TRM-LE/CA/05/C) kHz RF-PHY Specification (TRM-LE/CA/05/C) D ew N en de d RF Current Specification ns SID360 fo r Spec ID# RF-PHY Specification (TRM-LE/CA/05/C) IRX SID373A IRX_RF SID374 IRX, HIGHGAIN SID375 ITX, 3 dBm TX current at 3-dBm setting (PA10) - 20 - mA - SID376 ITX, 0 dBm TX current at 0-dBm setting (PA7) - 16.5 - mA - R ec om m SID373 Measured at VDDR ITX_RF, 0 dBm TX current at 0-dBm setting (PA7) - 15.6 - mA Measured at VDDR SID376B ITX_RF, 0 dBm TX current at 0 dBm excluding Balun loss - 14.2 - mA Guaranteed by design simulation SID377 ITX, -3 dBm TX current at -3-dBm setting (PA4) - 15.5 - mA - SID378 ITX, -6 dBm TX current at -6-dBm setting (PA3) - 14.5 - mA - SID379 ITX, -12 dBm TX current at -12-dBm setting (PA2) - 13.2 - mA - SID380 ITX, -18 dBm TX current at -18-dBm setting (PA1) - 12.5 - mA - SID380A Iavg_1sec, 0 dBm Average current at 1-second BLE connection interval - 17.1 - A TXP: 0 dBm; 20-ppm master and slave clock accuracy N ot SID376A Document Number: 001-95464 Rev. *K Page 19 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 7. BLE Subsystem (continued) Min Typ Max Units Details/ Conditions - 6.1 - A TXP: 0 dBm; 20-ppm master and slave clock accuracy 2400 - 2482 Description Iavg_4sec, 0 dBm Average current at 4-second BLE connection interval General RF Specification ns SID380B Parameter es ig Spec ID# FREQ RF operating frequency SID382 CHBW Channel spacing - 2 - SID383 DR On-air data rate - 1000 - SID384 IDLE2TX BLE Radio Idle to BLE Radio TX transition time - 120 140 s - SID385 IDLE2RX BLE Radio Idle to BLE Radio RX transition time - 75 120 s - 5 - dB - - MHz - kbps - ew RSSI, ACC RSSI accuracy - SID387 RSSI, RES RSSI resolution - 1 - dB - SID388 RSSI, PER RSSI sample period - 6 - s - Device-Level Specifications fo r SID386 N RSSI Specification MHz D SID381 en de d All specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71-V to 5.5-V, except where noted. Table 8. DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions VDD Power supply input voltage (VDDA = VDDD = VDD) 1.8 - 5.5 V With regulator enabled SID7 VDD Power supply input voltage unregulated (VDDA = VDDD = VDD) 1.71 1.8 1.89 V Internally unregulated supply SID9 VCCD SID10 Radio supply voltage (Radio on) 1.9 - 5.5 V - Radio supply voltage (Radio off) 1.71 - 5.5 V - Digital regulator output voltage (for core logic) - 1.8 - V - Digital regulator output bypass capacitor 1 1.3 1.6 F X5R ceramic or better om VDDR VDDR R ec SID8 SID8A m SID6 CVCCD Active Mode, VDD = 1.71 V to 5.5 V IDD3 Execute from flash; CPU at 3 MHz - 2.1 - mA T = 25 C, VDD = 3.3 V SID14 IDD4 Execute from flash; CPU at 3 MHz - - - mA T = -40 C to 85 C SID15 IDD5 Execute from flash; CPU at 6 MHz - 2.5 - mA T = 25 C, VDD = 3.3 V SID16 IDD6 Execute from flash; CPU at 6 MHz - - - mA T = -40 C to 85 C SID17 IDD7 Execute from flash; CPU at 12 MHz - 4 - mA T = 25 C, VDD = 3.3 V SID18 IDD8 Execute from flash; CPU at 12 MHz - - - mA T = -40 C to 85 C SID19 IDD9 Execute from flash; CPU at 24 MHz - 7.1 - mA T = 25 C, VDD = 3.3 V N ot SID13 Document Number: 001-95464 Rev. *K Page 20 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 8. DC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions IDD10 Execute from flash; CPU at 24 MHz - - - mA T = -40 C to 85 C SID21 IDD11 Execute from flash; CPU at 48 MHz - 13.4 - mA T = 25 C, VDD = 3.3 V SID22 IDD12 Execute from flash; CPU at 48 MHz - - - mA T = -40 C to 85 C IMO on - - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz - - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz 1.5 - A T = 25 C, VDD = 3.3 V - - A T = -40 C to 85 C IDD13 Deep-Sleep Mode, VDD = 1.8 to 3.6 V IDD15 WDT with WCO on - SID26 IDD16 WDT with WCO on - Deep-Sleep Mode, VDD = 3.6 to 5.5 V IDD17 WDT with WCO on SID28 IDD18 WDT with WCO on en de d SID27 fo r SID25 N ECO on IDD14 ew Sleep Mode, VDD and VDDR = 1.9 to 5.5 V SID24 es ig SID23 D Sleep Mode, VDD = 1.8 to 5.5 V ns SID20 - - - A T = 25 C, VDD = 5 V - - - A T = -40 C to 85 C Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed) SID29 IDD19 WDT with WCO on - - - A T = 25 C SID30 IDD20 WDT with WCO on - - - A T = -40 C to 85 C - 150 - nA T = 25 C, VDD = 3.3 V - - - nA T = -40 C to 85 C GPIO and reset active - - - nA T = 25 C, VDD = 5 V GPIO and reset active - - - nA T = -40 C to 85 C Hibernate Mode, VDD = 1.8 to 3.6 V IDD27 SID38 IDD28 GPIO and reset active m SID37 GPIO and reset active SID39 IDD29 SID40 IDD30 om Hibernate Mode, VDD = 3.6 to 5.5 V R ec Hibernate Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed) SID41 IDD31 GPIO and reset active - - - nA T = 25 C SID42 IDD32 GPIO and reset active - - - nA T = -40 C to 85 C IDD33 Stop-mode current (VDD) - 20 - nA T = 25 C, VDD = 3.3 V SID44 IDD34 Stop-mode current (VDDR) - 40 -- nA T = 25 C, VDDR = 3.3 V SID45 IDD35 Stop-mode current (VDD) - - - nA T = -40 C to 85 C SID46 IDD36 Stop-mode current (VDDR) - - - nA T = -40 C to 85 C, VDDR = 1.9 V to 3.6 V Stop-mode current (VDD) - - - nA T = 25 C, VDD = 5 V ot SID43 N Stop Mode, VDD = 1.8 to 3.6 V Stop Mode, VDD = 3.6 to 5.5 V SID47 IDD37 Document Number: 001-95464 Rev. *K Page 21 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 8. DC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions IDD38 Stop-mode current (VDDR) - - - nA T = 25 C, VDDR = 5 V SID49 IDD39 Stop-mode current (VDD) - - - nA T = -40 C to 85 C SID50 IDD40 Stop-mode current (VDDR) - - - nA T = -40 C to 85 C nA T = 25 C nA T = -40 C to 85 C Stop-mode current (VDD) - - - SID52 IDD42 Stop-mode current (VDD) - - - D IDD41 Table 9. AC Specifications Description Min SID53 FCPU CPU frequency SID54 TSLEEP Wakeup from Sleep mode - SID55 TDEEPSLEEP Wakeup from Deep-Sleep mode - SID56 THIBERNATE Wakeup from Hibernate mode SID57 TSTOP Wakeup from Stop mode Table 10. GPIO DC Specifications Spec ID# Parameter Description Max Units Details/ Conditions 1.71 V VDD 5.5 V - 48 MHz 0 - s Guaranteed by characterization 25 s 24-MHz IMO. Guaranteed by characterization - fo r en de d GPIO DC Typ ew Parameter N Spec ID# es ig Stop Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed) SID51 ns SID48 - - 0.7 ms Guaranteed by characterization - - 2.2 ms Guaranteed by characterization Min Typ Max Units Details/ Conditions VIH Input voltage HIGH threshold 0.7 x VDD - - V CMOS input SID59 VIL Input voltage LOW threshold - - 0.3 x VDD V CMOS input SID60 VIH LVTTL input, VDD < 2.7 V 0.7 x VDD - - V - SID61 VIL LVTTL input, VDD < 2.7 V - - 0.3x VDD V - LVTTL input, VDD >= 2.7 V 2.0 - - V - LVTTL input, VDD >= 2.7 V - - 0.8 V - om VIH VIL R ec SID62 SID63 m SID58 VOH Output voltage HIGH level VDD -0.6 - - V IOH = 4-mA at 3.3-V VDD SID65 VOH Output voltage HIGH level VDD -0.5 - - V IOH = 1-mA at 1.8-V VDD SID66 VOL Output voltage LOW level - - 0.6 V IOL = 8-mA at 3.3-V VDD SID67 VOL Output voltage LOW level - - 0.6 V IOL = 4-mA at 1.8-V VDD SID68 VOL Output voltage LOW level - - 0.4 V IOL = 3-mA at 3.3-V VDD SID69 RPULLUP Pull-up resistor 3.5 5.6 8.5 k - SID70 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k - N ot SID64 Note 4. VIH must not exceed VDD + 0.2 V. Document Number: 001-95464 Rev. *K Page 22 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 10. GPIO DC Specifications (continued) Parameter Description Min Typ Max Units - - 2 nA IIL Input leakage current (absolute value) SID72 IIL_CTBM Input leakage on CTBm input pins - - 4 nA SID73 CIN Input capacitance - - 7 pF SID74 VHYSTTL Input hysteresis LVTTL 25 40 0.05 x VDD - - mV VHYSCMOS Input hysteresis CMOS SID76 IDIODE Current through protection diode to VDD/VSS - - 100 SID77 ITOT_GPIO Maximum total source or sink chip current - - 200 Spec ID# Parameter ew N Table 11. GPIO AC Specifications Description - - VDD > 2.7 V mV - A - mA - Details/ Conditions D SID75 25 C, VDD = 3.3 V es ig SID71 Details/ Conditions ns Spec ID# Min Typ Max Units 2 - 12 ns 3.3-V VDDD, CLOAD = 25-pF 2 - 12 ns 3.3-V VDDD, CLOAD = 25-pF TRISEF Rise time in Fast-Strong mode SID79 TFALLF Fall time in Fast-Strong mode SID80 TRISES Rise time in Slow-Strong mode 10 - 60 ns 3.3-V VDDD, CLOAD = 25-pF SID81 TFALLS Fall time in Slow-Strong mode 10 - 60 ns 3.3-V VDDD, CLOAD = 25-pF SID82 FGPIOUT1 GPIO Fout; 3.3 V VDD 5.5 V. Fast-Strong mode - - 33 MHz 90/10%, 25-pF load, 60/40 duty cycle SID83 FGPIOUT2 GPIO Fout; 1.7 VVDD 3.3 V. Fast-Strong mode - - 16.7 MHz 90/10%, 25-pF load, 60/40 duty cycle SID84 FGPIOUT3 GPIO Fout; 3.3 V VDD 5.5 V. Slow-Strong mode - - 7 MHz 90/10%, 25-pF load, 60/40 duty cycle SID85 FGPIOUT4 GPIO Fout; 1.7 V VDD 3.3 V. Slow-Strong mode - - 3.5 MHz 90/10%, 25-pF load, 60/40 duty cycle SID86 FGPIOIN GPIO input operating frequency. 1.71 V VDD 5.5 V - - 48 MHz 90/10% VIO N ot R ec om m en de d fo r SID78 Document Number: 001-95464 Rev. *K Page 23 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 12. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Description Min Typ Max Units A SID71A IIL Input leakage (absolute value). VIH > VDD - - 10 SID66A VOL Output voltage LOW level - - 0.4 SID78A TRISE_OVFS Output rise time in Fast-Strong mode 1.5 - 12 SID79A TFALL_OVFS Output fall time in Fast-Strong mode 1.5 - 12 SID80A TRISESS Output rise time in Slow-Strong mode 10 SID81A TFALLSS Output fall time in Slow-Strong mode 10 SID82A FGPIOUT1 GPIO FOUT; 3.3 V VDD 5.5 V Fast-Strong mode SID83A FGPIOUT2 GPIO FOUT; 1.71 V VDD 3.3 V Fast-Strong mode Spec ID# SID87 Parameter Description VIH Input voltage HIGH threshold 25C, VDD = 0 V, VIH = 3.0 V V IOL = 20-mA, VDD > 2.9 V ns 25-pF load, 10%-90%, VDD = 3.3-V 25-pF load, 10%-90%, VDD = 3.3-V 60 ns 25-pF load, 10%-90%, VDD = 3.3-V - 60 ns 25-pF load, 10%-90%, VDD = 3.3-V - - 24 MHz 90/10%, 25-pF load, 60/40 duty cycle - - 16 MHz 90/10%, 25-pF load, 60/40 duty cycle Min Typ Max Units 0.7 x VDDD - - V CMOS input - - 0.3 x VDDD V CMOS input 3.5 5.6 8.5 k ew D ns N - fo r Table 13. XRES DC Specifications en de d XRES Details/ Conditions ns Parameter es ig Spec ID# Details/ Conditions VIL Input voltage LOW threshold RPULLUP Pull-up resistor SID90 CIN Input capacitance - 3 - pF - SID91 VHYSXRES Input voltage hysteresis - 100 - mV - SID92 IDIODE Current through protection diode to VDD/VSS - - 100 A - Min Typ Max Units 1 - - s R ec om m SID88 SID89 - Table 14. XRES AC Specifications Spec ID# TRESETWIDTH Description Reset pulse width Details/ Conditions - N ot SID93 Parameter Document Number: 001-95464 Rev. *K Page 24 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Analog Peripherals Temperature Sensor Parameter TSENSACC Description Temperature sensor accuracy Min Typ Max Units Details/Conditions -5 1 5 C -40 to +85 C Min Typ Max SAR ADC Spec ID# Parameter Description Units D Table 16. SAR ADC DC Specifications es ig Spec ID# SID155 ns Table 15. Temperature Sensor Specifications Details/Conditions A_RES Resolution - - 12 bits SID157 A_CHNIS_S Number of channels - single-ended - - 16 - 8 full-speed SID158 A-CHNKS_D Number of channels - differential - SID159 A-MONO Monotonicity - SID160 A_GAINERR Gain error - SID161 A_OFFSET Input offset voltage SID162 A_ISAR Current consumption SID163 A_VINS SID164 SID165 ew SID156 - 8 - Differential inputs use neighboring I/O - - - Yes - 0.1 % With external reference fo r N - - 2 mV Measured with 1-V VREF - - 1 mA - Input voltage range - single-ended VSS - VDDA V - A_VIND Input voltage range - differential VSS - VDDA V - A_INRES Input resistance - - 2.2 k - SID166 A_INCAP Input capacitance - - 10 pF - SID312 VREFSAR Trimmed internal reference to SAR -1 - 1 % Min Typ Max Units 70 - - dB Common-mode rejection ratio 66 - - dB - - Percentage of Vbg (1.024 V) m en de d - Spec ID# Parameter A_PSRR Description Power supply rejection ratio R ec SID167 om Table 17. SAR ADC AC Specifications Details/ Conditions Measured at 1-V reference A_CMRR SID169 A_SAMP Sample rate - - 1 Msps SID313 Fsarintref SAR operating speed without external reference bypass - - 100 ksps SID170 A_SNR Signal-to-noise ratio (SNR) 65 - - dB SID171 A_BW Input bandwidth without aliasing - - A_SAMP/2 kHz SID172 A_INL Integral nonlinearity (INL). VDD = 1.71 to 5.5 V, 1 Msps -1.7 - 2 LSB VREF = 1 V to VDD SID173 A_INL Integral nonlinearity. VDDD = 1.71 to 3.6 V, 1 Msps -1.5 - 1.7 LSB VREF = 1.71 V to VDD SID174 A_INL Integral nonlinearity. VDD = 1.71 to 5.5 V, 500 ksps -1.5 - 1.7 LSB VREF = 1 V to VDD N ot SID168 Document Number: 001-95464 Rev. *K 12-bit resolution FIN = 10 kHz - Page 25 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 17. SAR ADC AC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions A_DNL Differential nonlinearity (DNL). VDD = 1.71 to 5.5 V, 1 Msps -1 - 2.2 LSB VREF = 1 V to VDD SID176 A_DNL Differential nonlinearity. VDD = 1.71 to 3.6 V, 1 Msps -1 - 2 LSB VREF = 1.71 V to VDD SID177 A_DNL Differential nonlinearity. VDD = 1.71 to 5.5 V, 500 Ksps -1 - 2.2 SID178 A_THD Total harmonic distortion - - -65 Description Min Typ Max 1.71 Parameter VCSD Voltage range of operation IDAC1 DNL for 8-bit resolution -1 SID181 IDAC1 INL for 8-bit resolution SID182 IDAC2 DNL for 7-bit resolution SID183 IDAC2 INL for 7-bit resolution SID184 SNR Ratio of counts of finger to noise SID187 es ig FIN = 10 kHz Units Details/ Conditions - 5.5 V - 1 LSB - -3 - 3 LSB - -1 - 1 LSB - - Capacitance range of 9-pF to 35-pF; 0.1-pF sensitivity. Radio is not operating during the scan. fo r -3 - 3 LSB 5 - - Ratio - 612 - A - - 306 - A - - 305 - A - - 153 - A - N ot R ec om SID188 en de d SID186 Output current of IDAC1 (8-bits) in HIGH IDAC1_CRT1 range Output current of IDAC1 (8-bits) in LOW IDAC1_CRT2 range Output current of IDAC2 (7-bits) in HIGH IDAC2_CRT1 range Output current of IDAC2 (7-bits) in LOW IDAC2_CRT2 range m SID185 dB VREF = 1 V to VDD - N SID179 SID180 ew Table 18. CSD Block Specifications Spec ID# LSB D CSD ns SID175 Document Number: 001-95464 Rev. *K Page 26 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Digital Peripherals 4x TCPWM Table 19. Timer DC Specifications Parameter ITIM1 Description Block current consumption at 3 MHz Min - Typ - Max 50 Units A SID190 ITIM2 Block current consumption at 12 MHz - - 175 A 16-bit timer SID191 ITIM3 Block current consumption at 48 MHz - - 712 A 16-bit timer Min FCLK Typ - Max 48 es ig Parameter TTIMFREQ Description Operating frequency Units MHz Details/Conditions - SID193 TCAPWINT Capture pulse width (internal) 2 x TCLK - - ns - SID194 TCAPWEXT Capture pulse width (external) 2 x TCLK SID195 TTIMRES Timer resolution - - ns - - - ns - SID196 TTENWIDINT Enable pulse width (internal) 2 x TCLK SID197 TTENWIDEXT Enable pulse width (external) 2 x TCLK - - ns - - - ns - SID198 TTIMRESWINT Reset pulse width (internal) SID199 TTIMRESEXT Reset pulse width (external) 2 x TCLK - - ns - 2 x TCLK - - ns - fo r N TCLK ew Spec ID SID192 D Table 20. Timer AC Specifications Details/Conditions 16-bit timer ns Spec ID SID189 Counter Table 21. Counter DC Specifications Parameter ICTR1 Description Block current consumption at 3 MHz Min - Typ - Max 50 SID201 ICTR2 Block current consumption at 12 MHz - - 175 A 16-bit Counter SID202 ICTR3 Block current consumption at 48 MHz - - 712 A 16-bit Counter Min FCLK Typ - Max 48 Units MHz Details/Conditions - en de d Spec ID SID200 Units Details/Conditions A 16-bit Counter Table 22. Counter AC Specifications Parameter TCTRFREQ Description Operating frequency SID204 TCTRPWINT Capture pulse width (internal) 2 x TCLK - - ns - SID205 TCTRPWEXT Capture pulse width (external) 2 x TCLK - - ns - SID206 TCTRES Counter resolution TCLK - - ns - SID207 TCENWIDINT Enable pulse width (internal) 2 x TCLK - - ns - SID208 TCENWIDEXT Enable pulse width (external) 2 x TCLK - - ns - SID209 TCTRRESWINT Reset pulse width (internal) 2 x TCLK - - ns - SID210 TCTRRESWEXT Reset pulse width (external) 2 x TCLK - - ns - Min Typ Max Units Details/Conditions R ec om m Spec ID SID203 ot Pulse Width Modulation (PWM) Table 23. PWM DC Specifications N Spec ID Parameter Description SID211 IPWM1 Block current consumption at 3 MHz - - 50 A 16-bit PWM SID212 IPWM2 Block current consumption at 12 MHz - - 175 A 16-bit PWM SID213 IPWM3 Block current consumption at 48 MHz - - 741 A 16-bit PWM Document Number: 001-95464 Rev. *K Page 27 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 24. PWM AC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions TPWMFREQ Operating frequency FCLK - 48 MHz - TPWMPWINT Pulse width (internal) 2 x TCLK - - ns - SID216 TPWMEXT Pulse width (external) 2 x TCLK - - ns SID217 TPWMKILLINT Kill pulse width (internal) 2 x TCLK - - ns SID218 TPWMKILLEXT Kill pulse width (external) 2 x TCLK - - SID219 TPWMEINT Enable pulse width (internal) 2 x TCLK - - SID220 TPWMENEXT Enable pulse width (external) 2 x TCLK - - SID221 TPWMRESWINT Reset pulse width (internal) 2 x TCLK - - SID222 TPWMRESWEXT Reset pulse width (external) 2 x TCLK - Table 25. I2C DC Specifications Parameter Description Min - - es ig - - ns - ns - ns - D ns ns - Typ Max Units Details/Conditions - 50 A - II2C1 Block current consumption at 100 kHz SID224 II2C2 Block current consumption at 400 kHz - - 155 A - SID225 II2C3 Block current consumption at 1 Mbps - - 390 A - II2C4 I2C - - 1.4 A - Min - Typ - Max 1 Units Mbps Details/Conditions - Min Typ Max Units - 17.5 - A - 500 5000 pF - 20 - mV - 2 - mA - 2 - mA Min 10 Typ 50 Max 150 Units Hz SID226 fo r SID223 N Spec ID - ew I2C ns SID214 SID215 enabled in Deep-Sleep mode Spec ID SID227 Parameter FI2C1 en de d Table 26. Fixed I2C AC Specifications Description Bit rate LCD Direct Drive Table 27. LCD Direct Drive DC Specifications Parameter ILCDLOW SID229 CLCDCAP SID230 LCDOFFSET SID231 ILCDOP1 Operating current in low-power mode LCD capacitance per segment/common driver Long-term segment offset LCD system operating current. Vbias = 5 V LCD system operating current. Vbias = 3.3 V R ec om SID228 Description m Spec ID SID232 ILCDOP2 Details/Conditions 16 x 4 small-segment display at 50 Hz 32 x 4 segments. 50 Hz. 25 C 32 x 4 segments. 50 Hz. 25 C Table 28. LCD Direct Drive AC Specifications Parameter FLCD ot Spec ID SID233 Description LCD frame rate Details/Conditions - N Table 29. Fixed UART DC Specifications Spec ID SID234 SID235 Parameter Description Min Typ Max Units Details/Conditions IUART1 Block current consumption at 100 kbps - - 55 A - IUART2 Block current consumption at 1000 kbps - - 360 A - Document Number: 001-95464 Rev. *K Page 28 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 30. Fixed UART AC Specifications SID236 Parameter FUART Description Bit rate Min Typ Max Units Details/Conditions - - 1 Mbps - Min Typ Max ns Spec ID SPI Specifications Spec ID Parameter Description es ig Table 31. Fixed SPI DC Specifications Units Details/Conditions A - A - A - ISPI1 Block current consumption at 1 Mbps - - 360 SID238 ISPI2 Block current consumption at 4 Mbps - - 560 SID239 ISPI3 Block current consumption at 8 Mbps - - 600 Min Typ Max Units Details/Conditions - 8 MHz - D SID237 SID240 Parameter FSPI Description SPI operating frequency (master; 6x oversampling) Table 33. Fixed SPI Master Mode AC Specifications Parameter TDMO SID242 TDSI SID243 THMO Description MOSI valid after SCLK driving edge MISO valid before SCLK capturing edge. Full clock, late MISO sampling used Min - Typ - Max 18 Units ns Details/Conditions - 20 - - ns Full clock, late MISO sampling 0 - - ns Referred to Slave capturing edge fo r Spec ID SID241 - N Spec ID ew Table 32. Fixed SPI AC Specifications en de d Previous MOSI data hold time Table 34. Fixed SPI Slave Mode AC Specifications Parameter TDMI Description MOSI valid before SCLK capturing edge SID245 TDSO SID246 TDSO_ext MISO valid after SCLK driving edge MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V Previous MISO data hold time THSO TSSELSCK om SID247 SID248 m Spec ID SID244 Typ - Max - Units ns - - 42 + 3 x TCPU ns - - 53 ns 0 - - ns 100 - - ns N ot R ec SSEL valid to first SCK valid edge Min 40 Document Number: 001-95464 Rev. *K Page 29 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Memory Table 35. Flash DC Specifications Min 1.71 Typ - Max 5.5 Units V SID309 TWS48 SID310 SID311 Number of Wait states at 32-48 MHz 2 - - - TWS32 Number of Wait states at 16-32 MHz 1 - - TWS16 Number of Wait states for 0-16 MHz 0 - - Min Typ Max Units - - 20 ms - 13 ms Details/Conditions Row (block) = 256 bytes - TROWWRITE[5] SID251 TROWERASE[5] SID252 SID253 TROWPROGRAM [5] Row program time after erase TBULKERASE[5] Bulk erase time (256 KB) Total device program time SID254 TDEVPROG SID255 FEND SID256 FRET SID257 FRET2 [5] Power-on-Reset (POR) Table 37. POR DC Specifications - 7 ms - - - 35 ms - - - Parameter VRISEIPOR SID259 VFALLIPOR SID260 VIPORHYST 25 seconds - 100 K - - cycles - 20 - - years - 10 - - years - Min Typ Max Units Details/Conditions Rising trip voltage 0.80 - 1.45 V - Falling trip voltage 0.75 - 1.40 V - 15 - 200 mV - Min Typ Max Units Details/Conditions - - 1 s - Min Typ Max Units Details/Conditions Hysteresis om SID258 Description m Spec ID - Flash endurance Flash retention. TA 55 C, 100 K P/E cycles Flash retention. TA 85 C, 10 K P/E cycles System Resources - N SID250 Description Row (block) write time (erase and program) Row erase time - fo r Parameter en de d Spec ID - ew Table 36. Flash AC Specifications Details/Conditions - CPU execution from flash CPU execution from flash CPU execution from flash ns Description Erase and program voltage es ig Parameter VPE D Spec ID SID249 Table 38. POR AC Specifications Parameter R ec Spec ID SID264 TPPOR_TR Description Precision power-on reset (PPOR) response time in Active and Sleep modes ot Table 39. Brown-Out Detect N Spec ID# Parameter Description SID261 VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 - - V - SID262 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 - - V - Note 5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 001-95464 Rev. *K Page 30 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 40. Hibernate Reset SID263 Parameter VHBRTRIP Description Min Typ Max Units 1.1 - - V Description Min Typ Max BOD trip voltage in Hibernate Table 41. Voltage Monitor DC Specifications Spec ID Parameter VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 SID266 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 SID267 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 LVI_A/D_SEL[3:0] = 0011b 1.95 LVI_A/D_SEL[3:0] = 0100b 2.05 SID270 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 SID271 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 SID272 VLVI8 LVI_A/D_SEL[3:0] = 0111b SID273 VLVI9 LVI_A/D_SEL[3:0] = 1000b SID274 VLVI10 LVI_A/D_SEL[3:0] = 1001b SID2705 VLVI11 LVI_A/D_SEL[3:0] = 1010b V - V - 2.00 2.05 V - 2.10 2.15 V - ew VLVI4 VLVI5 2.20 2.26 V - 2.30 2.36 V - N SID268 SID269 V Details/ Conditions - Units D SID265 - es ig Voltage Monitors (LVD) Details/ Conditions ns Spec ID# 2.40 2.46 V - 2.50 2.56 V - fo r 2.34 2.44 2.54 2.60 2.67 V - 2.63 2.70 2.77 V - VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V - VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V - SID278 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V - en de d SID276 SID277 SID279 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V - SID280 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V - SID281 LVI_IDD Block current - - 100 A - SID282 Parameter Description om Spec ID m Table 42. Voltage Monitor AC Specifications TMONTRIP SWD Interface Voltage monitor trip time Min Typ Max Units Details/ Conditions - - 1 s - Min Typ Max R ec Table 43. SWD Interface Specifications Spec ID Parameter Description Units Details/Conditions F_SWDCLK1 3.3 V VDD 5.5 V - - 14 MHz SWDCLK 1/3 CPU clock frequency SID284 F_SWDCLK2 1.71 V VDD 3.3 V - - 7 MHz SWDCLK 1/3 CPU clock frequency ot SID283 T_SWDI_SETUP T = 1/f SWDCLK 0.25 x T - - ns - T_SWDI_HOLD 0.25 x T - - ns - SID287 T_SWDO_VALID T = 1/f SWDCLK - - 0.5 x T ns - SID288 T_SWDO_HOLD T = 1/f SWDCLK 1 - - ns - N SID285 SID286 T = 1/f SWDCLK Document Number: 001-95464 Rev. *K Page 31 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Internal Main Oscillator Table 44. IMO DC Specifications Parameter Description Min Typ Max Units Details/Conditions - IIMO1 IMO operating current at 48 MHz - - 1000 A IIMO2 IMO operating current at 24 MHz - - 325 A SID291 IIMO3 IMO operating current at 12 MHz - - 225 A SID292 IIMO4 IMO operating current at 6 MHz - - 180 SID293 IIMO5 IMO operating current at 3 MHz - - 150 Min Typ Parameter Description SID296 FIMOTOL3 Frequency variation from 3 to 48 MHz SID297 FIMOTOL3 IMO startup time % - 12 - s Details/Conditions With API-called calibration - Min Typ Max Units Details/Conditions - 0.3 1.05 A - Typ Max Units Details/Conditions en de d Parameter Units N Description ILO operating current at 32 kHz Table 47. ILO AC Specifications Spec ID - 2 fo r Parameter IILO2 - A - Table 46. ILO DC Specifications Spec ID A - Internal Low-Speed Oscillator SID298 Max ew Spec ID - D Table 45. IMO AC Specifications - es ig SID289 SID290 ns Spec ID Description Min SID299 TSTARTILO1 ILO startup time - - 2 ms - SID300 FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz - Min Typ Max Units Details/Conditions Table 48. External Clock Specifications Spec ID Parameter Description ExtClkFreq External clock input frequency 0 - 48 MHz SID302 ExtClkDuty Duty cycle; measured at VDD/2 45 - 55 % CMOS input level only. TTL input is not supported Min Typ Max Units Details/ Conditions - 24 - MHz - -50 - 50 ppm - om m SID301 CMOS input level only. TTL input is not supported R ec Table 49. ECO Specifications Spec ID# Parameter Description FECO Crystal frequency SID390 FTOL Frequency tolerance SID391 ESR Equivalent series resistance - - 60 - SID392 PD Drive level - - 100 W - SID393 TSTART1 Startup time (Fast Charge on) - - 850 s - SID394 TSTART2 Startup time (Fast Charge off) - - 3 ms - SID395 CL Load capacitance - 8 - pF - SID396 C0 Shunt capacitance - 1.1 - pF - SID397 IECO Operating current - 1400 - A - N ot SID389 Document Number: 001-95464 Rev. *K Page 32 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 50. WCO Specifications Parameter Description Min Typ Max Units Details/ Conditions - SID398 FWCO Crystal frequency - 32.768 - kHz SID399 FTOL Frequency tolerance - 50 - ppm Equivalent series resistance - 50 - Drive level - - 1 k SID402 TSTART Startup time - - 500 SID403 CL Crystal load capacitance 6 - 12.5 SID404 C0 Crystal shunt capacitance - 1.35 - SID405 IWCO1 Operating current (high-power mode) - - 8 SID406 IWCO2 Operating current (low-power mode) - ew 2.6 - W - ms - pF - pF - A - A - N ot R ec om m en de d fo r N - - es ig ESR PD D SID400 SID401 ns Spec ID# Document Number: 001-95464 Rev. *K Page 33 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Ordering Information TCPWM 12-bit ADC I2S PWM 2 4 1 Msps Yes 1 CYBL10573-76FNXI 48 256 No Yes (Gestures) 2 4 1 Msps Yes 1 CYBL11171-56LQXI 48 256 Yes No 1 2 1 Msps No Yes 56-QFN 4.1 Yes 76-WLCSP 4.1 No 56-QFN 4.2 ns SCB Yes (Gestures) Bluetooth Version CapSense No Package DMA 256 es ig Flash Size (KB) 48 LCD CPU Speed (MHz) CYBL10573-56LQXI D Part Number The CYBL1XX7X part numbers and features are listed in the following table. CYBL11172-56LQXI 48 256 Yes No 2 4 1 Msps No 4 No 56-QFN 4.2 CYBL11173-56LQXI 48 256 Yes No 2 4 1 Msps Yes 0 No 56-QFN 4.2 CYBL11471-56LQXI 48 256 Yes Yes 2 4 1 Msps No 0 No 56-QFN 4.2 CYBL11472-56LQXI 48 256 Yes Yes 2 4 CYBL11473-56LQXI 48 256 Yes Yes 2 4 N ew 0 2 4 4 Yes 0 No 56-QFN 4.2 1 Msps No 0 Yes 56-QFN 4.2 1 Msps No 0 No 56-QFN 4.2 1 Msps Yes 1 No 56-QFN 4.2 fo r 1 Msps 48 256 Yes CYBL11572-56LQXI 48 256 Yes Yes (Gestures) 2 CYBL11573-56LQXI 48 256 Yes Yes (Gestures) 2 4 1 Msps Yes 1 Yes 56-QFN 4.2 CYBL11573-56LQXQ 48 256 Yes Yes (Gestures) 2 4 1 Msps Yes 1 Yes 56-QFN 4.2 CYBL11573-76FNXI 48 256 Yes Yes (Gestures) 2 4 1 Msps Yes 1 Yes 76-WLCSP 4.2 CYBL11573-76FLXI 48 256 Yes Yes (Gestures) 2 4 1 Msps Yes 1 Yes 76-Thin CSP 4.2 CYBL11573-76FNXQ 48 256 Yes Yes (Gestures) 2 4 1 Msps Yes 1 Yes 76-WLCSP 4.2 N ot R ec om m en de d CYBL11571-56LQXI Yes (Gestures) Document Number: 001-95464 Rev. *K Page 34 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Ordering Code Definitions CY BL 1 X A B C - DE FG H I ns Temperature Range: I = Industrial, Q = Extended Industrial X = Pb-Free Number of pins in the package es ig Package Code: LQ = QFN, FN = WLCSP (0.55-mm Thickness), FL = Thin CSP (0.4-mm Thickness) Device Identification Number that corresponds to the part feature set Flash Capacity: 7 = 256 KB D Product Type: 1 = Embedded MCU, 4 = CapSense, 5 = CapSense with Gestures Bluetooth Standard Supported: 0 = BLE4.1, 1 = BLE 4.2 ew st Subfamily: 1 = 1 BLE family Marketing Code: BL = BLE Product family The Field Values are listed in the following table: Description CYBL Cypress PRoC BLE Family 1X Subfamily en de d Field A Product Type B Flash Capacity Values Meaning CYBL 10, 11 1st Generation BLE 4.1, 4.2 1 Embedded Only 4 CapSense 5 Touch 7 256 KB Feature set m C Package Pins R ec om DE FG fo r N Company ID: CY = Cypress Package code Pb I Temperature Range 76 LQ QFN FN WLCSP FL Thin CSP X Pb-free X Absent (with Pb) Q Extended temp -40 C to 105 C I Industrial -40 C to 85 C N ot H 56 Note 6. All part numbers support input voltage from 1.9 V to 5.5 V. Document Number: 001-95464 Rev. *K Page 35 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Packaging Table 51. Package Characteristics Min Typ Operating ambient temperature Description - -40 25 TJ Operating junction temperature - -40 - TJA Package JA (56-pin QFN) - - 16.9 TJC Package JC (56-pin QFN) - - TJA Package JA (76-ball WLCSP) - - Package JC (76-ball WLCSP) - - Package JA (76-ball Thin WLCSP) - - TJC Package JC (76-ball Thin WLCSP) - 260 C 76-ball WLCSP and Thin WLCSP 260 C N 56-pin QFN fo r Maximum Peak Temperature C 125 C - C/watt 9.7 - C/watt 20.1 - C/watt 0.19 - C/watt 20.9 - C/watt 0.17 - C/watt ew - Table 52. Solder Reflow Peak Temperature Package Units 105 D TJC TJA Max ns Parameter es ig Conditions TA Maximum Time at Peak Temperature 30 seconds 30 seconds Table 53. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 56-pin QFN en de d Package 76-ball WLCSP and Thin WLCSP Spec ID 001-58740 Rev. *C 001-96603 Rev. *A MSL 3 MSL 1 Description 56-pin QFN 7 mm x 7 mm x 0.6 mm 76-ball WLCSP 4.04 mm x 3.87 mm x 0.55 mm 76-ball thin WLCSP 4.04 mm X 3.87 mm X 0.4 mm N ot R ec om 002-10658, Rev. ** Package m Table 54. Package Details MSL Document Number: 001-95464 Rev. *K Page 36 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Figure 6. 56-Pin QFN 7 mm x 7 mm x 0.6 mm TOP VIEW SIDE VIEW fo r N ew D es ig ns BOTTOM VIEW NOTES: HATCH AREA IS SOLDERABLE EXPOSED PAD 2. BASED ON REF JEDEC # MO-248 3. ALL DIMENSIONS ARE IN MILLIMETERS en de d 1. 001-58740 *C N ot R ec om m The center pad on the QFN package must be connected to ground (VSS) for the proper operation of the device. Document Number: 001-95464 Rev. *K Page 37 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet WLCSP Compatibility The PRoC BLE family has products with 128 KB (16KB SRAM) and 256 KB (32KB SRAM) Flash. Package pin-outs and sizes are identical for the 56-pin QFN package but are different in one dimension for the 68-ball WLCSP. Figure 7 shows the 128KB and 256 KB Flash CSP Packages. Figure 7. 128KB and 256 KB Flash CSP Packages 128K BLE en de d fo r N ew D 256K BLE es ig ns The 256KB Flash product has an extra column of balls which are required for mechanical integrity purposes in the Chip-Scale package. With consideration for this difference, the land pattern on the PCB may be designed such that either product may be used with no change to the PCB design. m CONNECTED PADS NC PADS PACKAGE CENTER PACK BOUNDARY FIDUCIAL FOR128K FIDUCIAL FOR256K om The rightmost column of (all NC, No Connect) balls in the 256K BLE WLCSP is for mechanical integrity purposes. The package is thus wider (3.2 mm versus 2.8 mm). All other dimensions are identical. Cypress will provide layout symbols for PCB layout. N ot R ec The scheme in Figure 7 is implemented to design the PCB for the 256K BLE package with the appropriate space requirements thus allowing use of either package at a later time without redesigning the Printed Circuit Board. Document Number: 001-95464 Rev. *K Page 38 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Figure 8. 76-Ball WLCSP Package Outline PIN #1 MARK B 7 1 2 3 4 5 6 7 8 9 9 8 7 6 5 4 3 2 1 A B B 6 C C SD D D D1 D E es ig E ns A F F G G eD H H J J SE A eE 6 D E E1 BOTTOM VIEW ew TOP VIEW 0.10 C C 76XOb N A1 0.05 C DETAIL A 5 fo r O0.06 M C A B O0.03 M C A DETAIL A SIDE VIEW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. SYMBOL MIN. A - A1 0.18 en de d DIMENSIONS MAX. - 0.55 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 0.21 0.24 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. D 3.87 BSC E 4.04 BSC D1 3.20 BSC E1 3.20 BSC MD SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. m 9 ME 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND 9 N DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. om 76 b 0.23 0.26 eD 0.40 BSC eE 0.40 BSC SD 0.381 BSC 0.321 BSC 0.29 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 9. JEDEC SPECIFICATION NO. REF : N/A 001-96603 *B N ot R ec SE 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. NOM. Document Number: 001-95464 Rev. *K Page 39 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Figure 9. 76-Ball Thin WLCSP Package Outline PIN #1 MARK B 1 2 3 4 5 6 7 8 9 9 8 7 6 5 4 3 2 1 A A B B 6 C C SD D E D D1 D E F es ig F ns 7 G G eD H H J J SE A E eE 6 D E1 BOTTOM VIEW ew TOP VIEW 0.10 C C 76XOb 5 N A1 0.05 C DETAIL A O0.06 M C A B O0.03 M C fo r A DETAIL A SIDE VIEW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS SYMBOL NOM. MAX. A - - 0.40 A1 0.072 0.08 0.088 E N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX 4.04 BSC SIZE MD X ME. 3.20 BSC D1 E1 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A 3.20 BSC MD PLANE PARALLEL TO DATUM C. 9 ME 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND 9 N DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. 76 om eE 0.22 0.25 m b eD 0.40 BSC 0.40 BSC 0.381 SE 0.321 0.28 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 002-10658 ** N ot R ec SD 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. 3.87 BSC D 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. en de d MIN. Document Number: 001-95464 Rev. *K Page 40 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Acronyms Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus Acronym Description ns Acronym Table 55. Acronyms Used in This Document (continued) ETM embedded trace macrocell FET field-effect transistor FIR finite impulse response, see also IIR FPB flash patch and breakpoint es ig Table 55. Acronyms Used in This Document FS full-speed GPIO general-purpose input/output, applies to a PSoC pin arithmetic logic unit AMUXBUS analog multiplexer bus HCI host controller interface API application programming interface HVI high-voltage interrupt, see also LVI, LVD APSR application program status register IC ARM(R) advanced RISC machine, a CPU architecture IDAC ATM automatic thump mode IDE ew D ALU integrated circuit current DAC, see also DAC, VDAC N BW bandwidth CAN Controller Area Network, a communications protocol integrated development environment Inter-Integrated Circuit, a communications protocol fo r I2C, or IIC I2S Inter-IC Sound IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO internal main oscillator, see also ILO common-mode rejection ratio CPU central processing unit CRC cyclic redundancy check, an error-checking protocol IMO INL integral nonlinearity, see also DNL DAC digital-to-analog converter, see also IDAC, VDAC I/O input/output, see also GPIO, DIO, SIO, USBIO DFB digital filter block IPOR initial power-on reset DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. IPSR interrupt program status register DMIPS Dhrystone million instructions per second DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR DWT ECC instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. port write data registers LR link register digital system interconnect LUT lookup table data watchpoint and trace LVD low-voltage detect, see also LVI error correcting code LVI low-voltage interrupt, see also HVI om m interrupt request ITM external crystal oscillator LVTTL low-voltage transistor-transistor logic EEPROM electrically erasable programmable read-only memory MAC multiply-accumulate EMI electromagnetic interference MCU microcontroller unit EMIF external memory interface MISO master-in slave-out EOC end of conversion NC no connect EOF end of frame NMI nonmaskable interrupt EPSR execution program status register ESD electrostatic discharge N ot ECO IRQ R ec DSI en de d CMRR Document Number: 001-95464 Rev. *K NRZ non-return-to-zero NVIC nested vectored interrupt controller Page 41 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Table 55. Acronyms Used in This Document (continued) Acronym Description Table 55. Acronyms Used in This Document (continued) Acronym Description nonvolatile latch, see also WOL SRAM static random access memory opamp operational amplifier SRES software reset PAL programmable array logic, see also PLD STN super twisted nematic PC program counter SWD serial wire debug, a test protocol PCB printed circuit board SWV single-wire viewer PGA programmable gain amplifier TD transaction descriptor, see also DMA PHUB peripheral hub THD total harmonic distortion PHY physical layer TIA transimpedance amplifier PICU port interrupt control unit TN twisted nematic PLA programmable logic array TRM technical reference manual PLD programmable logic device, see also PAL TTL PLL phase-locked loop TX PMDD package material declaration data sheet UART POR power-on reset PRES precise power-on reset port read data register PSoC(R) Programmable System-on-ChipTM PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register es ig D ew N VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal om switched capacitor/continuous time SCL I2C serial clock S/H USB input/output, PSoC pins used to connect to a USB port R ec SC/CT SDA Universal Serial Bus USBIO m RTC transmit Universal Asynchronous Transmitter Receiver, a communications protocol fo r pseudo random sequence PS transistor-transistor logic USB en de d PRS ns NVL I2C serial data sample and hold signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. N ot SINAD SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate Document Number: 001-95464 Rev. *K Page 42 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Document Conventions Units of Measure Table 56. Units of Measure (continued) Unit of Measure Unit of Measure H microhenry microsecond degrees Celsius dB decibel V microvolt dBm decibel-milliwatts W microwatt fF femtofarads mA milliampere Hz hertz ms millisecond KB 1024 bytes mV millivolt kbps kilobits per second nA nanoampere Khr kilohour ns nanosecond kHz kilohertz nV k kilo ohm ksps kilosamples per second pF LSB least significant bit ppm ew D C s ns Symbol Symbol es ig Table 56. Units of Measure nanovolt N ohm picofarad picosecond s second sps samples per second en de d fo r parts per million ps megabits per second MHz megahertz M mega-ohm Msps megasamples per second sqrtHz square root of hertz A microampere V volt F microfarad W watt N ot R ec om m Mbps Document Number: 001-95464 Rev. *K Page 43 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Revision History N ot R ec om m en de d fo r N ew D es ig ns Description Title: PRoCTM BLE: CYBL1XX7X Family Datasheet Programmable Radio-on-Chip With Bluetooth Low Energy Document Number: 001-95464 Orig. of Submission Revision ECN Description of Change Change Date *J 5438827 DEJO 09/16/2016 Release to web Updated the template. *K 5669710 SGUP 03/27/2017 Added NRND watermark. Document Number: 001-95464 Rev. *K Page 44 of 45 PRoCTM BLE: CYBL1XX7X Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support PSoC(R) Solutions cypress.com/arm cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch USB Controllers N Touch Sensing cypress.com/usb cypress.com/wireless om m en de d fo r Wireless Connectivity es ig Automotive D ARM(R) Cortex(R) Microcontrollers ew Products ns Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. R ec (c) Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. N ot CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-95464 Rev. *K Revised March 27, 2017 Page 45 of 45