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Low Noise/Low Power/2-Wire Bus
X9418
Dual Digitally Controlled Potentiometers (XDCP
™
)
FEATURES
• Two potentiometers in one package
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per
Potentiometer
• Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications
• High reliability
—Endurance–100,000 Data Changes per Bit per
Register
—Register Data Retention–100 years
• 8-bytes of nonvolatile memory
• 2.5K
Ω
, 10K
Ω
resistor array
• Resolution: 64 taps each potentiometer
• 24-pin plastic DIP, 24-lead TSSOP and 24-lead
SOIC packages
DESCRIPTION
The X9418 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
R0 R1
R2 R3
Resistor
Array
XDCP1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Interface
and
Control
Circuitry
SCL
SDA
A0
A1
A2
A3
VH0/RH0
VL0/RL0
Data
8
VW0/RW0
VW1/RW1
Wiper
Counter
Register
(WCR)
WP
VCC
VSS
V+
V-
A
PPLICATION
N
OTES
AVAILABLE
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
X9418
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PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9418.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A
0
–
A
3
)
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9418. A maximum of 16
devices may occupy the 2-wire serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
—V
H1
/R
H1
), V
L
/R
L
(V
L0
/R
L0
—V
L1
/R
L1
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
V
W
/R
W
(V
W0
/R
W0
—V
W1
/R
W1
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.
PIN CONFIGURATION
PIN NAMES
Symbol Description
SCL Serial Clock
SDA Serial Data
A0-A3 Device Address
V
H0
/R
H0
–V
H1
/R
H1
,
V
L0
/R
L0
–V
L1
/R
L1
Potentiometer Pins
(terminal equivalent)
V
W0
/R
W0
–V
W1
/R
W1
Potentiometer Pins
(wiper equivalent)
WP Hardware Write Protection
V+,V- Analog Supplies
V
CC
System Supply Voltage
V
SS
System Ground
NC No Connection
VCC
RL0/VL0
RH0/VH0
WP
SDA
A1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
5
V+
NC
NC
NC
A0
NC
A3
SCL
NC
NC
DIP/SOIC
X9418
VSS
RW0/VW0
14
13
11
12
A2
RL1/VL1
RH1/VH1
RW1/VW1 NC
V-
SDA
A1
RL1/VL1
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
A2
VW0/RW0
VH0/RH0
VL0/RL0
VCC
NC
NC
NC
V+
X9418
A3
RH1/VH1
14
13
11
12
RW1/VW1
NC
V-
SCL A0
NC
TSSOP
X9418
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PRINCIPLES OF OPERATION
The X9418 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9418 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9418 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
LOW
). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9418 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9418 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9418 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9418 will respond with a final acknowledge.
Array Description
The X9418 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9418
this is fixed as 0101[B].
Figure 1. Slave Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0–A3 inputs. The X9418 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9418 to respond with an acknowledge. The
A0–A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
100
A3 A2 A1 A0
Device Type
Identifier
Device Address
1
X9418
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Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9418
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9418 is still busy with the write operation no ACK will
be returned. If the X9418 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The next byte sent to the X9418 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.
Figure 2. Instruction Byte Format
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented
instruction is issued. The last bits (P0) select which
one of the two potentiometers is to be affected by the
instruction. Bit 1 is defined to be 0.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed tWRL. A transfer from the wiper
counter register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the two potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between both of the potentiometers
and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9418; either between the host and one
of the Data Registers or directly between the host and
the wiper counter register. These instructions are:
Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter
Register (change current wiper position of the selected
pot), read Data Register (read the contents of the
selected nonvolatile register) and write Data Register
(write a new value to the selected Data Register). The
sequence of operations is shown in Figure 4.
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction Issue STOP
NO
YES
YES
Proceed
Issue STOP
NO
Proceed
I1I2I3 I0 R1 R0 0 P0
Wiper Counter
Register Select
Register
Select
Instructions
X9418
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Figure 3. Two-Byte Instruction Sequence
S
T
A
R
T
0101A3A2A1A0A
C
K
I3 I2 I1 I0 R1 R0 0 P0 A
C
K
SCL
SDA
S
T
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9418 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
capability to the host. For each SCL clock pulse (tHIGH)
while SDA is HIGH, the selected wiper will move one
resistor segment towards the VH/RH terminal. Similarly,
for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards
the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
Table 1. Instruction Set
Note: (7) 1/0 = data is one or zero
Instruction
Instruction Set
OperationI3I2I1I0R1R0P1P0
Read Wiper Counter
Register
1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter Register
pointed to by P0
Write Wiper Counter
Register
1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter Register
pointed to by P0
Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register pointed to
by P0 and R1–R0
Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register pointed to by
P0 and R1–R0
XFR Data Register to
Wiper Counter Register
1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register pointed
to by P0 and R1–R0 to its associated Wiper Counter
Register
XFR Wiper Counter
Register to Data Register
1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter Register
pointed to by P0 to the Data Register pointed to by
R1–R0
Global XFR Data
Registers to Wiper
Counter Registers
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed
to by R1–R0 of both pots to their respective Wiper
Counter Registers
Global XFR Wiper
Counter Registers to
Data Register
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by R1–R0 of both pots
Increment/Decrement
Wiper Counter Register
0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter
Register pointed to by P0
X9418
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Figure 4. Three-Byte Instruction Sequence
Figure 5. Increment/Decrement Instruction Sequence
Figure 6. Increment/Decrement Timing Limits
S
T
A
R
T
0 1 0 1 A3 A2 A1 A0 A
C
K
I3 I2 I1 I0 R1 R0 0 P0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
0 0 D5 D4 D3 D2 D1 D0
S
T
A
R
T
0101A3A2A1A0A
C
K
I3 I2 I1 I0 R0 0 P0 A
C
K
SCL
SDA
S
T
O
P
XX
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
SCL
SDA
VW/RW
INC/DEC
CMD
Issued
Voltage Out
tWRID
X9418
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Figure 7. Acknowledge Response from Receiver
Figure 8. Detailed Potentiometer Block Diagram
SCL from
Data Output
from Transmitter
189
START Acknowledge
Master
Data Output
from Receiver
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
VH/RH
VL/RL
VW/RW
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
8 6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
X9418
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DETAILED OPERATION
Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and four Data Registers.
A detailed discussion of the register organization and
array operation follows.
Wiper Counter Register
The X9418 contains two wiper counter registers, one
for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9418 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile
Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).
– {D5~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.
Wiper Counter Register, (6-Bit), Volatile
One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV
(MSB) (LSB)
WP5 WP4 WP3 WP2 WP1 WP0
VVVVVV
(MSB) (LSB)
X9418
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Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
WCR
addresses S
A
C
K
wiper position
(sent by slave on SDA) M
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
01001000P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
WCR
addresses S
A
C
K
wiper position
(sent by master on SDA) S
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
01010000P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
wiper position/data
(sent by slave on SDA) M
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
01011R
1
R
00P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
wiper position/data
(sent by master on SDA) S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
2
A
1
A
01100 R
1
R
00P0 00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
01101R
1
R
00P
0
X9418
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XFR Wiper Counter Register (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
2
A
1
A
01110R
1
R
00P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
WCR
addresses S
A
C
K
increment/decrement
(sent by master on SDA) S
T
O
P
0101A
3
A
2
A
1
A
00010000P
0
I/
D
I/
D....
I/
D
I/
D
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR
addresses S
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
00001R
1
R
000
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR
addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
2
A
1
A
01000R
1
R
000
SYMBOL TABLE Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
120
100
80
40
60
20
20 40 60 80 100 120
00
Resistance (K)
Bus Capacitance (pF)
Min.
Resistance
Max.
Resistance
RMAX = CBUS
tR
RMIN = IOL MIN
VCC MAX =1.8KΩ
X9418
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ....................–65°C to +135°C
Storage temperature.........................–65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to VSS......................... –1V to +7V
Voltage on V+ (referenced to VSS) ........................ 10V
Voltage on V- (referenced to VSS) ........................ -10V
(V+) – (V-) ............................................................. 12V
Any VH/RH, VL/RL, VW/RW ............................. V- to V+
Lead temperature (soldering, 10 seconds) ........300°C
IW (10 seconds) ................................................. ±6mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Device Supply Voltage (VCC) Limits
X9418 5V ±10%
X9418-2.7 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
End to end resistance tolerance –20 +20 %
Power rating 50 mW 25°C, each pot
IW Wiper current –3 +3 mA
RWWiper resistance 150 250 ΩWiper current = ± 1mA, V+, V- = ±3V
40 100 ΩWiper current = ± 1mA, V+, V- = ±5V
V+ Voltage on V+ pin X9418 +4.5 +5.5 V
X9418-2.7 +2.7 +5.5
V- Voltage on V- pin X9418 -5.5 -4.5 V
X9418-2.7 -5.5 -2.7
VTERM Voltage on any VH/RH, VL/RL or
VW/RW
V- V+ V
Noise -120 dBV Ref: 1kHz
Resolution (4) 1.6 % See Note 4
Absolute linearity (1) –1 +1 MI(3) Vw(n)(actual)—Vw(n)(expected)(4)
Relative linearity (2) –0.2 +0.2 MI(3) Vw(n + 1)—[Vw(n) + MI](4)
Temperature Coefficient of RTOTAL ±300 ppm/°C See Note 4
Ratiometric Temperature Coefficient ±20 ppm/°C See Note 4
CH/CL/CWPotentiometer Capacitances 10/10/25 pF See Circuit #3,
Spice Macromodel
IAL RH, RL, RW Leakage Current 0.1 10 µA VIN = V– to V+. Device is in Stand-by
mode.
X9418
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH—RL)/63, single pot
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V–, and then the potentiometer pins, RH,
RL, and RW. Voltage should not be applied to the potentiometer pins before V+ or V– is applied. The VCC ramp rate
specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possi-
ble. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will
not be complete until VCC, V+ and V– reach their final value.
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is a tested or guaranteed parameter and should only be used as a guidance.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
ICC1 VCC supply current
(nonvolatile write)
1mAf
SCL = 400kHz, SDA = Open,
Other Inputs = VSS
ICC2 VCC supply current
(move wiper, write, read)
100 µA fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = VSS
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V
VIL Input LOW voltage –0.5 VCC x 0.1 V
VOL Output LOW voltage 0.4 V IOL = 3mA
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 Years
Symbol Test Max. Unit Test Conditions
CI/O(4) Input/output capacitance (SDA) 8 pF VI/O = 0V
CIN(4) Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V
Symbol Parameter Min. Typ. Max. Unit
tPUR(5) Power-up to initiation of read operation 1 ms
tPUW(5) Power-up to initiation of write operation 5 ms
tRVCC(6) VCC Power up ramp rate 0.2 50 V/msec
X9418
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AC TIMING (over recommended operating conditions)
Symbol Parameter Min. Max. Unit
fSCL Clock frequency 400 kHz
tCYC Clock cycle time 2500 ns
tHIGH Clock high time 600 ns
tLOW Clock low time 1300 ns
tSU:STA Start setup time 600 ns
tHD:STA Start hold time 600 ns
tSU:STO Stop setup time 600 ns
tSU:DAT SDA data input setup time 100 ns
tHD:DAT SDA data input hold time 30 ns
tRSCL and SDA rise time 300 ns
tF SCL and SDA fall time 300 ns
tAA SCL low to SDA data output valid time 900 ns
tDH SDA data output hold time 50 ns
TINoise suppression time constant at SCL and SDA inputs 50 ns
tBUF Bus free time (prior to any transmission) 1300 ns
tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns
tHD:WPA WP, A0, A1, A2 and A3 hold time 0 ns
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Circuit #3 SPICE Macro Model
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
5V
1533Ω
100pF
SDA Output
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
X9418
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HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
g
Input Timing
Output Timing
Symbol Parameter Typ. Max. Unit
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Unit
tWRPO Wiper response time after the third (last) power supply is stable 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 10 µs
tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
X9418
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XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
SCL
SDA
VW/RW
(STOP)
LSB
tWRL
SCL
SDA
VW/RW
tWRID
Wiper Register Address Inc/Dec Inc/Dec
SDA
SCL ...
...
...
WP
A0, A1
A2, A3
tSU:WPA tHD:WPA
(START) (STOP)
(Any Instruction)
X9418
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APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
VW/RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysteresis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100KΩ
10KΩ10KΩ
10KΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9418
Characteristics subject to change without notice. 17 of 21
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Application Circuits (continued)
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
Attenuator Filter
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2pRC)
R2
R4All RS = 10kΩ
+
–
VS
R2
R1
R
C
VO
X9418
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PACKAGING INFORMATION
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.022 (0.56)
0.014 (0.36)
0.150 (3.81)
0.125 (3.18)
0.625 (15.87)
0.600 (15.24)
0.110 (2.79)
0.090 (2.29)
1.265 (32.13)
1.230 (31.24)
1.100 (27.94)
Ref.
Pin 1 Index
0.162 (4.11)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
Pin 1
Seating
Plane
0.065 (1.65)
0.040 (1.02)
0.557 (14.15)
0.530 (13.46)
0.080 (2.03)
0.065 (1.65)
0°
15°
24-Lead Plastic Dual In-Line Package Type P
Typ. 0.010 (0.25)
NOTE:
X9418
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PACKAGING INFORMATION
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
0.014 (0.35)
0.020 (0.50)
Pin 1
Pin 1 Index
0.050 (1.27)
0.598 (15.20)
0.610 (15.49)
0.003 (0.10)
0.012 (0.30)
0.092 (2.35)
0.105 (2.65)
(4X) 7°
24-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.420"
0.050" Typical
0.050"
Typical
0.030" Typical
24 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.015 (0.40)
0.050 (1.27)
0.009 (0.22)
0.013 (0.33)
0° – 8°
X 45°
X9418
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PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
24-Lead Plastic, TSSOP Package Type V
.169 (4.3)
.177 (4.5).252 (6.4) BSC
.026 (.65) BSC
.303 (7.70)
.311 (7.90)
.002 (.06)
.005 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
See Detail “A”
.031 (.80)
.041 (1.05)
.010 (.25)
.020 (.50)
.030 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16) (7.72)
(1.78)
(0.42)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
0°–8°
X9418
Characteristics subject to change without notice. 21 of 21
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
©Xicor, Inc. 2000 Patents Pending
REV 1.1.5 7/23/02 www.xicor.com
Ordering Information
Device VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1
W = 10KΩ10KΩ
Y = 2.5KΩ2.5KΩ
X9418 P T VY
