AR0237CS AR0237CS 1/2.7inch 2.1 Mp/Full HD Digital Image Sensor The AR0237CS from ON Semiconductor is a 1/2.7-inch CMOS digital image sensor with an active-pixel array of 1928 (H) x 1088 (V). It captures images in either linear or high dynamic range modes, with a rolling-shutter readout. It includes sophisticated camera functions such as in-pixel binning, windowing and both video and single frame modes. It is designed for both low light and high dynamic range scene performance. It is programmable through a simple two-wire serial interface. The AR0237 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and HD video. www.onsemi.com IBGA80 CASE 503BA PLCC48 CASE 776AQ PLCC48 CASE 776AS ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Table 1. KEY PERFORMANCE PARAMETERS Parameter Features Value * Superior Low-light Performance * Latest 3.0 mm pixel with Optical Format 1/2.7-inch (6.6 mm) Active Pixels 1928 (H) x 1088 (V) (16:9 Mode) Pixel Size 3.0 mm x 3.0 mm Color Filter Array RGB Bayer, RGB-IR Shutter Type Electronic Rolling Shutter and GRR Input Clock Range 6-48 MHz Output Clock Maximum 148.5 Mp/s (4-lane HiSPi) 74.25 Mp/s (Parallel) Output Serial Parallel Frame Rate 1080p * * * HiSPi 10-, 12-, 14-, 16-, or 20-bit 10-, 12-bit * 60 fps Linear HiSPi 30 fps Linear Parallel 30 fps Line Interleaved HiSPi 15 fps Line Interleaved Parallel * * * * Responsivity 4.0 V/lux-sec SNRMAX 41 dB Max Dynamic Range Up to 96 dB Supply Voltage I/O Digital Analog HiSPi 1.8 or 2.8 V 1.8 V 2.8 V 0.3-0.6 V (SLVS), 1.7-1.9 V (HiVCM) Power Consumption (Typical) < 300 mW Line Interleaved 1080p30 < 190 mW 1080p30 Linear Mode Operating Temperature -30C to +85C Ambient Package Options 10 x 10 mm 80-pin iBGA 11.43 x 11.43 mm 48-pin mPLCC (c) Semiconductor Components Industries, LLC, 2016 February, 2017 - Rev. 5 * * * * * ON Semiconductor DR-Pixt Technology with Dual Conversion Gain Full HD Support at Up to 1080p 60 fps for Superior Video Performance Linear or High Dynamic Range Capture Supports Line Interleaved T1/T2 Readout to Enable HDR Processing in ISP Chip Support for External Mechanical Shutter On-chip Phase-locked Loop (PLL) Oscillator Integrated Position-based Color and Lens Shading Correction Slave Mode for Precise Frame-rate Control Stereo/3D Camera Support Statistics Engine Data Interfaces: Four-lane Serial High-speed Pixel Interface (HiSPi) Differential Signaling (SLVS and HiVCM), or Parallel Auto Black Level Calibration High-speed Configurable Context Switching Temperature Sensor Applications * Video Surveillance * 1080p60 (Surveillance) Video Applications * High Dynamic Range Imaging 1 Publication Order Number: AR0237CS/D AR0237CS ORDERING INFORMATION Table 2. AVAILABLE PART NUMBERS Part Number Product Description Orderable Product Attribute Description AR0237CSSC00SUEA0-DR 2 Mp 1/2.7 Image Sensor, RGB, 0 CRA, iBGA Package, Multi Output Drypack AR0237CSSC00SHRA0-DR 2 Mp 1/2.7 Image Sensor, RGB, 0 CRA, mPLCC Package, HiSPi Output Drypack AR0237CSSC00SPRA0-DR 2 Mp 1/2.7 Image Sensor, RGB, 0 CRA, mPLCC Package, Parallel Output Drypack AR0237CSSC12SHRA0-DR 2 Mp 1/2.7 Image Sensor, RGB, 12 CRA, mPLCC Package, HiSPi Output Drypack AR0237CSSC12SPRA0-DR 2 Mp 1/2.7 Image Sensor, RGB, 12 CRA, mPLCC Package, Parallel Output Drypack AR0237IRSH12SHRA0-DR-E 2 Mp 1/2.7 Image Sensor, RGB-IR, 12 CRA, mPLCC Package, HiSPi Output Drypack AR0237IRSH12SPRA0-DR-E 2 Mp 1/2.7 Image Sensor, RGB-IR, 12 CRA, mPLCC Package, Parallel Output Drypack AR0237CSSC00SUEAH3-GEVB RGB, 0 CRA, iBGA Package, Multi Output, Headboard Headboard AR0237CSSC00SHRAH3-GEVB RGB, 0 CRA, mPLCC Package, HiSPi Output, Headboard Headboard AR0237CSSC00SPRAH3-GEVB RGB, 0 CRA, mPLCC Package, Parallel Output, Headboard Headboard AR0237CSSC12SHRAH3-GEVB RGB, 12 CRA, mPLCC Package, HiSPi Output, Headboard Headboard AR0237CSSC12SPRAH3-GEVB RGB, 12 CRA, mPLCC Package, Parallel Output, Headboard Headboard AR0237IRSH12SHRAH3-GEVB RGB-IR, 12 CRA, mPLCC Package, HiSPi Output, Headboard Headboard AR0237IRSH12SPRAH3-GEVB RGB-IR, 12 CRA, mPLCC Package, Parallel Output, Headboard Headboard See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 AR0237CS GENERAL DESCRIPTION The AR0237CS from ON Semiconductor can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 1080p-resolution image at 60 frames per second (fps) through the HiSPi port. In linear mode, it outputs 12-bit or 10-bit A-Law compressed raw data, using either the parallel or serial (HiSPi) output ports. In high dynamic range mode, it outputs two exposure values that the ISP will combine into an HDR image. The device may be operated in video (master) mode or in single frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The AR0237 includes additional features to allow application-specific tuning: windowing and offset, auto black level correction, and on-board temperature sensor. Optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. The AR0237CS is designed to operate over a wide temperature range of -30C to +85C ambient. FUNCTIONAL OVERVIEW The AR0237CS is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor configured in linear mode, and in HDR mode. ADC Data 12 Row Noise Correction Black Level Correction Test Pattern Generator Pixel Defect Correction 12 Digital Gain and Pedestal A-Law Compression 10 bits 12 bits HiSPi Parallel Figure 1. Block Diagram of AR0237CS (providing offset correction and gain), and then through an analog-to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The sensor also offers a high dynamic range mode of operation where two images and taken using different exposures. These images are output in from the sensor and the ISP must combine them into one high dynamic range image. User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 2.1 Mp Active-Pixel Sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain www.onsemi.com 3 AR0237CS TYPICAL CONFIGURATIONS 1.5 kW2 1.5 kW2 Digital Digital Core I/O Power1 Power1 VDD_IO VDD HiSPi Power either 0.4 V (SLVS) or 1.8 V (HiVCM)1 VDD_SLVS Analog Analog PLL Power1 Power1 Power1 VDD_PLL VAA VAA_PIX SLVS0_P SLVS0_N SLVS1_P Master Clock (6-48 MHz) EXTCLK SLVS1_N SLVS2_P To Controller SLVS2_N SADDR SDATA SCLK TRIGGER OE_BAR From Controller SLVS3_P SLVS3_N SLVSC_P SLVSC_N RESET_BAR FLASH SHUTTER TEST VDD_IO VDD DGND AGND Digital Ground Analog Ground VDD_SLVS VDD_PLL VAA VAA_PIX Notes: 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed. 3. The parallel interface output pads can be left unconnected if the serial output interface is used. 4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237 demo headboard schematics for circuit recommendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. Figure 2. Serial 4-lane HiSPi Interface www.onsemi.com 4 1.5 kW2 1.5 kW2 AR0237CS Master Clock (6-48 MHz) Digital I/O Power1 Digital Core Power1 PLL Power1 Analog Power1 Analog Power1 VDD_IO VDD VDD_PLL VAA VAA_PIX DOUT[11:0] EXTCLK PIXCLK SADDR SDATA SCLK From Controller To Controller LINE_VALID FRAME_VALID TRIGGER OE_BAR FLASH SHUTTER RESET_BAR TEST VDD_IO VDD DGND AGND Digital Ground Analog Ground VDD_PLL VAA VAA_PIX Notes: 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed. 3. The serial interface output pads can be left unconnected if the parallel output interface is used. 4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237 demo headboard schematics for circuit recommendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 7. The EXTCLK input is limited to 6-48 MHz. Figure 3. Parallel Pixel Data Interface www.onsemi.com 5 AR0237CS PIN DESCRIPTIONS 1 A 2 3 4 5 6 7 8 9 SLVS0_P SLVS1_P SLVSC_P SLVS2_P SLVS3_P VDD VDD_IO VDD B VDD_PLL SLVS0_N SLVS1_N SLVSC_N SLVS2_N SLVS3_N DGND DGND SHUTTER C VAA AGND DGND VDD_ SLVS VDD DGND DGND DGND Reserved D VDD DGND EXTCLK PIXCLK SADDR TRIGGER DGND AGND VAA E VDD_IO DGND SDATA FLASH FRAME_VALID SCLK DGND AGND VAA_PIX F VDD DGND DOUT11 DOUT10 DOUT9 LINE_ VALID Reserved AGND VAA G VAA AGND DGND DOUT8 DOUT7 DOUT6 DGND DGND VDD_IO H VDD_IO DGND DGND DOUT5 DOUT4 DOUT3 RESET_ BAR TEST VDD J DOUT2 VDD_IO DOUT1 DOUT0 VDD DGND VDD_IO OE_BAR VDD_IO Top View (Ball Down) Figure 4. 80-ball iBGA Package Table 3. PIN DESCRIPTIONS, 80-BALL IBGA Name iBGA Pin Type SLVS0_P A2 Output HiSPi serial data, lane 0, differential P Description SLVS1_P A3 Output HiSPi serial data, lane 1, differential P SLVSC_P A4 Output HiSPi serial DDR clock differential P SLVS2_P A5 Output HiSPi serial data, lane 2, differential P SLVS3_P A6 Output HiSPi serial data, lane 3, differential P VDD_PLL B1 Power PLL power SLVS0_N B2 Output HiSPi serial data, lane 0, differential N www.onsemi.com 6 AR0237CS Table 3. PIN DESCRIPTIONS, 80-BALL IBGA (continued) Name iBGA Pin Type Description SLVS1_N B3 Output HiSPi serial data, lane 1, differential N SLVSC_N B4 Output HiSPi serial DDR clock differential N SLVS2_N B5 Output HiSPi serial data, lane 2, differential N SLVS3_N B6 Output HiSPi serial data, lane 3, differential N SHUTTER B9 Output Control for external mechanical shutter. Can be left floating if not used VAA C1, G1, D9, F9 Power Analog power AGND C2, G2, D8, E8, F8 Power Analog ground VDD_SLVS C4 Power SLVS power 0.4 V/1.8 V depending on how R0x306E[9] is set. 0 = 0.4 V; 1 = 1.8 V Power Digital power Digital ground VDD C5, J5, A9, H9, A7, D1, F1 Reserved C9, F7 DGND B7, C7, D7, E7, G7, B8, C8, G8, D2, E2, F2, H2, C3, G3, H3, C6, J6 Power EXTCLK D3 Input PIXCLK D4 Output SADDR D5 Input Two-wire Serial address select. 0: 0x20. 1: 0x30 TRIGGER D6 Input Exposure synchronization input VAA_PIX E9 Power Pixel power VDD_IO E1, H1, J2, J7, A8, G9, J9 Power I/O supply power SDATA E3 I/O External input clock Pixel clock out. DOUT is valid on rising edge of this clock Two-wire Serial data I/O FLASH E4 Output Flash control output FRAME_VALID E5 Output Asserted when DOUT frame data is valid SCLK E6 Input DOUT11 F3 Output Parallel pixel data output (MSB) DOUT10 F4 Output Parallel pixel data output DOUT9 F5 Output Parallel pixel data output LINE_VALID F6 Output Asserted when DOUT line data is valid DOUT8 G4 Output Parallel pixel data output DOUT7 G5 Output Parallel pixel data output DOUT6 G6 Output Parallel pixel data output DOUT5 H4 Output Parallel pixel data output DOUT4 H5 Output Parallel pixel data output Parallel pixel data output Two-wire Serial clock input DOUT3 H6 Output RESET_BAR H7 Input Asynchronous reset (active LOW). All settings are restored to factory default Manufacturing test enable pin (connect to DGND) TEST H8 Input DOUT2 J1 Output Parallel pixel data output DOUT1 J3 Output Parallel pixel data output DOUT0 J4 Output Parallel pixel data output (LSB) OE_BAR J8 Input Output enable (active LOW) www.onsemi.com 7 VDD SLVS3_P SLVS3_N SLVS2_P SLVS2_N SLVSC_P SLVSC_N SLVS1_P SLVS1_N SLVS0_P SLVS0_N VDD_SLVS AR0237CS 6 43 7 42 5 DGND 4 3 2 1 47 46 45 44 VDD_IO 48 VDD_PLL 8 41 VDD EXTCLK 9 40 DGND VAA 10 39 AGND AGND 11 38 VAA_PIX VDD_IO 12 37 VAA VDD 13 36 Reserved DGND 14 35 VAA Reserved 15 34 VAA_PIX VAA 16 33 AGND AGND 17 32 DGND 36x Thermal Connection Pads DGND DGND DGND DGND DGND DGND DGND DGND 20 21 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND 22 DGND DGND DGND 23 24 25 26 DGND 27 28 VDD 29 18 31 19 VDD_IO SHUTTER TRIGGER OE_BAR RESET_BAR SCLK SADDR SDATA TEST FLASH VDD_IO VDD 30 Figure 5. 48-pin mPLCC Package HiSPi (Top Side View) Table 4. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI Pin Name Type Description 1 SLVSC_N Output HiSPi serial DDR clock differential N 2 SLVS1_P Output HiSPi serial data, lane 1, differential P 3 SLVS1_N Output HiSPi serial data, lane 1, differential N 4 SLVS0_P Output HiSPi serial data, lane 0, differential P 5 SLVS0_N Output HiSPi serial data, lane 0, differential N 6 VDD_SLVS Power SLVS Power 0.4 V/1.8 V depending on how R0x306E[9] is set. 0 = 0.4 V; 1 = 1.8 V 7 DGND Power Digital ground www.onsemi.com 8 AR0237CS Table 4. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI (continued) Pin Name Type Description 8 VDD_PLL Power 9 EXTCLK Input 10 VAA Power Analog Power PLL power External input clock 11 AGND Power Analog Ground 12 VDD_IO Power I/O Power Supply 13 VDD Power Digital Power 14 DGND Power Digital ground 15 Reserved 16 VAA Power Analog Power 17 AGND Power Analog Ground 18 DGND Power Digital ground 19 VDD Power Digital Power 20 VDD_IO Power I/O Power Supply 21 FLASH Output Flash control output 22 TEST Input Manufacturing test enable pin (connect to DGND) 23 SDATA I/O 24 SADDR Input Two-wire Serial data I/O Two-wire Serial address select. 0: 0x20, 1: 0x30 25 SCLK Input Two-wire Serial clock input 26 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default 27 OE_BAR Input Output enable (active LOW) 28 TRIGGER Input Exposure synchronization input 29 SHUTTER Output Control for external mechanical shutter. Can be left floating if not used. 30 VDD_IO Power I/O Power Supply 31 VDD Power Digital Power 32 DGND Power Digital ground 33 AGND Power Analog Ground 34 VAA_PIX Power Pixel Power 35 VAA Power Analog Power 36 Reserved 37 VAA Power Analog Power 38 VAA_PIX Power Pixel Power 39 AGND Power Analog Ground 40 DGND Power Digital ground 41 VDD Power Digital Power 42 VDD_IO Power I/O Power Supply 43 VDD Power Digital Power 44 SLSV3_P Output HiSPi serial data, lane 3, differential P 45 SLVS3_N Output HiSPi serial data, lane 3, differential N 46 SLVS2_P Output HiSPi serial data, lane 2, differential P 47 SLVS2_N Output HiSPi serial data, lane 2, differential N 48 SLVSLC_P Output HiSPi serial DDR clock differential P www.onsemi.com 9 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 DOUT10 DOUT11 AR0237CS 6 43 7 42 5 DGND 4 3 2 1 47 46 45 VDDIO2V8 R1V8 44 48 VDDIO2V8 R1V8_PLL 8 41 DVDD1V8 EXTCLK 9 40 DGND VAA2V8 10 39 AGND AGND 11 38 VAA2V8_PIX 37 VAA2V8 36 AGND 29x Thermal Connection Pads DGND DGND DGND VDDIO2V8 R1V8 12 VDD1V8 13 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND 14 35 Reserved Reserved 15 34 SHUTTER VAA2V8 16 33 TRIGGER AGND 17 32 OUTPUT_ ENABLE_N DVDD1V8 20 21 22 23 24 25 26 27 28 RESET_N 29 18 31 19 Figure 6. 48-pin mPLCC Package Parallel (Top Side View) Table 5. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI Pin Name Type 1 DOUT6 Output Data output 6 2 DOUT7 Output Data output 7 3 DOUT8 Output Data output 8 4 DOUT9 Output Data output 9 5 DOUT10 Output Data output 10 6 DOUT11 Power Data output 11 7 DGND Power Digital ground 8 VDD_PLL Power PLL power Description www.onsemi.com 10 DVDD1V8 VDDIO2V8 R1V8 SCLK SADDR LINE_VALID SDATA DGND TEST FRAME_VALID PIXCLK FLASH VDDIO2V8 R1V8 30 AR0237CS Table 5. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI (continued) Pin Name Type Description 9 EXTCLK Input 10 VAA Power Analog Power 11 AGND Power Analog Ground 12 VDD_IO Power I/O Power Supply 13 VDD Power Digital Power 14 DGND Power Digital ground 15 Reserved 16 VAA Power Analog Power 17 AGND Power Analog Ground 18 VDD Power Digital Power 19 VDD_IO Power I/O Power Supply 20 FLASH Power Flash control output 21 PIXCLK Output Pixel Clock 22 FRAME_VALID Output Frame Valid 23 TEST Input 24 DGND Power 25 SDATA I/O 26 LINE_VALID Output 27 SADDR Input Two-wire Serial address select. 0: 0x20, 1: 0x30 28 SCLK Input Two-wire Serial clock input 29 VDD_IO Power I/O Power Supply 30 VDD Power Digital Power 31 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default 32 OE_BAR Input Output enable (active LOW) 33 TRIGGER Input Exposure synchronization input 34 SHUTTER Output 35 Reserved Input 36 AGND Power Analog Ground 37 VAA_2V8 Power Analog Power 38 VAA_PIX Power Pixel Power 39 AGND Power Analog Ground 40 DGND Power Digital ground 41 VDD Power Digital Power 42 VDD_IO Power I/O Power Supply 43 DOUT0 Output Data Output 0 44 DOUT1 Output Data Output 1 45 DOUT2 Output Data Output 2 46 DOUT3 Output Data Output 3 47 DOUT4 Output Data Output 4 48 DOUT5 Output Data Output 5 External input clock Manufacturing test enable pin (connect to DGND) Digital Ground Two-wire Serial data I/O Line Valid Control for external mechanical shutter. Can be left floating if not used. www.onsemi.com 11 AR0237CS PIXEL DATA FORMAT Pixel Array Structure While the sensor's format is 1928 x 1088, additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is always performed for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. 1944 2 Barrier + 6 Border Pixels 1928 x 1088 5.78 x 3.26 mm 2 Barrier + 6 Border Pixels 10 Barrier + 4 Border Pixels Light Dummy Pixel Active Pixel Figure 7. Pixel Array Description ... Column Readout Direction Active Pixel (0, 0) Array Pixel (0, 0) Row Readout Direction 1116 10 Barrier + 4 Border Pixels ... R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B Figure 8. Pixel Color Pattern Detail (RGB) (Top Right Corner) www.onsemi.com 12 AR0237CS ... Column Readout Direction Row Readout Direction Active Pixel (0, 0) Array Pixel (0, 0) B G R G B G R G G IR G IR G IR G IR ... R G B G R G B G G IR G IR G IR G IR Figure 9. Pixel Color Pattern Detail (RGB-IR) (Top Right Corner) Default Readout Order By convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see Figure 8). This reflects the actual layout of the array on the die. Also, the first pixel data read out of the sensor in default condition is that of pixel (10, 14). When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 10. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 10. Lens Scene Sensor (Rear View) Row Readout Order Column Readout Order Pixel (0,0) Figure 10. Imaging a Scene www.onsemi.com 13 AR0237CS FEATURES OVERVIEW For a complete description, recommendations, and usage guidelines for product features, refer to the AR0237 Developer Guide. 3.0 mm Dual Conversion Gain Pixel To improve the low light performance and keep the high dynamic range, a large (3.0 mm) dual conversion gain pixel is implemented for better image optimization. With a dual conversion gain pixel, the conversion gain of the pixel may be dynamically changed to better adapt the pixel response based on dynamic range of the scene. * HDR By default, the sensor powers up in Linear Mode. One can change to HDR Mode. The HDR scheme used is multi-exposure HDR. This allows the sensor to handle up to 96 dB of dynamic range. In HDR mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. The exposure ratio may be set to 4x, 8x, 16x, or 32x. Sensor also provides flexibility to choose any exposure ratio by setting number of t2 exposure rows independent of the t1 exposure. The data will be output as line interleaved data as described in the T1/T2 Line Interleaved Mode section. There is also an option to output either T1 only or T2 only. Embedded Data and Statistics The AR0237 has the capability to output image data and statistics embedded within the frame timing. There are two types of information embedded within the frame readout. * Embedded Data: If enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. * Embedded Statistics: If enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. Resolution The active array supports a maximum of 1928 x 1088 pixels to support 1080p resolution. Utilizing a 3.0um pixel will result in an optical format of 1/2.7-inch (approximately 6.6 mm diagonal). Multi-Camera Synchronization Frame Rate The AR0237 supports advanced line synchronization controls for multi-camera (stereo) support. At full (1080p) resolution, the AR0237 is capable of running up to 60 fps in linear mode and 30 fps in line interleaved mode. Slave Mode The slave mode feature of the AR0237 supports triggering the start of a frame readout from an input signal that is supplied from an external ASIC. The slave mode signal allows for precise control of frame rate and register change updates. Image Acquisition Mode * and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0237 switches cleanly from the old integration time to the new while only generating frames with uniform integration. See "Changes to Integration Time" in the AR0237 Register Reference. Global Reset Mode: This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0237 provides control signals to interface to that shutter. The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. The AR0237 supports two image acquisition modes: Electronic Rolling Shutter (ERS) Mode: This is the normal mode of operation. When the AR0237 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When ERS mode is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing Context Switching and Register Updates The user has the option of using the highly configurable context memory, or a simplified implementation in which only a subset of registers is available for switching. The AR0237 supports a highly configurable context switching RAM of size 256 x 16. Within this Context Memory, changes to any register may be stored. The register set for each context must be the same, but the number of contexts and registers per context are limited only by the size of the context memory. Alternatively, the user may switch between two predefined register sets A and B by writing to a context switch change bit. When the context switch is configured to www.onsemi.com 14 AR0237CS context A the sensor will reference the context A registers. If the context switch is changed from A to B during the readout of frame n, the sensor will then reference the context B coarse_integration_time registers in frame n+1 and all other context B registers at the beginning of reading frame n+2. The sensor will show the same behavior when changing from context B to context A. The registers listed in Table 6 are context-switchable: Table 6. LIST OF CONFIGURABLE RESISTORS FOR CONTEXT A AND CONTEXT B Context A Register Description Context B Register Description coarse_integration_time coarse_integration_time_cb line_length_pck line_length_pck_cb frame_length_lines frame_length_lines_cb row_bin row_bin_cb col_bin col_bin_cb fine_gain fine_gain_cb coarse_gain coarse_gain_cb coarse_integration_time2 coarse_integration_time2_cb dcg_manual_set dcg_manual_set_cb dcg_manual_set_t1 dcg_manual_set_t1_cb bypass_pix_comb bypass_pix_cb coarse_gain_t1 coarse_gain_t1_cb fine_gain_t1 fine_gain_t1_cb x_addr_start x_addr_start_cb y_addr_start y_addr_start_cb x_addr_end x_addr_end_cb y_addr_end y_addr_end_cb y_odd_inc y_odd_inc_cb x_odd_inc x_odd_inc_cb green1_gain green1_gain_cb blue_gain blue_gain_cb red_gain red_gain_cb green2_gain green2_gain_cb global_gain global_gain_cb operation_mode_ctrl operation_mode_ctrl_cb bypass_pix_comb bypass_pix_comb_cb Analog/Digital Gains readout. The sensor will sample the combined 2x adjacent pixels within the same color plane. Vertical row binning is applied in the pixel readout. Row binning can be configured as 2x rows within the same color plane. Pixel skipping can be configured up to 2x in both the x-direction and y-direction. Skipping pixels in the x-direction will not reduce the row time. Skipping pixels in the y direction will reduce the number of rows from the sensor effectively reducing the frame time. Skipping will introduce image artifacts from aliasing. The AR0237 supports row wise vertical binning. Row wise vertical summing is only supported in monochrome sensors. Binning and summing is not supported with RGB IR sensors. A programmable analog gain of 1.0x to 16x (linear and HDR) applied simultaneously to all color channels will be featured along with a digital gain of 1x to 16x that may be configured on a per color channel basis. Note that with the RGB IR sensor digital gain should only be applied to all color channels equally since with the 4 x 4 kernel the gains will not be applied to the proper color channel. Analog gain can be applied per exposure in line interleaved mode. Skipping/Binning Modes The AR0237 supports subsampling. Subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. Horizontal binning is achieved in the digital www.onsemi.com 15 AR0237CS * PIXCLK * DOUT[11:0] Clocking Options The sensor contains a phase-locked loop (PLL) that is used for timing generation and control. The required VCO clock frequency is attained through the use of a pre-PLL clock divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an even multiplier value. The multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. Use of the PLL is required when using the HiSPi interface. The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. High Speed Serial Pixel (HiSPi) Interface The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. The AR0237 supports serial data widths of 10 or 12 bits on one, two, or four lanes. The specification includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in PCB design. Delay compensation may be set for clock and/or data lines in the hispi_timing register R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x0000 to reduce jitter, skew, and power dissipation. Temperature Sensor The AR0237 sensor has a built-in PTAT-based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function can be used to convert the ADC output value to the final temperature in degrees Celsius. A single reference point will be made available via register read as well as a slope for back-calculating the junction temperature value. An error of 5% or better over the full specified operating range of the sensor is to be expected. Silicon/Firmware/Sequencer Revision Information A revision register will be provided to read out (via I2C) silicon and sequencer/OTPM revision information. This will be helpful to distinguish among different lots of material if there are future OTPM or sequencer revisions. Sensor Control Interface The two-wire serial interface bus enables read/write access to control and status registers within the AR0237. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5 kW resistor. Either the slave or master device can drive SDATA LOW - the interface protocol determines which device is allowed to drive SDATA at any given time. The two-wire serial interface can run at 100 kHz or 400 kHz. Lens Shading Correction The latest lens shading correction algorithm will be included for potential low Z height applications. Compression When the AR0237 is configured for linear mode operation, the sensor can optionally compress 12-bit data to 10-bit using A-law compression. The A-law compression is disabled by default. Packaging The AR0237 will be offered in a 10 x 10 80-iBGA package (parallel and HiSPi) and a 11.43 x 1143 48 pin mPLCC (HiSSPi) package. T1/T2 Line Interleaved Mode Parallel Interface The AR0237 outputs the T1 and T2 exposures separately, in a line interleaved format. The purpose of this is to enable off chip HDR linear combination and processing. See the AR0237 Developer Guide for more information. The parallel pixel data interface uses these output-only signals: * FRAME_VALID * LINE_VALID www.onsemi.com 16 AR0237CS 70 Red 60 Green (R) Green (B) Quantum Efficiency (%) 50 Blue 40 30 20 10 0 350 450 550 650 750 850 950 1050 1150 Wavelength (nm) Figure 11. Quantum Efficiency - RGB Packaged Part 70 Red 60 Green (R) Green (B) Quantum Efficiency (%) 50 Blue IR 40 30 20 10 0 350 450 550 650 750 850 950 Wavelength (nm) Figure 12. Quantum Efficiency - RGB-IR Packaged Part www.onsemi.com 17 1050 1150 AR0237CS CRA vs. Image Height Plot AR0237 CRA Characteristic 16 14 Chief Ray Angle (Deg) 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 Image Height (%) Figure 13. Chief Ray Angle Characteristics www.onsemi.com 18 90 100 110 Image Height CRA (%) (mm) (deg) 0 0 0 5 0.166 0.62 10 0.332 1.24 15 0.498 1.86 20 0.664 2.48 25 0.830 3.10 30 0.996 3.72 35 1.162 4.34 40 1.328 4.96 45 1.494 5.58 50 1.660 6.20 55 1.826 6.82 60 1.992 7.44 65 2.158 8.06 70 2.324 8.68 75 2.491 9.30 80 2.657 9.92 85 2.823 10.54 90 2.989 11.16 95 3.155 11.78 100 3.321 12.40 AR0237CS ELECTRICAL SPECIFICATIONS Unless otherwise stated, the following specifications apply under the following conditions: VDD = 1.8 V - 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V 0.3 V; VDD_SLVS = 0.4 V - 0.1/+0.2; TA = -30C to +85C-40C to +105C; Output load = 10 pF; Frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 14 and Table 7. SDATA tLOW tf tSU;DAT tr tf tHD;STA tBUF tr SCLK tSU;STA tHD;STA tHD;DAT S NOTE: tHIGH tSU;STO Sr P S Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Figure 14. Two-Wire Serial Bus Timing Parameters Table 7. TWO-WIRE SERIAL BUS CHARACTERISTICS (fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25C) Standard Mode Fast Mode Symbol Min Max Min Max Unit fSCL 0 100 0 400 kHz Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated tHD;STA 4.0 - 0.6 - ms LOW Period of the SCLK Clock tLOW 4.7 - 1.3 - ms HIGH Period of the SCLK Clock tHIGH 4.0 - 0.6 - ms Set-up Time for a Repeated START Condition tSU;STA 4.7 - 0.6 - ms Data Hold Time tHD;DAT 0 (Note 4) 3.45 (Note 5) 0 (Note 6) 0.9 (Note 5) ms Data Set-up Time tSU;DAT 250 - 100 (Note 6) - ns Rise Time of both SDATA and SCLK Signals tr - 1000 20 + 0.1 Cb (Note 7) 300 ns Fall Time of both SDATA and SCLK Signals tf - 300 20 + 0.1 Cb (Note 7) 300 ns Set-up Time for STOP Condition tSU;STO 4.0 - 0.6 - ms Bus Free Time between a STOP and START Condition tBUF 4.7 - 1.3 - ms Cb - 400 - 400 pF CIN_SI - 3.3 - 3.3 pF Parameter SCLK Clock Frequency Capacitive Load for each Bus Line Serial Interface Input Pin Capacitance www.onsemi.com 19 AR0237CS Table 7. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued) (fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25C) Standard Mode Parameter SDATA Max Load Capacitance Fast Mode Symbol Min Max Min Max Unit CLOAD_SD - 30 - 30 pF RSD 1.5 4.7 1.5 4.7 kW SDATA Pull-up Resistor I2C 1. 2. 3. 4. 5. 6. This table is based on standard (v2.1 January 2000). Philips Semiconductor. Two-wire control is I2C-compatible. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1 VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. I/O Timing By default, the AR0237 launches pixel data, FV, and LV with the falling edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of PIXCLK. tR See Figure 15 below and Table 8 for I/O timing (AC) characteristics. tF 90% 10% tRP 90% tFP 90% 10% 10% 90% 10% tEXTCLK EXTCLK PIXCLK tPD Data[11:0] Pxl_0 Pxl_1 Pxl_2 Pxl_n tPFL tPLL tPLH tPFH LINE_VALID/ FRAME_VALID FRAME_VALID Leads LINE_VALID by 6 PIXCLKs FRAME_VALID Trails LINE_VALID by 6 PIXCLKs Figure 15. I/O Timing Diagram Table 8. I/O TIMING CHARACTERISTICS (I/O timing characteristics are measured under the following conditions: Temperature is 25C Ambient; 10 pF Load; 1.8 V I/O Supply Voltage) Symbol Definition fEXTCLK1s Input Clock Frequency tEXTCLK1 Input Clock Period Condition Min Typ Max Unit 6 - 48 MHz 20.8 - 166 ns tR Input Clock Rise Time - 3 - ns tF Input Clock Fall Time - 3 - ns tRP Pixclk Rise Time 2 3.5 5 ns tFP Pixclk Fall Time 2 3.5 5 ns Clock Duty Cycle 45 50 55 % tCP fPIXCLK EXTCLK to PIXCLK Propagation Delay Nominal Voltages, PLL Disabled 10 14 18 ns PIXCLK Frequency Default, Nominal Voltages 6 - 74.25 MHz www.onsemi.com 20 AR0237CS Table 8. I/O TIMING CHARACTERISTICS (continued) (I/O timing characteristics are measured under the following conditions: Temperature is 25C Ambient; 10 pF Load; 1.8 V I/O Supply Voltage) Symbol Definition Condition Min Typ Max Unit tPD PIXCLK to Data Valid Default, Nominal Voltages 0 2.5 5 ns tPFH PIXCLK to FV HIGH Default, Nominal Voltages -2 3 6 ns tPLH PIXCLK to LV HIGH Default, Nominal Voltages -2 3 6 ns tPFL PIXCLK to FV LOW Default, Nominal Voltages -2 2.5 6 ns tPLL PIXCLK to LV LOW Default, Nominal Voltages -2 2.5 6 ns Output Load Capacitance - < 10 - pF Input Pin Capacitance - 2.5 - pF CLOAD CIN DC Electrical Characteristics The DC electrical characteristics are shown in the tables below. Table 9. DC ELECTRICAL CHARACTERISTICS Symbol Min Typ Max Unit 1.7 1.8 1.95 V 1.7/2.5 1.8/2.8 1.9/3.1 V Analog Voltage 2.5 2.8 3.1 V VAA_PIX Pixel Supply Voltage 2.5 2.8 3.1 V VDD_PLL PLL Supply Voltage 2.5 2.8 3.1 V HiSPi Supply Voltage 0.3 0.4 0.6 V VDD Definition Condition Core Digital Voltage VDD_IO VAA VDD_SLVS I/O Digital Voltage VIH Input HIGH Voltage VDD_IO x 0.7 - - V VIL Input LOW Voltage - - VDD_IO x 0.3 V IIN Input leakage Current 20 - - mA VOH Output HIGH Voltage VDD_IO - 0.3 - - V VOL Output LOW Voltage - - 0.4 V IOH Output HIGH Current At Specified VOH -22 - - mA IOL Output LOW Current At Specified VOL - - 22 mA No Pull-up Resistor; VIN = VDD_IO or DGND Table 10. ABSOLUTE MAXIMUM RATINGS Symbol VDD_MAX VDD_IO_MAX Min Max Unit Core Digital Voltage Definition Condition -0.3 2.4 V I/O Digital Voltage -0.3 4 V VAA_MAX Analog Voltage -0.3 4 V VAA_PIX Pixel Supply Voltage -0.3 4 V VDD_PLL PLL Supply Voltage -0.3 4 V HiSPi I/O Digital Voltage -0.3 2.4 V Storage Temperature -40 85 C VDD_SLVS_MAX tST Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 21 AR0237CS Table 11. 1080p30 LINEAR 74 MHZ PARALLEL 2.8 V (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = VDD_IO = 2.8 V; VDD = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; Low power mode enabled; TA = 25C) Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 20 34 50 mA I/O Digital Operating Current Streaming 1080p30 IDD_IO 2.8 15 28 50 mA Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 5.5 6.4 7 mA Power 138.2 238.72 409.2 mW Table 12. 1080p30 LINEAR 74 MHZ PARALLEL 1.8 V (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; Low power mode enabled; TA = 25C Dark Image, 8x Analog Gain, HCG, 20 ms integration time) Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 20 34 50 mA I/O Digital Operating Current Streaming 1080p30 IDD_IO 1.8 10 14 30 mA Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 5.5 6.4 7 mA Power 114.2 185.52 323.2 mW Table 13. 1080p30 LINEAR 74 MHZ HISPI SLVS (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V; VDD_SLVS = 0.4 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; Low power mode enabled; TA = 25C Dark Image, 8x Analog Gain, HCG, 20 ms integration time) Definition Condition Symbol Voltage Min Typ Max Unit IDD 1.8 25 44 65 mA Digital Operating Current Streaming 1080p30 Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 6 7.5 8.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 0.4 6 9.5 14 mA Power 109 185.2 306 mW Table 14. 1080p30 LINEAR 74 MHZ HISPI HIVCM (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = VDD_SLVS = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; Low power mode enabled; TA = 25C Dark Image, 8x Analog Gain, HCG, 20 ms integration time) Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 25 44 65 mA Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 6 7.5 8.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 1.8 12 20 35 mA Power 128.2 217.4 363.4 mW www.onsemi.com 22 AR0237CS Table 15. 1080p60 LINEAR 74 MHZ LINEAR SLVS (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V; VDD_SLVS = 0.4 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25C Dark Image, 8x Analog Gain, HCG, 20 ms integration time) Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p60 IDD 1.8 50 88 130 mA Analog Operating Current Streaming 1080p60 IAA 2.8 20 36 60 mA Pixel Supply Current Streaming 1080p60 IAA_PIX 2.8 1 4 8 mA PLL Supply Current Streaming 1080p60 IDD_PLL 2.8 7 8.5 9.5 mA SLVS Supply Current Streaming 1080p60 IDD_SLVS 0.4 6 9.5 14 mA Power 170.8 298 442.6 mW Table 16. 1080p60 LINEAR 74 MHZ LINEAR HIVCM (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V; VDD_SLVS = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25C Dark Image, 8x Analog Gain, HCG, 20 ms integration time) Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p60 IDD 1.8 50 88 130 mA Analog Operating Current Streaming 1080p60 IAA 2.8 20 36 60 mA Pixel Supply Current Streaming 1080p60 IAA_PIX 2.8 1 4 8 mA PLL Supply Current Streaming 1080p60 IDD_PLL 2.8 7 8.5 9.5 mA SLVS Supply Current Streaming 1080p60 IDD_SLVS 1.8 12 20 35 mA Power 190 330.2 500 mW Table 17. 1080p30 LINEAR 74 MHZ LINE INTERLEAVED SLVS (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V; VDD_SLVS = 0.4 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25C Dark Image, 8x Analog Gain, HCG, 20 ms integration time) Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 50 88 130 mA Analog Operating Current Streaming 1080p30 IAA 2.8 20 36 60 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 4 8 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 7 8.5 9.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 0.4 6 9.5 14 mA Power 170.8 298 442.6 mW Table 18. 1080p30 LINEAR 74 MHZ LINE INTERLEAVED HIVCM (Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V; VDD_SLVS = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25C Dark Image, 8x Analog Gain, HCG, 20 ms integration time) Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 50 88 130 mA Analog Operating Current Streaming 1080p30 IAA 2.8 20 36 60 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 4 8 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 7 8.5 9.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 1.8 12 20 35 mA Power 190 330.2 500 mW www.onsemi.com 23 AR0237CS HiSPi Electrical Specifications corresponds to VDD_TX in the HiSPi Physical Layer Specification. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. The DLL as implemented on AR0237 is limited in the number of available delay steps and differs from the HiSPi specification as described in this section. The ON Semiconductor AR0237 sensor supports both SLVS and HiVCM HiSPi modes. Refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS supply in this datasheet Table 19. CHANNEL SKEW (Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.4 V; Data Rate = 480 Mbps; DLL set to 0) Definition Data Lane Skew in Reference to Clock Symbol Value Unit tCHSKEW1PHY -150 ps www.onsemi.com 24 AR0237CS POWER-ON RESET AND STANDBY TIMING Power-Up Sequence 6. After the last power supply is stable, enable EXTCLK. 7. Assert RESET_BAR for at least 1 ms. The parallel interface will be tri-stated during this time. 8. Wait 15,0000 EXTCLKs (for internal initialization into software standby. 9. Configure PLL, output, and image settings to desired values. 10. Wait 1 ms for the PLL to lock. 11. Set streaming mode (R0x301a[2] = 1). The recommended power-up sequence for the AR0237 is shown in Figure 16. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply. 2. After 100 ms, turn on VAA and VAA_PIX power supply. 3. After 100 ms, turn on VDD_IO power supply. 4. After 100 ms, turn on VDD power supply. 5. After 100 ms, turn on VDD_SLVS power supply. VDD_PLL (2.8) t0 VAA_PIX VAA (2.8) t1 VDD_IO (1.8/2.8) t2 VDD (1.8) t3 VDD_SLVS (0.4) EXTCLK t4 RESET_BAR t5 tX Hard Reset t6 Internal Initialization Software Standby PLL Lock Streaming Figure 16. Power Up Table 20. POWER-UP SEQUENCE Symbol Definition Min Typ Max Unit t0 VDD_PLL to VAA/VAA_PIX (Note 3) 0 100 - ms t1 VAA/VAA_PIX to VDD_IO 0 100 - ms t2 VDD_IO to VDD 0 100 - ms t3 VDD to VDD_SLVS 0 100 - ms tX Xtal Settle Time t4 Hard Reset t5 Internal Initialization t6 PLL Lock Time - 30 (Note 1) - ms 1 (Note 2) - - ms 150000 - - EXTCLKs 1 - - ms 1. Xtal settling time is component-dependent, usually taking about 10-100 ms. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then the sensor may have functionality issues and will experience high current draw on this supply. www.onsemi.com 25 AR0237CS Power-Down Sequence The recommended power-down sequence for the AR0237 is shown in Figure 17. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0. 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Turn off VDD_SLVS. 4. Turn off VDD. 5. Turn off VDD_IO. 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL. VDD_SLVS (0.4) t0 VDD (1.8) t1 VDD_IO (1.8/2.8) t2 VAA_PIX VAA (2.8) t3 VDD_PLL (2.8) EXTCLK t4 Power Down until Next Power Up Cycle Figure 17. Power Down Table 21. POWER-DOWN SEQUENCE Symbol Parameter Min Typ Max Unit t0 VDD_SLVS to VDD 0 - - ms t1 VDD to VDD_IO 0 - - ms t2 VDD_IO to VAA/VAA_PIX 0 - - ms t3 VAA/VAA_PIX to VDD_PLL 0 - - ms t4 Power Down until Next Power Up Time 100 - - ms 1. t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. www.onsemi.com 26 AR0237CS PACKAGE DIMENSIONS IBGA80 10x10 CASE 503BA ISSUE O www.onsemi.com 27 AR0237CS PACKAGE DIMENSIONS PLCC48 11.43x11.43 (HiSPi) CASE 776AQ ISSUE C www.onsemi.com 28 AR0237CS PACKAGE DIMENSIONS PLCC48 11.43x11.43 (Parallel) CASE 776AS ISSUE O DR-Pix is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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