XC4000XV: Electrical Characteristics - Xilinx, Inc.

May 14, 1999 (Version 1.2) 6-187

XC4000XLA/XV Field Programmable Gate Arrays

XV Speciﬁcation Information

Deﬁnition of Terms

In the following tables, some speciﬁcations may be designated as Advance or Preliminary. These terms are deﬁned as

follows:

Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families.

Values are subject to change. Use as estimates, not for production.

Preliminary: Based on preliminary characterization. Further changes are not expected.

Unmarked: Speciﬁcations not identiﬁed as either Advance or Preliminary are to be considered Final.

Except for pin-to-pin input and output parameters, the a.c. parameter delay speciﬁcations included in this document are

derived from measuring internal test patterns. All speciﬁcations are representative of worst-case supply voltage and junction

temperature conditions.

All speciﬁcations subject to change without notice.

XC4000XV D.C. Characteristics

Absolute Maximum Ratings

Symbol Description Value Units

VCCINT Supply voltage relative to GND -0.5 to 3.0 V

VCCIO Supply voltage relative to GND -0.5 to 4.0 V

VIN Input voltage relative to GND (Note 1) -0.5 to 5.5 V

VTS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V

VCC Longest Supply Voltage Rise Time from 1 V to 3V 50 ms

TSTG Storage temperature (ambient) -65 to +150 °C

TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C

TJJunction temperature Ceramic packages +150 °C

Plastic packages +125 °C

Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to

achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot toVCC + 2.0 V, provided this over or

undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended

periods of time may affect device reliability.

XC4000XLA/XV Field Programmable Gate Arrays

6-188 May 14, 1999 (Version 1.2)

Recommended Operating Conditions

DC Characteristics Over Recommended Operating Conditions

Symbol Description Min Max Units

VCCINT

Supply voltage relative to GND, TJ=0°C to +85°C Commercial 2.3 2.7 V

Supply voltage relative to GND, TJ = -40°C to

+100°CIndustrial 2.3 2.7 V

VCCIO

Supply voltage relative to GND, TJ=0°C to +85°C Commercial 3.0 3.6 V

Supply voltage relative to GND, TJ = -40°C to

+100°CIndustrial 3.0 3.6 V

VIH High-level input voltage 50% of VCC 5.5 V

VIL Low-level input voltage 0 30% of VCC V

TIN Input signal transition time 250 ns

Notes: At junction temperatures above those listed above, all delay parameters increase by 0.35% per °C.

Input and output measurement threshold is ~50% of VCC.

Symbol Description Min Max Units

VOH High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) 2.4 V

High-level output voltage @ IOH = -500 µA, (LVCMOS) 90% VCC V

VOL Low-level output voltage @ IOL = 24.0 mA, VCC min (LVTTL) (Note 1) 0.4 V

Low-level output voltage @ IOL = 1500 µA, (LVCMOS) 10% VCC V

VDRINT VCCINT Data Retention Supply Voltage (below which configuration data may be

lost) 2.1 V

VDRIO VCCIO Data Retention Supply Voltage (below which configuration data may be

lost) 2.5 V

ICCO Quiescent FPGA supply current (Note 2) 10 mA

ILInput or output leakage current -10 +10 µA

CIN Input capacitance (sample tested) BGA, SBGA, PQ, HQ, & MQ packages 10 pF

PGA packages 16 pF

IRPU Pad pull-up (when selected) @ Vin = 0 V (sample tested) 0.02 0.25 mA

IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) 0.02 0.15 mA

IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA

Note 1: With up to 64 pins simultaneously sinking 24 mA.

Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and ﬂoating.

May 14, 1999 (Version 1.2) 6-189

XC4000XLA/XV Field Programmable Gate Arrays

XC4000XV Switching Characteristics Guidelines

Testing of the switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are

representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB ﬂip-ﬂops are clocked by the global clock net.

When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven

from the same global clock, the delay is longer. For more speciﬁc, more precise, and worst-case guaranteed data, reﬂecting

the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)

and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static

timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction

temperature).

Global Buffer Switching Characteristics Guidelines

Speed Grade All -09 -08 -07 Units

Description Symbol Device Min Max Max Max

Delay from pad through Global Low Skew (GLS)

clock buffer to any clock input, K. TGLS XC40110XV 7.2 6.3 5.4 ns

XC40150XV 7.3 6.4 5.5 ns

XC40200XV 8.8 7.7 6.6 ns

XC40250XV 8.9 7.8 6.7 ns

Delay from pad through Global Early (GE) clock

buffer to any IOB clock input for BUFGE #s 1, 2,

5, and 6.

TGE_1256 XC40110XV 2.5 2.2 1.8 ns

XC40150XV 2.6 2.3 1.9 ns

XC40200XV 2.9 2.6 2.2 ns

XC40250XV 3.0 2.7 2.3 ns

Delay from pad through Global Early (GE) clock

buffer to any IOB clock input for BUFGE #s 3, 4,

7, and 8.

TGE_3478 XC40110XV 5.1 4.5 3.8 ns

XC40150XV 5.2 4.6 3.9 ns

XC40200XV 5.6 4.9 4.2 ns

XC40250XV 5.7 5.0 4.3 ns

Delay from pad through FastCLK buffer to any

IOB clock input TFCLK XC40110XV 5.1 4.5 3.8 ns

XC40150XV 5.2 4.6 3.9 ns

XC40200XV 5.6 4.9 4.2 ns

XC40250XV 5.7 5.0 4.3 ns

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Advance

XC4000XLA/XV Field Programmable Gate Arrays

6-190 May 14, 1999 (Version 1.2)

XC4000XV CLB Characteristics Guidelines

Testing of switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are

representative values. For more speciﬁc, more precise, and worst-case guaranteed data, use the values reported by the

static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing

parameters assume worst-case operating conditions (supply voltage and junction temperature). Values are expressed in

nanoseconds unless otherwise noted.

CLB Switching Characteristic Guidelines

Speed Grade -09 -08 -07 Units

Description Symbol Min Max Min Max Min Max

Combinatorial Delays

F/G inputs to X/Y outputs TILO 1.3 1.1 1.0 ns

F/G inputs via H’ to X/Y outputs TIHO 2.0 1.7 1.5 ns

F/G inputs via transparent latch to Q outputs TITO 2.1 1.8 1.6 ns

C inputs via SR/H0 via H to X/Y outputs THH0O 1.9 1.6 1.4 ns

C inputs via H1 via H to X/Y outputs THH1O 1.7 1.5 1.3 ns

C inputs via DIN/H2 via H to X/Y outputs THH2O 1.9 1.6 1.4 ns

C inputs via EC, DIN/H2 to YQ, XQ output (bypass0 TCBYP 1.2 1.0 0.9 ns

CLB Fast Carry Logic

Operand inputs (F1, F2, G1, G4) to COUT TOPCY 2.2 1.9 1.7 ns

Add/Subtract input (F3) to COUT TASCY 1.3 1.1 1.0 ns

Initialization inputs (F1, F3) to COUT TINCY 1.4 1.2 1.0 ns

CIN through function generators to X/Y outputs TSUM 1.8 1.6 1.4 ns

CIN to COUT, bypass function generators TBYP 0.3 0.2 0.2 ns

Carry Net Delay, COUT to CIN TNET 0.4 0.3 0.3 ns

Sequential Delays

Clock K to Flip-Flop outputs Q TCKO 1.6 1.4 1.2 ns

Clock K to Latch outputs Q TCKLO 1.6 1.4 1.2 ns

Setup Time before Clock K

F/G inputs TICK 0.8 0.7 0.6 ns

F/G inputs via H TIHCK 1.5 1.3 1.1 ns

C inputs via H0 through H THH0CK 1.4 1.2 1.0 ns

C inputs via H1 through H THH1CK 1.2 1.1 0.9 ns

C inputs via H2 through H THH2CK 1.4 1.2 1.0 ns

C inputs via DIN TDICK 0.6 0.6 0.5 ns

C inputs via EC TECCK 0.7 0.6 0.5 ns

C inputs via S/R, going Low (inactive) TRCK 0.6 0.5 0.4 ns

CIN input via F/G TCCK 1.3 1.1 1.0 ns

CIN input via F/G and H TCHC 2.0 1.7 1.5 ns

Hold Time after Clock K

All Hold Times 0.0 0.0 0.0 ns

Clocks

Clock High time TCH 2.3 2.0 1.7 ns

Clock Low time TCL 2.3 2.0 1.7 ns

Set/Reset Direct

Width (High) TRPW 3.0 2.8 2.5 ns

Delay from C inputs via S/R, going High to Q TRIO 2.6 2.3 2.0 ns

Global Set/Reset

Minimum GSR Pulse Width TMRW 13.4 11.7 10.2 ns

Delay from GSR input to any Q TMRQ See page 197 for TRRI values per device

Toggle Frequency (MHz) (for export control purposes) FTOG 224 258 296 MHz

Advance

May 14, 1999 (Version 1.2) 6-191

XC4000XLA/XV Field Programmable Gate Arrays

CLB RAM Single Port Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are

representative values. For more speciﬁc, more precise, and worst-case guaranteed data, use the values reported by the

static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing

parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all

XC4000XV devices and are expressed in nanoseconds unless otherwise noted.

Single Port RAM Speed Grade -09 -08 -07 Units

Size Symbol Min Max Min Max Min Max

Write Operation

Address write cycle time (clock K period) 16x2 TWCS 7.0 6.1 5.3 ns

32x1 TWCTS 7.0 6.1 5.3 ns

Clock K pulse width (active edge) 16x2 TWPS 3.5 3.1 2.7 ns

32x1 TWPTS 3.5 3.1 2.7 ns

Address setup time before clock K 16x2 TASS 1.5 1.3 1.2 ns

32x1 TASTS 1.6 1.4 1.2 ns

Address hold time after clock K 16x2 TAHS 0.0 0.0 0.0 ns

32x1 TAHTS 0.0 0.0 0.0 ns

DIN setup time before clock K 16x2 TDSS 1.6 1.4 1.2 ns

32x1 TDSTS 2.0 1.7 1.5 ns

DIN hold time after clock K 16x2 TDHS 0.0 0.0 0.0 ns

32x1 TDHTS 0.0 0.0 0.0 ns

WE setup time before clock K 16x2 TWSS 1.5 1.3 1.2 ns

32x1 TWSTS 1.4 1.3 1.1 ns

WE hold time after clock K 16x2 TWHS 0.0 0.0 0.0 ns

32x1 TWHTS 0.0 0.0 0.0 ns

Data valid after clock K 16x2 TWOS 5.2 4.6 4.0 ns

32x1 TWOTS 6.2 5.4 4.7 ns

Read Operation

Address read cycle time 16x2 TRC 4.5 3.1 3.1 ns

32x1 TRCT 6.5 5.5 5.5 ns

Data Valid after address change (no Write Enable) 16x2 TILO 1.3 1.1 1.0 ns

32x1 TIHO 2.0 1.7 1.5 ns

Address setup time before clock K 16x2 TICK 0.8 0.7 0.6 ns

32x1 TIHCK 1.5 1.3 1.1 ns

Advance

XC4000XLA/XV Field Programmable Gate Arrays

6-192 May 14, 1999 (Version 1.2)

CLB RAM Dual Port Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are

guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative

values for typical pin locations and normal clock loading. For more speciﬁc, more precise, and worst-case guaranteed data,

reﬂecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development

System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from

the static timing analyzer report.

CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms

Dual Port RAM Speed Grade -09 -08 -07 Units

Size Symbol Min Max Min Max Min Max

Address write cycle time (clock K period) 16x1 TWCDS 7.0 6.1 5.3 ns

Clock K pulse width (active edge) 16x1 TWPDS 3.5 3.1 2.7 ns

Address setup time before clock K 16x1 TASDS 1.5 1.3 1.2 ns

Address hold time after clock K 16x1 TAHDS 0.0 0.0 0.0 ns

DIN setup time before clock K 16x1 TDSDS 1.9 1.7 1.4 ns

DIN hold time after clock K 16x1 TDHDS 0.0 0.0 0.0 ns

WE setup time before clock K 16x1 TWSDS 1.5 1.3 1.2 ns

WE hold time after clock K 16x1 TWHDS 0.0 0.0 0.0 ns

Data valid after clock K 16x1 TWODS 6.0 5.3 4.6 ns

Note: Timing for 16x1 option is identical to 16x2 RAM. Advance

X6461

WCLK (K)

ADDRESS

DATA IN

DATA OUT OLD NEW

TDSS TDHS

TASS TAHS

TWSS

TWPS

TWHS

TWOS

TILO

WCLK (K)

ADDRESS

DATA IN

TDSDS TDHDS

TASDS TAHDS

TWSDS

TWPDS

TWHDS

X6474

DATA OUT OLD NEW

TWODS

TILO

Single Port RAM Dual Port RAM

May 14, 1999 (Version 1.2) 6-193

XC4000XLA/XV Field Programmable Gate Arrays

XC4000XV Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are

guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative

values for typical pin locations and normal clock loading. For more speciﬁc, more precise, and worst-case guaranteed data,

reﬂecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development

System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from

the static timing analyzer report.

Global Clock Input to Output Delay Guidelines

Low Skew FastCLK Input to Output Delay Guidelines for BUFNW, SW, NE, and SE

Speed Grade All -09 -08 -07 Units

Description Symbol Device Min Max Max Max

Global Low Skew (GLS) Clock Input to Output TICKOF XC40110XV 10.6 9.2 8.0 ns

Delay using Output Flip-Flop. XC40150XV 10.7 9.3 8.1 ns

XC40200XV 12.2 10.6 9.2 ns

XC40250XV 12.3 10.7 9.3 ns

For output SLOW option add TSLOW All Devices 1.7 1.6 1.4 ns

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Advance

Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible

column, and where all accessible IOB and CLB ﬂip-ﬂops are clocked by the global clock net.

Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is

measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all

accessible CLB ﬂip-ﬂops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined

by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin

clock-to-out delay for clocked outputs in FAST mode speciﬁcation.

Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.

Speed Grade All -09 -08 -07 Units

Description Symbol Device Min Max Max Max

FastCLK Input to Output Delay using Output TICKFOF XC40110XV 5.9 5.1 4.4 ns

Flip-Flop for FastCLK buffers BUFNW, BUFSW, XC40150XV 6.0 5.2 4.5 ns

BUFNE, and BUFSE. XC40200XV 6.3 5.5 4.8 ns

XC40250XV 6.4 5.6 4.9 ns

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Advance

Notes: Listed above are representative values where one FastCLK input drives one vertical clock line in each accessible column,

and where all accessible IOB and CLB ﬂip-ﬂops are clocked by the FastCLK net.

Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is

measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all

accessible CLB ﬂip-ﬂops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined

by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin

clock-to-out delay for clocked outputs in FAST slew mode speciﬁcation.

Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.

XC4000XLA/XV Field Programmable Gate Arrays

6-194 May 14, 1999 (Version 1.2)

Global Early Clock Input to Output Delay Guidelines for BUFGE #s 1, 2, 5, and 6

Global Early Clock Input to Output Delay Guidelines for BUFGE #s 3, 4, 7, and 8

Capacitive Load Factor

Figure 1 shows the relationship between I/O output delay

and load capacitance. It allows a user to adjust the speci-

ﬁed output delay if the load capacitance is different than

50 pF. For example, if the actual load capacitance is

120 pF, add 2.5 ns to the speciﬁed delay. If the load capac-

itance is 20 pF, subtract 0.8 ns from the speciﬁed output

delay.

Figure 1 is usable over the speciﬁed operating conditions of

voltage and temperature and is independent of the output

slew rate control.

Figure 1: Delay Factor at Various Capacitive Loads

Speed Grade All -09 -08 -07 Units

Description Symbol Device Min Max Max Max

Global Clock Signal Input to Output Delay using

Global Early (GE) clock buffer to clock Output

Flip-Flop for BUFGE #s 1, 2, 5, and 6.

TICKEOF_1256 XC40110XV 8.5 7.4 6.4 ns

XC40150XV 8.6 7.5 6.5 ns

XC40200XV 9.0 7.8 6.8 ns

XC40250XV 9.1 7.9 6.9 ns

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Advance

Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is

measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all

accessible CLB ﬂip-ﬂops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by

the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin

clock-to-out delay for clocked outputs in FAST mode speciﬁcation.

Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.

Speed Grade All -09 -08 -07 Units

Description Symbol Device Min Max Max Max

Global Clock Signal Input to Output Delay using

Global Early (GE) clock buffer to clock Output

Flip-Flop for BUFGE #s 3, 4, 7, and 8.

TICKEOF_3478 XC40110XV 8.5 7.4 6.4 ns

XC40150XV 8.6 7.5 6.5 ns

XC40200XV 9.0 7.8 6.8 ns

XC40250XV 9.1 7.9 6.9 ns

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Advance

Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is

measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all

accessible CLB ﬂip-ﬂops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by

the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin

clock-to-out delay for clocked outputs in FAST mode speciﬁcation.

Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.

X8257

-2 0 20406080

Capacitance (pF)

Delta Delay (ns)

100 120 140

-1

May 14, 1999 (Version 1.2) 6-195

XC4000XLA/XV Field Programmable Gate Arrays

XC4000XV Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are

guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative

values for typical pin locations and normal clock loading. For more speciﬁc, more precise, and worst-case guaranteed data,

reﬂecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development

System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from

the static timing analyzer report.

Global Low Skew Clock, Set-Up and Hold Guidelines

FastCLK Input Set-Up and Hold Guidelines for BUFNW, SW, NE, and SE

Speed Grade -09 -08 -07 Units

Description Symbol Device Min Min Min

Input Setup and Hold Time Relative to Global Clock Input Signal

No Delay XC40110XV 0.0 / 6.8 0.0 / 5.9 0.0 / 5.1 ns

Global Low Skew Clock and IFF TPSN/TPHN XC40150XV 0.0 / 7.5 0.0 / 6.6 0.0 / 5.7 ns

Global Low Skew Clock and FCL XC40200XV 0.0 / 8.8 0.0 / 6.7 0.0 / 6.7 ns

XC40250XV 0.0 / 9.8 0.0 / 8.5 0.0 / 7.4 ns

Partial Delay XC40110XV 5.5 / 0.5 4.8 / 0.5 4.1 / 0.4 ns

Global Low Skew Clock and IFF TPSP/TPHP XC40150XV 6.1 / 0.5 5.3 / 0.5 4.6 / 0.4 ns

Global Low Skew Clock and FCL XC40200XV 7.9 / 0.3 6.8 / 0.2 5.9 / 0.2 ns

XC40250XV 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 ns

Full Delay XC40110XV 8.0 / 0.0 6.9 / 0.0 6.0 / 0.0 ns

Global Low Skew Clock and IFF TPSD/TPHD XC40150XV 8.9 / 0.0 7.7 / 0.0 6.7 / 0.0 ns

XC40200XV 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0 ns

XC40250XV 9.7 / 0.0 8.4 / 0.0 7.3 / 0.0 ns

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Advance

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance.

Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is

measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two

IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions.

Speed Grade -09 -08 -07 Units

Description Symbol Device Min Min Min

No Delay XC40110XV 0.8 / 4.2 0.7 / 3.7 0.6 / 3.2 ns

FastCLK and IFF TPSFN/TPHFN XC40150XV 0.8 / 4.6 0.7 / 4.0 0.6 / 3.5 ns

XC40200XV 0.8 / 4.9 0.7 / 4.3 0.6 / 3.7 ns

XC40250XV 0.8 / 5.3 0.7 / 4.6 0.6 / 4.0 ns

Partial Delay XC40110XV 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0 ns

FastCLK and IFF TPSFP/TPHFP XC40150XV 11.1 / 0.0 9.7 / 0.0 8.4 / 0.0 ns

XC40200XV 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 ns

XC40250XV 11.6 / 0.0 10.1 / 0.0 8.8 / 0.0 ns

Full Delay XC40110XV 11.7 / 0.0 10.5 / 0.0 9.1 / 0.0 ns

FastCLK and IFF TPSFD/TPHFD XC40150XV 11.8 / 0.0 10.6 / 0.0 9.2 / 0.0 ns

XC40200XV 12.4 / 0.0 10.8 / 0.0 9.4 / 0.0 ns

XC40250XV 12.7 / 0.0 11.0 / 0.0 9.6 / 0.0 ns

IFF = Input Flip-Flop or Latch Advance

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance

Notes: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a

reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times

under given design conditions.

XC4000XLA/XV Field Programmable Gate Arrays

6-196 May 14, 1999 (Version 1.2)

BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-Up and Hold for IFF and FCL Guidelines

BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-Up and Hold for IFF and FCL Guidelines

Speed Grade -09 -08 -07 Units

Description Symbol Device Min Min Min

Input Setup and Hold Time Relative to Global Clock Input Signal

No Delay XC40110XV 0.5 / 6.1 0.4 / 5.3 0.4 / 4.6 ns

Global Early Clock and IFF TPSEN/TPHEN XC40150XV 0.6 / 6.2 0.5 / 5.4 0.4 / 4.7 ns

Global Early Clock and FCL TPFSEN/TPFHEN XC40200XV 1.3 / 7.3 1.2 / 6.3 1.0 / 5.5 ns

XC40250XV 1.5 / 7.5 1.3 / 6.6 1.1 / 5.7 ns

Partial Delay XC40110XV 7.3 / 0.0 6.3 / 0.0 5.5 / 0.0 ns

Global Early Clock and IFF TPSEP/TPHEP XC40150XV 8.1 / 0.0 7.0 / 0.0 6.1 / 0.0 ns

Global Early Clock and FCL TPFSEP/TPFHEP XC40200XV 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 ns

XC40250XV 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0 ns

FullDelay XC40110XV 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 ns

Global Early Clock and IFF TPSED/TPHED XC40150XV 10.7 / 0.0 9.3 / 0.0 8.1 / 0.0 ns

XC40200XV 11.9 / 0.0 10.4 / 0.0 9.0 / 0.0 ns

XC40250XV 13.1 / 0.0 11.4 / 0.0 9.9 / 0.0 ns

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Advance

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance.

Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is

measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two

IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions.

Speed Grade -09 -08 -07 Units

Description Symbol Device Min Min Min

Input Setup and Hold Time Relative to Global Clock Input Signal

No Delay XC40110XV 0.4 / 5.2 0.3 / 4.5 0.3 / 3.9 ns

Global Early Clock and IFF TPSEN/TPHEN XC40150XV 0.4 / 5.3 0.4 / 4.6 0.3 / 4.0 ns

Global Early Clock and FCL TPFSEN/TPFHEN XC40200XV 0.9 / 6.2 0.8 / 5.4 0.7 / 4.7 ns

XC40250XV 1.1 / 6.5 0.9 / 5.6 0.8 / 4.9 ns

Partial Delay XC40110XV 7.4 / 0.0 6.5 / 0.0 5.6 / 0.0 ns

Global Early Clock and IFF TPSEP/TPHEP XC40150XV 7.5 / 0.0 6.6 / 0.0 5.7 / 0.0 ns

Global Early Clock and FCL TPFSEP/TPFHEP XC40200XV 9.7 / 0.0 8.4 / 0.0 7.3 / 0.0 ns

XC40250XV 11.6 / 0.0 10.1 / 0.0 8.8 / 0.0 ns

FullDelay XC40110XV 10.0 / 0.0 8.6 / 0.0 7.5 / 0.0 ns

Global Early Clock and IFF TPSED/TPHED XC40150XV 10.1 / 0.0 8.7 / 0.0 7.6 / 0.0 ns

XC40200XV 10.7 / 0.0 9.3 / 0.0 8.1 / 0.0 ns

XC40250XV 12.8 / 0.0 11.2 / 0.0 9.7 / 0.0 ns

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Advance

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance.

Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is

measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two

IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions.

May 14, 1999 (Version 1.2) 6-197

XC4000XLA/XV Field Programmable Gate Arrays

IOB Input Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are

representative values. For more speciﬁc, more precise, and worst-case guaranteed data, use the values reported by the

static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path

delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume

worst-case operating conditions (supply voltage and junction temperature).

Speed Grade -09 -08 -07 Units

Description Symbol Device Min Max Min Max Min Max

Clocks

Clock Enable (EC) to Clock (IK) TECIK All Devices 0.0 0.0 0.0 ns

Delay from Fast Capture Latch enable (OK) active

edge to IFF clock (IK) active edge TOKIK All Devices 1.3 1.2 1.0 ns

Setup Times

Pad to Clock (IK), no delay TPICK All Devices 1.3 1.1 1.0 ns

Pad to Clock (IK), via transparent Fast Capture

Latch, no delay TPICKF Al Devices 1.8 1.6 1.4 ns

Pad to Fast Capture Latch Enable (OK), no delay TPOCK All Devices 1.1 1.0 0.8 ns

Hold Times

All Hold Times All Devices 0.0 0.0 0.0 ns

Global Set/Reset

Minimum GSR Pulse Width TMRW All Devices 13.4 11.7 10.2 ns

Delay from GSR input to any Q TRRI* XC40110XV 27.2 23.6 20.5 ns

XC40150XV 29.1 25.3 22.0 ns

XC40200XV 33.8 29.4 25.5 ns

XC40250XV 35.8 31.1 27.0 ns

Propagation Delays

Pad to I1, I2 TPID All devices 1.6 1.4 1.2 ns

Pad to I1, I2 via transparent input latch, no delay TPLI All devices 2.7 2.3 2.0 ns

Pad to I1, I2 via transparent FCL and input latch,

no delay TPFLI All Devices 3.6 3.1 2.7 ns

Clock (IK) to I1, I2 (flip-flop)

Clock (IK) to I1, I2 (latch enable, active Low)

FCL Enable (OK) active edge to I1, I2 (via trans-

parent standard input latch)

TIKRI

TIKLI

TOKLI

All Devices

1.4

1.6

2.7

1.2

1.4

2.4

1.1

1.2

2.1

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch. Advance

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance.

* Indicates Minimum Amount of Time to Assure Valid Data.

XC4000XLA/XV Field Programmable Gate Arrays

6-198 May 14, 1999 (Version 1.2)

IOB Output Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are

representative values. For more speciﬁc, more precise, and worst-case guaranteed data, use the values reported by the

static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path

delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume

worst-case operating conditions (supply voltage and junction temperature).

Revision Control

Speed Grade -09 -08 -07 Units

Description Symbol Device Min Max Min Max Min Max

Clocks

Clock High TCH All Devices 2.3 2.0 1.7 ns

Clock Low TCL All Devices 2.3 2.0 1.7 ns

Propagation Delays (See Note 1)

Clock (OK) to Pad TOKPOF All Devices 3.5 3.0 2.7 ns

Output (O) to Pad TOPF All Devices 3.0 2.6 2.3 ns

3-state to Pad hi-Z (slew-rate independent) TTSHZ All Devices 3.0 2.6 2.2 ns

3-state to Pad active and valid TTSONF All Devices 3.1 2.7 2.3 ns

Clock to Pad hi-Z TOKSHZ All Devices 4.7 4.1 3.5 ns

Clock to Pad active and valid TOKSONF All Devices 4.8 4.2 3.6 ns

Output (O) to Pad via Fast Output MUX TOFPF All Devices 4.4 3.8 3.3 ns

Select (OK) to Pad via Fast MUX TOKFPF All Devices 4.0 3.5 3.0 ns

Setup and Hold Times

Output (O) to clock (OK) setup time TOOK All Devices 0.4 0.4 0.3 ns

Output (O) to clock (OK) hold time TOKO All Devices 0.0 0.0 0.0 ns

Clock Enable (EC) to clock (OK) setup time TECOK All Devices 0.0 0.0 0.0 ns

Clock Enable (EC) to clock (OK) hold time TOKEC All Devices 0.3 0.2 0.1 ns

Global Set/Reset

Minimum GSR pulse width TMRW All Devices 13.4 11.7 10.2 ns

Delay from GSR input to any Pad TRPO* XC40110XV 30.5 26.6 23.1 ns

XC40150XV 32.5 28.3 24.6 ns

XC40200XV 37.1 32.3 28.1 ns

XC40250XV 39.1 34.0 29.6 ns

Slew Rate Adjustment

For output SLOW option add TSLOW All Devices 2.3 2.0 1.7 ns

* Indicates Minimum Amount of Time to Assure Valid Data. Advance

Bold Face: Preliminary Values for the XC40150-09. All other values are Advance.

Note: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.

Version Description

2/1/99 (1.0) Release included in 1999 data book, section 6

2/19/99 (1.1) Updated Switching Characteristics Tables

5/14/99 (1.2) Replaced Electrical Specification pages for XLA and XV families with separate updates and added

URL link on placeholder page for electrical specifications/pinouts for WebLINX users.