JUNE 2012
DSC-3101/09
1
©2012 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆Ideal for high-performance processor secondary cache
◆◆
◆◆
◆Commercial (0°C to +70°C) and Industrial (–40°C to +85°C)
temperature range options
◆◆
◆◆
◆Fast access times:
– Commercial and Industrial: 10/12/15/20ns
◆◆
◆◆
◆Low standby current (maximum):
– 2mA full standby
◆◆
◆◆
◆Small packages for space-efficient layouts:
– 28-pin 300 mil SOJ
– 28-pin TSOP Type I
◆◆
◆◆
◆Produced with advanced high-performance CMOS
technology
◆◆
◆◆
◆Inputs and outputs are LVTTL-compatible
◆◆
◆◆
◆Single 3.3V(±0.3V) power supply
Description
The IDT71V256SA is a 262,144-bit high-speed static RAM organized
as 32K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology.
The IDT71V256SA has outstanding low power characteristics while
at the same time maintaining very high performance. Address access
times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V
desktop designs.
When power management logic puts the IDT71V256SA in standby
mode, its very low power characteristics contribute to extended battery life.
By taking CS HIGH, the SRAM will automatically go to a low power standby
mode and will remain in standby as long as CS remains HIGH. Further-
more, under full standby mode (CS at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically will be much
smaller.
The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin
300 mil TSOP Type I.
Functional Block Diagram
A
0
ADDRESS
DECODER
262,144 BIT
MEMORY ARRAY
I/O CONTROL
3101 drw 01
INPUT
DATA
CIRCUIT
WE
CS
V
CC
GND
A
14
I/O
0
I/O
7
CONTROL
CIRCUIT
OE
,
Lower Power
3.3V CMOS Fast SRAM
256K (32K x 8-Bit)
IDT71V256SA
2
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Pin Configurations
Absolute Maximum Ratings(1)
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Truth Table(1)
DIP/SOJ
Top View
Pin Descriptions
TSOP
Top View
3101 drw 02
5
6
7
8
9
10
11
12
A
12
1
2
3
4
24
23
22
21
20
19
18
17
SO28-5
13
14
28
27
26
25
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
V
CC
WE
A
8
A
9
A
11
OE
A
10
CS
I/O
7
16
15
I/O
2
GND
I/O
6
I/O
5
I/O
4
I/O
3
A
14
A
13
,
3101 drw 03
22
23
24
25
26
27
28
1
2
3
4
5
7
6
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
SO28-8
OE
A
11
A
9
A
8
A
13
A
14
A
7
A
6
A
5
A
4
A
3
A
12
WE
V
CC
,
Name Description
A
0
- A
14
Addresses
I/O
0
- I/O
7
Data Inp ut/ Outp ut
CS Chip Select
WE Write Enable
OE Outp ut Enab le
GND Ground
V
CC
Power
3101 tbl 01
NOTE:
1 . H = VIH, L = VIL, X = Don’t Care
WE CS OE I/O Function
X H X Hig h-Z Stand by (I
SB
)
XV
HC
X Hig h-Z Stand by (I
SB1
)
H L H Hig h-Z Output Disab le
HLLD
OUT
Read
LLXD
IN
Write
3101 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. Input, Output, and I/O terminals; 4.6V maximum.
Symbol Rating Com'l. Unit
V
CC
Supply Voltage
Re lativ e to GND -0.5 to +4.6 V
V
TERM
(2)
Terminal Voltage
Re lativ e to GND -0.5 to V
CC
+0.5 V
T
BIAS
Te mp erature Und er Bias -55 to +125
o
C
T
STG
Storage Te mp erature -55 to +125
o
C
P
T
Po we r Di ss ip atio n 1. 0 W
I
OUT
DC Output Curre nt 50 mA
3101 tbl 03
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV 6 pF
C
OUT
Outpu t Capac i tanc e V
OUT
= 3dV 7 pF
3101 tbl 04
Grade Temperature GND Vcc
Commercial 0OC to +70OC 0V 3.3V ± 0. 3V
Industrial -40OC to +85OC 0V 3.3V ± 0. 3V
3101 tbl 05
6.42
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
3
Recommended DC Operating
Conditions
NOTE:
1. VIL (min.) = –2.0V for pulse width less than 5ns, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
____
V
CC
+0.3 V
V
IH
Input High Voltage - I/O 2.0
____
V
CC
+0.3 V
V
IL
Inp ut L o w Vo l tag e -0 .3
(1)
____
0.8 V
3101 tbl 06
DC Electrical Characteristics
(VCC = 3.3V± 0.3V)
DC Electrical Characteristics(1)
(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V, Commercial and Industrial Temperature
Ranges)
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs cycling at fMAX; f = 0 means that no inputs are cycling.
Symbol Parameter 71V256SA10 71V256SA12 71V256SA15 71V256SA20 Unit
I
CC
Dynamic Operating Current CS < V
IL
, Outputs
Ope n, V
CC
= Max., f = f
MAX
(2)
100 90 85 85 mA
I
SB
Standb y Power Supp ly Current (TTL Level)
CS = V
IH
, V
CC
= Max., Outputs Open, f = f
MAX
(2)
20 20 20 20 mA
I
SB1
Full Standby Power Supply Current (CMOS Level)
CS > V
HC
, V
CC
= Max., Outputs Open, f = 0
(2)
,
V
IN
< V
LC
or V
IN
> V
HC
2222mA
3101 tbl 07
Symbol Parameter Test Conditions
IDT71V256SA
UnitMin. Typ. Max.
|I
LI
| Input Le akage Current V
CC
= Max., V
IN
=
GND to V
CC
___ ___
2µA
|I
LO
| Outp ut Le ak ag e Curre nt V
CC
= Max., CS = V
IH
, V
OUT
= GND to V
CC
___ ___
2µA
V
OL
Outp ut Low Vo ltage I
OL
= 8mA, V
CC
= Min.
___ ___
0.4 V
V
OH
Outp ut High Vo ltag e I
OH
= -4mA, V
CC
= Mi n. 2.4
___ ___
V
3101 tbl 08
4
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
Figure 1. AC Test Load Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
*Includes scope and jig capacitances
AC Test Conditions
3101 drw 04
320Ω
30pF*
350Ω
DATA
OUT
3.3V
,
3101 drw 05
320Ω
5pF*
350Ω
DATA
OUT
3.3V
,
Input Pulse Levels
Inp ut Ris e /Fal l Time s
Input Timing Referenc e Leve ls
Outp ut Re fere nce Lev e ls
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
3101 tbl 09
NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
Symbol Parameter
71V256SA10 71V256SA12 71V256SA15 71V256SA20
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycl e
t
RC
Re ad Cyc le Time 10
____
12
____
15
____
20
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
____
20 ns
t
ACS
Chip Selec t Acc ess Time
____
10
____
12
____
15
____
20 ns
t
CLZ
(1)
Chip S e lect to Outp ut in Low-Z 5
____
5
____
5
____
5
____
ns
t
CHZ
(1)
Chip Select to Output in High-Z 080809010ns
t
OE
Output Enab le to Outp ut Valid
____
6
____
6
____
7
____
8ns
t
OLZ
(1)
Outp ut E nab l e to Ou tp ut i n Lo w-Z 3
____
3
____
0
____
0
____
ns
t
OHZ
(1)
Output Disable to Output in High-Z 26260708ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
3
____
ns
Writ e Cy c le
t
WC
Write Cycle Time 10
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 9
____
9
____
10
____
15
____
ns
t
CW
Chip Sele ct to End -of-Write 9
____
9
____
10
____
15
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 9
____
9
____
10
____
15
____
ns
t
WR
Write Recove ry Time 0
____
0
____
0
____
0
____
ns
t
DW
Da ta to Wr ite Ti me O ve rl ap 6
____
6
____
7
____
8
____
ns
t
DH
D ata Ho ld fro m Wri te Time 0
____
0
____
0
____
0
____
ns
t
OW
(1)
Outp ut A cti ve from E nd -o f-Wri te 4
____
4
____
4
____
4
____
ns
t
WHZ
(1)
Write E nable to Output in Hig h-Z 1 8 1 8 1 9 1 10 ns
3 101 tbl 10
6.42
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cyc le No. 1(1)
NOTES:
1. WE is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.
ADDRESS
CS
DATA
OUT
OE
3101 drw 06
t
RC
t
AA
t
OH
t
ACS
t
CLZ
t
CHZ (2)
t
OE
t
OLZ
(2)
(2)
t
OHZ (2)
DATA VALID
,
Timing Waveform of R ead Cyc le No. 2(1,2,4)
Timing Waveform of R ead Cyc le No. 3(1,3,4)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
DATA
OUT
CS
3101 drw 08
t
ACS
(5)
t
CLZ
(5)
CHZ
t
DATA VALID
,
ADDRESS
DATA
OUT
3101 drw 07
t
RC
t
AA
t
OH
t
OH
DATA VALIDPREVIOUS DATA VALID
,
6
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
Timing Wa v ef orm of Write Cyc le No . 2 (CS Controlled Timing)(1,2,3,4)
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified tWP.
CS
DATA
IN
ADDRESS
WE
t
WR
3101 drw 10
t
AW
t
DW
t
WC
t
CW
t
DH
AS
t t
(5)
DATA VALID
,
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3 . During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified tWP.
Timing Wa vef orm of Write Cyc le No. 1 (WE Controlled Timing)(1,2,4,6)
CS
DATA
IN
ADDRESS
WE
DATA
OUT
OE
3101 drw 09
t
AW
t
WR
t
DW
t
WC
t
WP
t
DH
t
WHZ
t
OW
(3)
(6)
t
AS
(5)
(3)
t
OHZ (5)
DATA VALID
(5)
,
6.42
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
7
Ordering Information — Commercial and Industrial
300 mil SOJ (SO28-5)
TSOP Type I (SO28-8)
SA
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Y
PZ
10
12
15
20*
Speed in nanoseconds
3101 drw 11
71V256
Device
Type
* Available in TSOP package only.
X
Tape & Reel
8
X
GGreen
8
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/7/00 Updated to new format
Pg. 1, 3, 4, 7 Expanded Industrial Temperature offerings
Pg. 1, 2, 7 Removed 28-pin 300 mil plastic DIP package offering
Pg. 6 Removed Note No. 1 from Write Cycle No. 1 diagram; renumbered notes and footnotes
Pg. 7 Revised Ordering Information
Pg. 8 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
06/21/02 Pg. 7 Added tape and reel option to the ordering information
01/30/04 Pg. 7 Added "restricted hazardous substance device" to order information.
02/20/09 Pg. 7 Removed "IDT" from ordering parts
06/11/12 Pg. 3 Corrected Recommended DC Operation Conditions Max VIH from 5.0 to Vcc+0.3V
Pg. 7 Added Green designator to ordering information
Pg. 7 Corrected footnote in the ordering information from "available in SOJ package only" to
"available in TSOP package only"
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
