fax id: 5404 CY7C419/21/25/29/33 CYPRESS 256/512 /1K /2K/4K x 9 Asynchronous FIFO Features Asynchronous first-in first-out (FIFO) buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421) * 1K x 9 (CY7C425) * 2K x 9 (CY7C429) * AK x 9 (CY7C433) * Dual-ported RAM cell * High-speed 50.0-MHz read/write independent of depth/width Low operating power: Icg = 35 mA Empty and Full flags (Half Full flag in standalone) TTL compatible Retransmit in standalone * Expandable in width * PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP Pin compatible and functionally equivalent to 1DT7200, 1DT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204 Functional Description The CY7C419, CY7C420/1, CY7C424/5, CY7C-428/9, and CY7C432/3 are first-in first-out (FIFO) memories offered in 600-mil wide and 300-mil wide packages. They are, respec- tively, 256, 512. 1,024, 2,048, and 4,096 words by 9-bits wide. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are aiso provided to facilitate unlimited expan- sion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in paral- lel, thus eliminating the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50.0 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high-impedance state when R is HIGH. A Half Full (HF) output flag is provided that is valid in the stan- daione and width expansion configurations. In the depth ex- pansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated. in the standalone and width expansion configurations, a LOW onthe retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit. and then Ris used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. in- put ESD protection is greater than 2000V and latch-up is pre- vented by careful layout and guard rings. For the most recent information, visit the Cypress web site at www.cypress.com 2-266CYPRESS CY7C419/21/25/29/33 Logic Block Diagram DATAINPUTS {D9--D g} TTT WRITE POINTER READ POINTER THRE mn. ai eurFERS r ee OUTPUTS (&-O_) RESET i READ LOGIC PL contrat FLAG + LOGIC [> EF tama EE EXPANSION x. LOGIC ROME Pin Configurations PLCC/LCC Top \ View Pore 2 Sara wR FURT Cc420-1 Selection Guide x 512 x 512 x x9 x x9 Maximum Rating (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature oe eee -65C to +150C Ambient Temperature with Power Applied oo... cece cet cererrentecrettes 55C to +125C Supply Voltage to Ground Potential ............. -0.5V to +7.0V DC Voltage Applied to Outputs in High 2 State 00 etter tree 0.5V to +7.0V DC Input Voltage Power Dissipation Output Current, into Outputs (LOW)... ee 20 mA Static Discharge Voltage oo... cece enenneee eens >2000V (per MIL-STD-883, Method 3015} Latch-Up Current... err tar erie >200 mA 2-267CY7C419/21/25/29/33 Operating Range Range Ambient Temperature! Voc Commercial OC to + 70C 5V 410% Industrial ~40C to +85C 5V + 10% Military -55C ta +125C SV + 10% Electrical Characteristics Over the Operating Rangel! 70419-10, 15, 30, 40 7C420/1~10, 15, 20, 25, 30, 40, 65 7C424/510, 15, 20, 25, 30, 40, 65 7C428/9--10, 15, 20, 25, 30, 40, 65 7432/3-10, 15, 20, 25, 30, 40, 65 Parameter Description Test Conditions Min. Max. Unit Vow Output HIGH Voltage Veco = Min.. toy = -2.0 mA 2.4 Vv Vor Output LOW Valtage Vec = Min. lop = 8.0 mA 0.4 Vv Vin Input HIGH Voltage Com'l 2.0 Voc Vv Mil/ind 2.2 Vec Vit Input LOW Voltage Note 3 0.8 Vv ly Input Leakage Current GND <V;< Veco ~-10 +10 uA loz Output Leakage Current Re Vi, GND <Vo < Voc L -10 +10 uA log Output Short Circuit Current! | Vgg = Max., Voyt = GND L ~90 mA Electrical Characteristics Over the Operating Rangel! (continued) | 70419-10 | 70419-15 | i 7C420-20 | 70420-25 | 70421~-10 | 70421-15 | 7C421-20 | 7C421-25 \ 7C424-20 | 7C0424-25 70425~-10 | 70425-15 | 7C425-20 | 7C425~25 70428-2060 70429-10 | 7C429-15 | 7C429-20 | 7C429~25 7C0432-25 70433-10 | 7C433-15 | 7C433-20 | 7C433-25 Parameter Description Test Conditions Min. i Max. | Min. | Max. | Min. | Max. | Min. | Max, | Unit lec Operating Current =| Vog = Max., | Com 85 65 55 50 | mA lour=OMA Fyivind 760 90 80 f= fax lees Operating Current Vec = Max., | Cam! 35 35 35 35 | mA lout =OmA F = 20 MHz ' Ise4 Standby Current All Inputs = Com'l | 10 10 10 10 | mA | Yin Min. Milind 15 15 15 lope Power-Down Current | All Inputs > Com i 5 5 5 mA Voo~02V [Milind 7] 8 5 8 Notes: : % is the instant on case temperature. 1 2 ee the last page of this specification for Group A subgroup testing information. 3. Vy, (Min.) = -2.0V for pulse durations of less than 20 ns. 4 For test purposes, not more than one output at a time should be shorted. Short circuit test duration shouid not exceed 30 seconds. 2-268CY7C419/21/25/29/33 Electrical Characteristics Over the Operating Rangel! (continued) 70419-30 70419-40 7C420-40 70420-65 70421~30 70421-40 7C421-65 70424-30 7C042440 7C424-65 70425-30 7C0425-40 7C0425-65 70428-65 7C429-30 7C429-40 7C0429-65 7C432-40 70433-30 7043340 70433-65 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Units loc Operating Current Veco = Max., Com! 40 35 35 mA lour = 0 mA Milind 75 70 65 t= fMax loc1 Operating Current Voc = Max., Com 35 35 35 mA lour = 0 mA F = 20 MHz Ise1 Standby Current Ail inputs = Com 10 10 10 mA c Vin Min. Mil 15 15 15 Ispe Power-Down Current | All Inputs > Com'l 5 5 5 mA Voc ~0.2V Mil 8 B a Capacitance! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f= 1 MHz, 6 pF Cour Output Capacitance Voo = 4.5V 6 pF Note: 5. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms At Q 5y 500 ome TT y R2 Ri 5009 V oy rn s R2 30 pF > . 5 pF > I F 3330 I 333.0 INCLUDING=t- te INCLUDING te JIGAND = 0420-6 JIGAND 420-7 SCOPE (a) SCOPE (b) THEVENIN EQUIVALENT 2002 OUTPUT o___-ww-_0 27 Equivalent to: 2-269 ALL INPUT PULSES 3.0V GND C420-8CYPRESS CY7C419/21/25/29/33 Switching Characteristics Over the Operating Range! 7] 70419-10 | 70419-15 7C420-20 7C420~-25 70421-10 7C421-15 70421-20 7421-25 7C424-20 | 70424~-25 70425-10 | 70425-15 | 7C425-20 | 70425-25 7C428-20 70429-10 7C0429-15 7429-20 7C429-25 70432~25 70433-1090 | 70433-15 | 7C433-20 | 7C433-25 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tao Read Cycle Time 20 25 30 35 ns ta Access Time 10 15 20 25 ns tar Read Recovery Time 10 10 10 10 ns tpr Read Pulse Width 10 15 20 25 ns ta? Read LOW to Low Z 3 3 3 3 ns tpvae"l Data Valid After Read HIGH 5 5 5 5 ns tuzAe es Read HIGH to High Z 15 15 15 18 ns twe Write Cycie Time 20 25 30 36 ns tpw Write Pulse Width 10 15 20 25 ns tuwz >") | Write HIGH to Low Z 5 5 5 5 ns twa Write Recovery Time 10 10 10 10 ns tsp Data Set-Up Time 6 8 12 15 ns typ Data Hold Time 0 0 0 0 ns twrsc MR Cycle Time 20 25 30 35 ns tpMA MR Pulse Width 10 15 20 25 ns tame MR Recovery Time 10 10 10 10 ions tapw Read HIGH to MR HIGH 10 15 20 25 ns twew Write HIGH to MA HIGH 10 15 20 25 ns tatc Retransmit Cycle Time 20 25 30 35 ns tpar Retransmit Pulse Width 10 15 20 25 ns | tata Retransmit Recovery Time 10 10 10 10 ns | Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified ig, lay and 30 pF load capacitance, as in part (a) of AC Test Load and Waveforms. unless otherwise specified. 7. See ihe last page of this specification for Group A subgroup testing information. 8. typ transition is measured at +200 mV from Ve, and200 mV from Voy. toy, transition is measured at the 1.5V level. tyyz and t, zp transition is measures at +100 mV from the steady state. 9. tigR and tov, use capacitance loading as in part (b! of AC Test Load and Waveforms. 2-270CY7C419/21/25/29/33 Switching Characteristics Over the Operating Range 7! (continued) 70419-10 7C419-15 7420-20 | 7C420-25 7C421-10 | 7C421~15 | 70421-20 | 7C421-25 70424-20 | 7C424-25 70425-10 | 7425-15 | 7C425-20 | 7C425-25 70428-20 7429-10 | 70429-15 | 7C429-20 | 7C429-25 70432-25 7C433-10 | 7C433-15 | 7C433-20 | 7C433-25 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit ter. MR to EF LOW 20 26 30 35 ns tueH MR to AF HIGH 20 25 30 35 ns trEH MR to FF HIGH 20 25 30 + 35 ns ther Read LOW to EF LOW 10 15 20 25 ns tare Read HIGH to FF HIGH 10 15 20 25 ns twee Write HIGH to EF HIGH 10 15 20 25 ns twee Write LOW to FF LOW 10 15 20 25 ns twee Write LOW to HF LOW 10 15 20 25 ns true Read HIGH to HF HIGH 10 15 20 25 ns trac Effective Read from Write HIGH 10 15 20 25 ns tape Effective Read Pulse Width After EF HIGH | 10 15 20 25 ns twaF Effective Write from Read HIGH 10 15 20 25 ns twee Effective Write Pulse Width After FF HIGH 10 15 20 25 ns tyot Expansion Out LOW Delay from Clock 10 15 20 25 ns | txow Expansion Out HIGH Delay from Clock 10 15 20 25 | ns 2-271CY7C419/21/25/29/33 CYPRESS Switching Characteristics Over the Operating Range 7] (continued) 7419-30 7C419-40 7C420-40 70420-65 70421-30 70421-40 70421-~65 70424-30 7C424-40 70424-65 7425-30 70425-40 7C0425-65 70428-65 70429-30 7C429-40 7C429-65 70432~40 7433-30 7043340 70433-65 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Unit tac Read Cycie Time 40 50 80 ns ta Access Time 30 40 65 ns trr Read Recovery Time 10 10 15 ns tpr Read Pulse Width 30 40 65 ns tne Read LOW to Low Z 3 3 3 ns tovae Data Valid After Read HIGH 5 5 5 ns tan? 8] Read HIGH to High Z 20 20 20 ns two Write Cycte Time 40 50 80 ns tpw Write Puise Width 30 40 65 ns tw?" Write HIGH to Low Z 5 5 5 ns twr Write Recovery Time 10 10 15 ns tsp Data Set-Up Time 18 20 30 ns typ Data Hold Time 0 0 0 ns tursc MR Cycle Time 40 50 80 ns teva MR Pulse Width 30 40 65 ns trMr MR Recovery Time 10 10 15 ns taew Read HIGH to MF HIGH 30 40 65 ns twew Write HIGH to MR HIGH 30 40 65 ns tate Retransmit Cycte Time 40 50 80 ns tpar Retransmit Pulse Width 30 40 65 ns tatrR Retransmit Recovery Time 10 10 15 ns ter. MR to EF LOW 40 50 80 ns tueH MR to AF HIGH 40 50 80 ns terH MR to FF HIGH 40 50 80 ns ther Read LOW to EF Low 30 35 60 ns tare Read HIGH to FF HIGH 30 35 60 ns wer Write HIGH to EF HIGH 30 35 60 ns twerr Write LOW to FF Low 30 35 60 ns tWHF Write LOW to RF LOW 30 35 60 ns tay Read HIGH to HF HIGH 30 35 60 ns trac Effective Read from Write HIGH 30 35 60 ns tape Effective Read Pulse Width After EF HIGH 30 40 65 ns twar Effective Write from Read HIGH 30 35 60 ns twer Effective Write Pulse Width After FF HIGH 30 40 65 ns tyou Expansion Out LOW Delay from Clock 30 40 65 ns txon Expansion Out HIGH Delay from Clock 30 40 65 ns 2-272ee CY7C419/21/25/29/33 Switching Waveforms Asynchronous Read and Write je__~ tae ______ tp; ___ >} pe ta Rk y tyzR t Qo-Q g (oAra Vall XXX) two w ~ taw oe twa - ____ Kf tsp > typ Do-D g DATA VALID DATA VALID a C420-9 Master Reset 4 tursc: tema WR . F, wit ter EF tHEH HF tere y FEOLLLLILLILLILELLLL LL ca20-10 Half-Full Flag HALF FULL HALF FULL+1 | HALF FULL we taHF R ee L WHF AF Vana C420-11 Notes: 10. Wand R 2 Vj, around the rising edge of MR. 14. tvase = tema + tama: 2-273CYPRESS Switching Waveforms (continued) Last Write to First Read Full Flag LAST WRITE FIRST READ ADDITIONAL READS CY7C419/21/25/29/33 FIRST WRITE R r Ly LS "Th / S/T WEF >} (REF pe 7 j 420-12 Last Read to First Write Empty Flag ADDITIONAL LAST READ FIRST WAITE WRITES FIRST READ . \__F S| TT / \__/ tREE llwer i EF RK_| ss 7 fa DATA OUT P{X KVALIOX X XXVALIOXX) 420-13 Retransmit!2! FURT y RW tard" tear Rf < tata C420-14 Notes: 12. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers. but flags will be valid at taro. 13. taro = tert + tatR 2-274Sars: Switching Waveforms (continued) Empty Flag and Read Data Flow-Through Mode CY7C419/21/25/29/33 DATA IN x " ~ f \# te trac F NAA EF twer DATA OUT XXXKK Full Flag and Write Data Flow-Through Mode A y C420-15 RK W ARAMA AY FF a tip DATA IN DATA VALID he ta f* tsp >| DATA OUT XK cara vaio XX C420-16 2-275ae CY7C419/21/25/29/33 Switching Waveforms (continued) Expansion Timing Diagrams WRITE TO LAST PHYSICAL WRITE TO FIRST PHYSICAL LOCATION OF DEVICE 1 LOCATION OF DEVICE 2 " y kt twr t t X0,1%)! 44] XOL XOH tio | KXXXKXKXKXM READ FROM LAST PHYSICAL LOCATION OF DEVICE 1 E t {14} XOL. RO (Xk) tso DATA VALIO ee- top >y 420-17 READ FROM FIRST PHYSICAL LOCATION OF DEVICE 2 txou XY ap ty CED 420-18 Note: 14, Architecture The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048, 4096 words of 9 bits each (implemented by an array of du- al-port RAM cells), a read pointer, a write pointer, control sig- nals (W, R, XT, XO, FL, RT, MR), and Full, Half Full, and Empty flags. Dual-Port RAM The dual-port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is neces- sary to achieve truly asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment Expansion Out of device 1 (%0,) is connected to Expansion In of device 2 (XT). the read and write pointers is much less than the time that would be required for data propagation through the memory, which would be the case if the memory were implemented using the conventional register array architecture. Resetting the FIFO Upon power-up, the FIFO must be reset with a Master Reset (MF) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF) and Full fiags (FF) being HIGH. Read (R) and write (W) must be HIGH tapyw/twew before and tary, after the rising edge of MF for a valid reset cycle. if reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state. 2-276CYPRESS CY7C419/21/25/29/33 Writing Data to the FIFO The availability of at least one empty location |s indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (Dp~Dg) tgp betore and typ after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs twer after the first LOW-to-HIGH transition of W for an empty FIFO. RF goes LOW typi after the falling edge of W following the FIFO actu- ally being Half Full. Therefore, the AF is active once the FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tay, after the rising edge of R when the FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. FF goes LOW twer after the falling edge of W, during the cycle in which the last available location is filled. internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tRFF after a read from a full FIFO. Reading Data from the FIFO The falling edge ot RF initiates a read cycle if the EF is not LOW. Data outputs (Qo~Qg) are in a high-impedance condition be- tween read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. The rising edge of R causes the data outputs te go to the high-impedance state and remain such until a write is performed. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read twee after a valid write. The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on FT resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and tara after retransmit is LOW. With every read cycle after retransmit, pre- viously accessed data as well as not previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted aiso. Up to the full depth of the FIFO can be repeatedly retransmit- ted. Standalone/Width Expansion Modes Standaione and width expansion modes are set by grounding Expansion In (X19) and tying First Load (FL) to Voc. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. Depth Expansion Mode (see Figure 1) Depth expansion mode is entered when, during a MR cycle, Expansion Out (XO) of one device is connected to Expansion In (XT) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and pulsed LOW again when the last physical location is read. Only one FIFO is enabled for read and one for write at any given time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created of word widths in increments of 9. When expanding in depth, a composite FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EF s togeth- er. RF and RT functions are not available in depth expansion mode. Use of the Empty and Full Flags In order to achieve the maximum frequency, the flags must be valid at the beginning of the next cycle. However, because they can be updated by either edge of the read of write signal, they must be valid by one-half of a cycle. Cypress FIFOs meet this requirement; some competitors FIFOs do not. The reason why the flags are required to be valid by the next cycle is fairly complex. It has to do with the effective pulse width violation phenomenon, which can occur at the full and empty boundary conditions, if the flags are not properly used. The empty flag must be used to prevent reading from an empty FIFO and the full flag must be used to prevent writing into a full FIFO. For example, consider an empty FIFO that is receiving read pulses. Because the FIFO is empty, the read pulses are ig- nored by the FIFO, and nothing happens. Next, a single word is written into the FIFO, with a signal that is asynchronous to the read signal. The (internal) state machine in the FIFO goes from empty to empty+1. However, it does this asynchronously with respect to the read signal, so that it cannot be determined what the effective pulse width of the read signal is, because the state machine does not ook at the read signal until it goes to the empty+1 state. In a similar manner, the minimum write pulse width may be violated by attempting to write into a full FIFO, and asynchronously performing a read. The empty and full flags are used to avoid these effective pulse width viola- tions, but in order to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next cycle. 2-277CY7C419/21/25/29/33 CYPRESS CY7C419 CY7C420/1 CY7C424/5, CY7C428/9 CY7C432/3 Fe Veo CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 FL * FIRST DEVICE 0420-19 Figure 1. Depth Expansion 2-278CYPRESS CY7C419/21/25/29/33 Ordering Information ) Ordering Code Package Type 10 19-1 1 4 2 Ordering Information (continued) Ordering Cade Package Type Ordering Information (continued) ns) Ordering Code Package Type 4 a = =| 2-279CY7C419/21/25/29/33 CYPRESS Ordering Information (continued) ns) Ordering Code Package Type Ordering Information (continued) Speed Package Operating (ns) Ordering Code Type Package Type Range 40 CY7C42440PC Pi5 28-Lead (600-Mil) Moided DIP Commercial 65 CY7C42465PC P15 28-Lead (600-Mil) Maided DIP Commercial Ordering information (continued) ) Ordering Code Package Type 10 2-280CY7C419/21/25/29/33 8 CYPRESS Ordering Information (continued) ) Ordering Code Package Type Ordering Information (continued) ns) Ordering Code Package Type Ordering Information (continued) ) Ordering Code Package Type 2-281CY7C419/21/25/29/33 CYPRESS Ordering Information (continued) Speed Package Operating ns) Ordering Code Name Package Type Range 25 CY7C432~25PC P15 28-Lead (600-Mil) Molded DIP Commercial 40 CY7C432-40PC P15 28-Lead (600-Mil) Moided DIP Commercial Ordering Information (continued) ) Ordering Code Package Type 2-282CY7C419/21/25/29/33 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameters Subgroups tac 9,10, 11 ta 9, 10, 11 tar 9,10, 11 tpR 910,17 tpva 9, 10, 11 two 9, 10, 11 tpw 9,10. 11 lwa 9, 10, 17 tsp 9, 10, 11 tHD 9,10, 11 twRsc 9, 16, 17 tema 9,10, 11 tamr 9,10, 11 tapw 9, 10, 11 twew 9, 10, 11 tate 9.10, 11 tear 9, 10, 11 tare 9, 10, 71 terL 9, 10, 17 tHe 9, 10, 11 TEE 9,10, 11 tree 9. 10, 11 taFF 9,10, 14 | twer 9, 10, 11 : | twee 9,10, 11 | tye 9, 10, 17 taHF 9,10, 11 tRAE 9,10, 11 tape 9, 10, 17 tWaF 9, 10, 11 | twee 9,10, 11 : txoL 9,10, 71 tyou 9, 10, i] | Document #: 38-00079-M 2-283