LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 LM3224 615kHz/1.25MHz Step-up PWM DC/DC Converter Check for Samples: LM3224 FEATURES DESCRIPTION * * The LM3224 is a step-up DC/DC converter with a 0.15 (typ.), 2.45A (typ.) internal switch and pin selectable operating frequency. With the ability to convert 3.3V to multiple outputs of 8V, -8V, and 23V, the LM3224 is an ideal part for biasing TFT displays. With the high current switch it is also ideal for driving high current white LEDs for flash applications. The LM3224 can be operated at switching frequencies of 615kHz and 1.25MHz allowing for easy filtering and low noise. An external compensation pin gives the user flexibility in setting frequency compensation, which makes possible the use of small, low ESR ceramic capacitors at the output. An external softstart pin allows the user to control the amount of inrush current during start up. The LM3224 is available in a low profile 8-lead VSSOP package. 1 2 * * * Operating Voltage Range of 2.7V to 7V 615kHz/1.25MHz Pin Selectable Frequency Operation Over Temperature Protection Optional Soft-Start Function 8-Lead VSSOP Package APPLICATIONS * * * * * * TFT Bias Supplies Handheld Devices Portable Applications GSM/CDMA Phones Digital Cameras White LED Flash/Torch Applications Typical Application Circuit VIN L D 5 6 3 8 Battery or Power Source CIN SW VIN FSLCT FB VC 2 VOUT GND 4 1 RC Optional RFB1 LM3224 SHDN SS 7 RFB2 COUT CSS CC 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2013, Texas Instruments Incorporated LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com Connection Diagram 1 8 VC SS FB FSLCT 7 2 3 6 SHDN VIN GND SW 4 5 Figure 1. 8-Lead Plastic VSSOP Top View Package Number DGK0008A PIN DESCRIPTIONS Pin 2 Name Function 1 VC Compensation network connection. Connected to the output of the voltage error amplifier. 2 FB Output voltage feedback input. 3 SHDN 4 GND Analog and power ground. 5 SW Power switch input. Switch connected between SW pin and GND pin. 6 VIN Analog power input. 7 FSLCT 8 SS Shutdown control input, active low. This pin has an internal pulldown resistor so the default condition is off. The pin must be pulled high to turn on the device. Switching frequency select input. VIN = 1.25MHz. Ground = 615kHz. Soft-start Pin. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 Block Diagram FSLCT | SS Duty Cycle Limit Oscillator Load Current Measurement SW + PWM COMP - - FB BG Set Reset Drive Reset Driver LOGIC ERROR AMP UVP OVP + BG Thermal SD OVP COMP + BG + Thermal Shutdown Bandgap Voltage Reference VC Shutdown Comparator SHDN UVP COMP VIN GND General Description The LM3224 utilizes a PWM control scheme to regulate the output voltage over all load conditions. The operation can best be understood referring to the block diagram and Figure 21 of the Operation section. At the start of each cycle, the oscillator sets the driver logic and turns on the NMOS power device conducting current through the inductor, cycle 1 of Figure 21 (a). During this cycle, the voltage at the VC pin controls the peak inductor current. The VC voltage will increase with larger loads and decrease with smaller. This voltage is compared with the summation of the SW voltage and the ramp compensation. The ramp compensation is used in PWM architectures to eliminate the sub-harmonic oscillations that occur during duty cycles greater than 50%. Once the summation of the ramp compensation and switch voltage equals the VC voltage, the PWM comparator resets the driver logic turning off the NMOS power device. The inductor current then flows through the schottky diode to the load and output capacitor, cycle 2 of Figure 21 (b). The NMOS power device is then set by the oscillator at the end of the period and current flows through the NMOS power device once again. The LM3224 has dedicated protection circuitry running during normal operation to protect the IC. The Thermal Shutdown circuitry turns off the NMOS power device when the die temperature reaches excessive levels. The UVP comparator protects the NMOS power device during supply power startup and shutdown to prevent operation at voltages less than the minimum input voltage. The OVP comparator is used to prevent the output voltage from rising at no loads allowing full PWM operation over all load conditions. The LM3224 also features a shutdown mode decreasing the supply current to 0.1A (typ.). These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 3 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 Absolute Maximum Ratings (1) www.ti.com (2) (2) VIN 7.5V SW Voltage 21V FB Voltage (3) 7V VC Voltage (4) 1.26V 0.3V SHDN Voltage 7.5V FSLCT 7.5V Maximum Junction Temperature 150C Power Dissipation (5) Internally Limited Lead Temperature 300C Vapor Phase (60 sec.) 215C Infrared (15 sec.) ESD Susceptibility (6) 220C Human Body Model Machine Model (1) (2) (3) (4) (5) (6) 2kV 200V If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test conditions, see the Electrical Characteristics(). The FB pin should never exceed VIN. Under normal operation the VC pin may go to voltages above this value. This maximum rating is for the possibility of a voltage being applied to the pin, however the VC pin should never have a voltage directly applied to it. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) - TA)/JA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. Operating Conditions Operating Junction Temperature Range -40C to +125C Storage Temperature -65C to +150C Supply Voltage 2.7V to 7V Maximum Output Voltage 4 20V Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 Electrical Characteristics (1) Specifications in standard type face are for TJ = 25C and those with boldface type apply over the full Operating Temperature Range ( TJ = -40C to +125C). VIN = 2.7V, FSLCT = SHDN = VIN, and IL = 0A, unless otherwise specified. Symbol IQ Typ Max (1) Units FB = 2V (Not Switching) 1.3 2.0 mA VSHDN = 0V 0.1 2.0 A 1.2285 1.26 1.2915 V 1.9 2.45 2.8 Parameter Quiescent Current VFB Feedback Voltage ICL (3) Switch Current Limit Min Conditions VIN = 2.7V (1) (4) VIN = 3V, VOUT = 8V 2.1 VIN = 3V, VOUT = 5V 2.2 2.7V VIN 7V %VFB/VIN Feedback Voltage Line Regulation IB FB Pin Bias Current ISS SS Pin Current 7.5 VSS SS Pin Voltage 1.2090 VIN Input Voltage Range gm Error Amp Transconductance AV Error Amp Voltage Gain DMAX Maximum Duty Cycle fS Switching Frequency ISHDN (5) (6) Shutdown Pin Current (2) 0.085 0.15 35 250 nA 11 13 A 1.2430 1.2622 7 V 87 135 mho 2.7 I = 5A 40 A 78 %/V V/V 85 92.5 FSLCT = Ground 450 615 750 kHz % FSLCT = VIN 0.9 1.25 1.5 MHz VSHDN = 2.7V 2.4 5.0 A VSHDN = 0.3V 0.3 1.2 IL Switch Leakage Current VSW = 20V 0.2 8.0 A RDSON Switch RDSON VIN = 2.7V, ISW = 1A 0.15 0.4 ThSHDN Shutdown Threshold Output High 1.2 Output Low UVP On Threshold (1) (2) (3) (4) (5) (6) 0.8 2.3 Off Threshold 0.8 V 0.3 2.5 2.6 V V 2.7 V All limits ensured at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely norm. Duty cycle affects current limit due to ramp generator. Current limit at 0% duty cycle. See Typical Performance Characteristics for Switch Current Limit vs. VIN Bias current flows into FB pin. The FB pin should never exceed VIN. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 5 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics SHDN Pin Current vs. SHDN Pin Voltage SS Pin Current vs. Temperature 7 11.8 11.6 VIN = 7.0V TJ = -40oC SS PIN CURRENT (PA) SHDN PIN CURRENT (PA) 6 5 TJ 4 =2 o 5C 3 2 o TJ = 125 C 1 11.4 11.2 11.0 10.8 VIN = 2.7V 10.6 10.4 0 0.0 1.0 2.0 4.0 3.0 5.0 6.0 10.2 -40 -25 -10 5 7.0 SHDN PIN VOLTAGE (V) TEMPERATURE (oC) Figure 2. Figure 3. FSLCT Pin Current vs. FSLCT Pin Voltage FB Pin Current vs. Temperature 70 8 FSLCT = VIN FB = 1.265V 60 TJ = -40oC 5 FB PIN CURRENT (nA) FSLCT PIN CURRENT (PA) 7 6 o TJ = 25 C 4 3 TJ = 125oC 2 50 40 VIN = 2.7V 30 VIN = 7.0V 20 10 1 0 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 7.0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 FSLCT VOLTAGE (V) TEMPERATURE (oC) Figure 4. Figure 5. NMOS RDSON vs. Input Voltage 0.23 615kHz Non-switching IQ vs. Input Voltage 1.8 ISW = 1.5A 0.21 NON-SWITCHING IQ (mA) 1.7 NMOS RDSON (:) 0.19 0.17 o TA = 85 C 0.15 0.13 0.11 TA = 25oC 0.09 0.07 TA = -40oC 1.6 TJ = 125oC 1.5 1.4 TJ = 25oC TJ = -40oC 1.3 1.2 1.1 0.05 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 7.0 INPUT VOLTAGE (V) 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 INPUT VOLTAGE (V) Figure 6. 6 20 35 50 65 80 95 110 125 Figure 7. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 Typical Performance Characteristics (continued) 1.25MHz Non-switching IQ vs. Input Voltage 615kHz Switching IQ vs. Input Voltage 2.0 4.5 1.7 1.6 1.5 TJ = -40oC 4.0 1.8 SWITCHING IQ (mA) NON-SWITCHING IQ (mA) 1.9 TJ = 125oC TJ = 25oC 1.4 TJ = -40oC 1.3 3.5 TJ = 25oC 3.0 TJ = 125oC 2.5 2.0 1.2 1.5 1.1 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 8. Figure 9. 1.25MHz Switching IQ vs. Input Voltage 8.0 615kHz Switching IQ vs. Temperature 4.50 o TJ = -40 C 4.25 7.0 VIN = 7.0V 5.0 4.0 SWITCHING IQ (mA) SWITCHING IQ (mA) 4.00 6.0 TJ = 25oC TJ = 125oC 3.0 2.0 3.75 3.50 3.25 3.00 2.75 2.50 2.25 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) INPUT VOLTAGE (V) Figure 10. Figure 11. 1.25MHz Switching IQ vs. Temperature 615kHz Switching Frequency vs. Temperature 7.5 640 SWITCHING FREQUENCY (kHz) 7.0 VIN = 7.0V 6.5 SWITCHING IQ (mA) VIN = 2.7V 1.0 6.0 5.5 5.0 4.5 4.0 3.5 VIN = 2.7V 3.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) 630 620 VIN = 7.0V 610 600 VIN = 2.7V 590 580 570 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 7 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 1.25MHz Switching Frequency vs. Temperature 615kHz Maximum Duty Cycle vs. Temperature 94.0 VIN = 7.0V 1.32 VIN = 7.0V MAXIMUM DUTY CYCLE (%) SWITCHING FREQUENCY (MHz) 1.34 1.30 1.28 1.26 1.24 VIN = 2.7V 1.22 1.20 93.5 93.0 92.5 VIN = 2.7V 92.0 1.18 1.16 -40 -25 -10 5 20 35 50 65 80 95 110 125 91.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) TEMPERATURE (oC) Figure 14. Figure 15. 1.25MHz Maximum Duty Cycle vs. Temperature Switch Current Limit vs. VIN 2.3 94.0 2.2 VIN = 7.0V 93.0 2.1 CURRENT LIMIT (A) MAXIMUM DUTY CYCLE (%) 93.5 92.5 92.0 91.5 VIN = 2.7V VOUT = 8V 2.0 1.9 VOUT = 12V 1.8 91.0 1.7 90.5 1.6 VOUT = 15V 90.0 -40 -25 -10 5 1.5 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 20 35 50 65 80 95 110 125 INPUT VOLTAGE (V) TEMPERATURE (oC) Figure 16. Figure 17. Switch Current Limit vs. Temperature Switch Current Limit vs. Temperature 2.20 2.10 VOUT = 8V VIN = 3.0V 2.00 2.10 VIN = 3.0V CURRENT LIMIT (A) CURRENT LIMIT (A) VOUT = 15V VIN = 5.5V 2.15 2.05 2.00 VIN = 4.2V 1.95 1.90 1.90 VIN = 4.2V 1.80 1.70 VIN = 5.5V 1.60 1.85 1.50 1.80 1.75 -40 -20 -30 0 -10 20 10 40 30 60 50 1.40 -40 80 70 90 TEMPERATURE (oC) TEMPERATURE (oC) Figure 18. 8 -20 0 20 40 60 80 -30 -10 10 30 50 70 90 Figure 19. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 Typical Performance Characteristics (continued) 1.25MHz Efficiency vs. Load Current 100 90 EFFICIENCY (%) 80 V OUT =8V V IN = 2.7V VIN =5.5V 70 V IN = 3.3V 60 VIN = 4. 2V 50 40 30 20 10 0 0. 1 1 10 100 1000 10000 LOAD CURRENT (mA) Figure 20. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 9 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com OPERATION L D COUT VIN RLOAD PWM L X + + L COUT VIN R LOAD V IN COUT R LOAD V OUT V OUT - - Cycle 1 (a) Cycle 2 (b) Figure 21. Simplified Boost Converter Diagram (a) First Cycle of Operation (b) Second Cycle Of Operation CONTINUOUS CONDUCTION MODE The LM3224 is a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a higher output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator operates in two cycles. In the first cycle of operation, shown in Figure 21 (a), the transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is supplied by COUT. The second cycle is shown in Figure 21 (b). During this cycle, the transistor is open and the diode is forward biased. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as: VOUT = VIN 1-D , D' = (1-D) = VIN VOUT where * D is the duty cycle of the switch (1) D and D will be required for design calculations. SETTING THE OUTPUT VOLTAGE The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in the typical operating circuit. The feedback pin voltage is 1.26V, so the ratio of the feedback resistors sets the output voltage according to the following equation: VOUT - 1.26 : RFB1 = RFB2 x 1.26 (2) 10 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 SOFT-START CAPACITOR The LM3224 has a soft-start pin that can be used to limit the inductor inrush current on start-up. The external SS pin is used to tailor the soft-start for a specific application but is not required for all applications and can be left open when not needed. When used, a current source charges the external soft-start capacitor, Css. The softstart time can be estimated as: Tss = Css*1.24V/Iss (3) THERMAL SHUTDOWN The LM3224 includes thermal shutdown protection. If the die temperature exceeds 140C the regulator will shut off the power switch, significantly reducing power dissipation in the device. The switch will remain off until the die temperature is reduced to approximately 120C. If the cause of the excess heating is not removed (excessive ambient temperature, excessive power dissipation, or both) the device will continue to cycle on and off in this manner to protect from damage. INTRODUCTION TO COMPENSATION IL (A) VIN VOUT L VIN L 'i L IL_AVG t (s) D*Ts Ts (a) ID (A) VIN VOUT L ID_AVG =IOUT_AVG t (s) D*Ts Ts (b) Figure 22. (a) Inductor current. (b) Diode current. The LM3224 is a current mode PWM boost converter. The signal flow of this control scheme has two feedback loops, one that senses switch current and one that senses output voltage. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 11 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through the inductor (see Figure 22 (a)). If the slope of the inductor current is too great, the circuit will be unstable above duty cycles of 50%. A 10H to 15H inductor is recommended for most 615 kHz applications, while a 4.7H to 10H inductor may be used for most 1.25 MHz applications. If the duty cycle is approaching the maximum of 85%, it may be necessary to increase the inductance by as much as 2X. See Inductor and Diode Selection for more detailed inductor sizing. The LM3224 provides a compensation pin (VC) to customize the voltage loop feedback. It is recommended that a series combination of RC and CC be used for the compensation network, as shown in the typical application circuit. For any given application, there exists a unique combination of RC and CC that will optimize the performance of the LM3224 circuit in terms of its transient response. The series combination of RC and CC introduces a pole-zero pair according to the following equations: fZC = 1 Hz 2SRCCC (4) 1 fPC = Hz 2S(RC + RO)CC where * RO is the output impedance of the error amplifier (approximately 900k) (5) For most applications, performance can be optimized by choosing values within the range 5k RC 100k (RC can be up to 200k if CC2 is used, see High Output Capacitor ESR Compensation) and 680pF CC 10nF. Refer to the Applications Information section for recommended values for specific circuits and conditions. Refer to the Compensation section for other design requirement. COMPENSATION This section will present a general design procedure to help insure a stable and operational circuit. The designs in this datasheet are optimized for particular requirements. If different conversions are required, some of the components may need to be changed to ensure stability. Below is a set of general guidelines in designing a stable circuit for continuous conduction operation, in most all cases this will provide for stability during discontinuous operation as well. The power components and their effects will be determined first, then the compensation components will be chosen to produce stability. INDUCTOR AND DIODE SELECTION Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value determined by the minimum input voltage and the maximum output voltage. This equation is: L> VINRDSON 0.144 fs D -1 ( D' ) (in H) where * * * fs is the switching frequency D is the duty cycl RDSON is the ON resistance of the internal switch taken from the graph "NMOS RDSON vs. Input Voltage" in the Typical Performance Characteristics section. (6) This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the recommended values may be used. The corresponding inductor current ripple as shown in Figure 22 (a) is given by: VIND (in Amps) 'iL = 2Lfs (7) 12 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be the average inductor current (input current or ILOAD/D') plus iL. As a side note, discontinuous operation occurs when the inductor current falls to zero during a switching cycle, or iL is greater than the average inductor current. Therefore, continuous conduction mode occurs when iL is less than the average inductor current. Care must be taken to make sure that the switch will not reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a saturation current rating higher than the peak inductor current expected. The output voltage ripple is also affected by the total ripple current. The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output current. The typical current waveform for the diode in continuous conduction mode is shown in Figure 22 (b). The diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. During short circuit testing, or if short circuit conditions are possible in the application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower forward voltage drop will decrease power dissipation and increase efficiency. DC GAIN AND OPEN-LOOP GAIN Since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. A high phase margin (greater than 45) is desired for the best stability and transient response. For the purpose of stabilizing the LM3224, choosing a crossover point well below where the right half plane zero is located will ensure sufficient phase margin. To ensure a bandwidth of 1/2 or less of the frequency of the RHP zero, calculate the open-loop DC gain, ADC. After this value is known, you can calculate the crossover visually by placing a -20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is less than 1/2 the RHP zero, the phase margin should be high enough for stability. The phase margin can also be improved by adding CC2 as discussed later in this section. The equation for ADC is given below with additional equations required for the calculation: gmROD' RFB2 {[(ZcLeff)// RL]//RL} (in dB) ADC(DB) = 20log10 RFB1 + RFB2 RDSON ) ( (8) 2fs Zc # nD' Leff = n = 1+ (in rad/s) (9) L (D')2 (10) 2mc (no unit) m1 (11) (12) mc 0.072fs (in V/s) m1 # VINRDSON L (in V/s) where * * * * RL is the minimum load resistance VIN is the minimum input voltage gm is the error amplifier transconductance found in the Electrical Characteristics table RDSON is the value chosen from the graph "NMOS RDSON vs. Input Voltage" in the Typical Performance Characteristics section Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 (13) 13 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com INPUT AND OUTPUT CAPACITOR SELECTION The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of the regulator is very close to the source output. The size will generally need to be larger for applications where the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value of 10F should be used for the less stressful condtions while a 22F to 47F capacitor may be required for higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very low ripple on the input source voltage. The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted RESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require more compensation which will be explained later on in the section. The ESR is also important because it determines the peak to peak output voltage ripple according to the approximate equation: VOUT 2iLRESR (in Volts) (14) A minimum value of 10F is recommended and may be increased to a larger value. After choosing the output capacitor you can determine a pole-zero pair introduced into the control loop by the following equations: fP1 = fZ1 = 1 (in Hz) 2S(RESR + RL)COUT (15) 1 (in Hz) 2SRESRCOUT where * RL is the minimum load resistance corresponding to the maximum load current (16) The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the High Output Capacitor ESR Compensation section. Some suitable capacitor vendors include Vishay, Taiyo-Yuden, and TDK. RIGHT HALF PLANE ZERO A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90 in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than 1/2 the frequency of the RHP zero. This zero occurs at a frequency of: VOUT(D')2 (in Hz) RHPzero = 2S,LOADL where * ILOAD is the maximum load current. (17) SELECTING THE COMPENSATION COMPONENTS The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to Compensation section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is determined by the equation: fPC = 1 (in Hz) 2S(RC + RO)CC where * 14 RO is the output impedance of the error amplifier, approximately 900k Submit Documentation Feedback (18) Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 Since RC is generally much less than RO, it does not have much effect on the above equation and can be neglected until a value is chosen to set the zero fZC. fZC is created to cancel out the pole created by the output capacitor, fP1. The output capacitor pole will shift with different load currents as shown by the equation, so setting the zero is not exact. Determine the range of fP1 over the expected loads and then set the zero fZC to a point approximately in the middle. The frequency of this zero is determined by: fZC = 1 (in Hz) 2SCCRC (19) Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to 500Hz range, change each value slightly if needed to ensure both component values are in the recommended range. HIGH OUTPUT CAPACITOR ESR COMPENSATION When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole follows: 1 (in Hz) fPC2 = 2SCC2(RC //RO) (20) To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC, fPC2 must be greater than 10fZC. CHECKING THE DESIGN With all the poles and zeros calculated the crossover frequency can be checked as described in the section DC Gain and Open-loop Gain. The compensation values can be changed a little more to optimize performance if desired. This is best done in the lab on a bench, checking the load step response with different values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a stable, high performance circuit. For improved transient response, higher values of RC should be chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to transients. If more detail is required, or the most optimum performance is desired, refer to a more in depth discussion of compensating current mode DC/DC switching regulators. POWER DISSIPATION The output power of the LM3224 is limited by its maximum power dissipation. The maximum power dissipation is determined by the formula PD = (Tjmax - TA)/JA where * * * Tjmax is the maximum specidfied junction temperature (125C) TA is the ambient temperature JA is the thermal resistance of the package (21) LAYOUT CONSIDERATIONS The input bypass capacitor CIN, as shown in the typical operating circuit, must be placed close to the IC. This will reduce copper trace resistance which effects input voltage ripple of the IC. For additional input voltage filtering, a 100nF bypass capacitor can be placed in parallel with CIN, close to the VIN pin, to shunt any high frequency noise to ground. The output capacitor, COUT, should also be placed close to the IC. Any copper trace connections for the COUT capacitor can increase the series resistance, which directly effects output voltage ripple. The feedback network, resistors RFB1 and RFB2, should be kept close to the FB pin, and away from the inductor, to minimize copper trace connections that can inject noise into the system. Trace connections made to the inductor and schottky diode should be minimized to reduce power dissipation and increase overall efficiency. For more detail on switching power supply layout considerations see Application Note Layout Guidelines for Switching Power Supplies (SNVA021). Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 15 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION D5 D4 L 10 PH 23V D7 C6 1 PF C5 1 PF C4 1 PF VIN = 2.7V - 5.5V D6 C7 1 PF C1 4.7 PF D1 D3 -8V C2 D2 4.7 PF 5 SW 7 6 FSLCT VIN 3 RFB1 LM3224 SHDN 8V 160k 8 SS VC GND 4 1 CIN 22 PF RC 30k CSS RFB2 COUT1 COUT2 30k 10 PF 10 PF CC2 68 pF CC 1 nF Figure 23. Triple Output TFT Bias (615 kHz operation) TRIPLE OUTPUT TFT BIAS The circuit in Figure 23 shows how the LM3224 can be configured to provide outputs of 8V, -8V, and 23V, convenient for biasing TFT displays. The 8V output is regulated, while the -8V and 23V outputs are unregulated. The 8V output is generated by a typical boost topology. The basic operation of the boost converter is described in the OPERATION section. The output voltage is set with RFB1 and RFB2 by: RFB1 = RFB2 VOUT - 1.26 1.26 : (22) The compensation network of RC and CC are chosen to optimally stabilize the converter. The inductor also affects the stability. When operating at 615 kHz, a 10uH inductor is recommended to insure the converter is stable at duty cycles greater than 50%. Refer to the COMPENSATION section for more information. The -8V output is derived from a diode inverter. During the second cycle, when the transistor is open, D2 conducts and C1 charges to 8V minus a diode drop (0.4V if using a Schottky). When the transistor opens in the first cycle, D3 conducts and C1's polarity is reversed with respect to the output at C2, producing -8V. 16 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 The 23V output is realized with a series of capacitor charge pumps. It consists of four stages: the first stage includes C4, D4, and the LM3224 switch; the second stage uses C5, D5, and D1; the third stage includes C6, D6, and the LM3224 switch; the final stage is C7 and D7. In the first stage, C4 charges to 8V when the LM3224 switch is closed, which causes D5 to conduct when the switch is open. In the second stage, the voltage across C5 is VC4 + VD1 - VD5 = VC4 8V when the switch is open. However, because C5 is referenced to the 8V output, the voltage at C5 is 16V when referenced to ground. In the third stage, the 16V at C5 appears across C6 when the switch is closed. When the switch opens, C6 is referenced to the 8V output minus a diode drop, which raises the voltage at C6 with respect to ground to about 24V. Hence, in the fourth stage, C7 is charged to 24V when the switch is open. From the first stage to the last, there are three diode drops that make the output voltage closer to 24 - 3xVDIODE (about 22.8V if a 0.4V forward drop is assumed). L 4.7 PH 2.9V - 4.2V D 5 6 3 8 Battery or Power Source SW FSLCT VIN SHDN FB VC 22 PF High Current White LED LM3224 SS CIN 7 2 GND 1 4 RSET 1.8: (700 mA) RC COUT 10 PF ceramic 2k Pull high for FLASH or constant full current, PWM for TORCH or partial current. Optional Disconnect FET CC 2.2 nF Figure 24. PWM White LED Flash/Torch Driver L 4.7 PH 2.9V - 4.2V D 5 6 3 8 Battery or Power Source SW FSLCT VIN SHDN 22 PF FB SS 2 GND 1 4 RC 2k Pull high for TORCH. Pull Flash Enable high for FLASH. High Current White LED LM3224 VC CIN 7 CC 2.2 nF RTORCH RFLASH 6.2: (200 mA) 2.55: (500 mA) Torch Enable Flash Enable COUT 10 PF ceramic Figure 25. Continuously Operating White LED Flash/Torch Driver Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 17 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com The LM3224 can be configured to drive high current white LEDs for the flash and torch functions of a digital camera, camera phone, or any other similar light source. The flash/torch can be set up with the circuit in Figure 24 by using the resistor RSET to determine the amount of current that will flow through the LED using the equation: ILED = VFB/RSET (23) If the flash and torch modes will both be used the resistor RSET can be chosen for the higher current flash value. To flash the circuit pull the SHDN high for the time duration needed for the flash. To enable a lower current torch mode a PWM signal can be applied to the SHDN pin. The torch current would then be approximately the percent ON time of the PWM signal multiplied by the flash (or maximum) current. The optional disconnect FET can be used to eliminate leakage current through the LEDs when the part is off and also to disconnect the LED when the input voltage exceeds the forward voltage drop of the LED. The maximum output current the LM3224 can supply in this configuration is shown in Table 1. Figure 25 is another method of driving a high current white LED. This circuit has a higher component count but allows the switcher to remain on continuously for torch mode reducing stress on the supply. The two FETs also double for a disconnect function as described above. In this circuit the device and the torch enable FET are turned on setting a lower current through the LED. When flash is needed the flash enable FET is turned on to increase the current for the amount of time desired. The minimum ensured maximum output current for this circuit is the same as for Figure 24. Table 1. Maximum LED Drive current (FSW=1.25MHz, L=4.7H, LED VFMAX=4V (VOUT=5.26V) VIN LED Drive Current (mA) 4.2 1077 4.1 1047 4.0 1017 3.9 987 3.8 958 3.7 929 3.6 900 3.5 871 3.4 842 3.3 814 3.2 785 3.1 757 3.0 729 2.9 701 2.8 673 2.7 646 Table 2. Some Recommended Inductors (Others May Be Used) 18 Manufacturer Inductor Contact Information Coilcraft DO3316 and DT3316 series www.coilcraft.com 800-3222645 TDK SLF10145 series www.component.tdk.com 847-803-6100 Pulse P0751 and P0762 series www.pulseeng.com Sumida CDRH8D28 and CDRH8D43 series www.sumida.com Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 Table 3. Some Recommended Input And Output Capacitors (Others May Be Used) Manufacturer Capacitor Contact Information Vishay Sprague 293D, 592D, and 595D series tantalum www.vishay.com 407-324-4140 Taiyo Yuden High capacitance MLCC ceramic www.t-yuden.com 408-573-4150 Cornell Dubilier ESRD seriec Polymer Aluminum Electrolytic SPV and AFK series V-chip series www.cde.com MuRata High capacitance MLCC ceramic www.murata.com L 4.7 PH 2.7V - 4.2V 5 6 3 8 Battery or Power Source 5V, 650 mA D 20.5k SW FSLCT VIN SHDN LM3224 FB SS VC CIN 22 PF 7 2 GND 1 4 COUT RC 10 PF ceramic 20k 6.98k CC 1 nF Figure 26. 1.25MHz, 5V Output L 10 PH 2.9V - 4.2V 5 6 3 8 Battery or Power Source 8V, 500mA D 160k SW FSLCT VIN SHDN SS CIN 22 PF 7 LM3224 FB VC 2 GND 1 4 COUT RC 30k 30k CC2 22 PF ceramic 68 pF CC 1 nF Figure 27. 1.25MHz, 8V Output Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 19 LM3224 SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 www.ti.com L 10 PH 2.9V - 4.2V 5 6 3 8 Battery or Power Source 12V, 300mA D 332k SW FSLCT VIN SHDN SS CIN LM3224 FB VC 22 PF 7 2 GND 1 4 COUT RC 22 PF ceramic 40.2k 39.2k CC 1.5 nF Figure 28. 1.25MHz, 12V Output L 15 PH 2.9V - 4.2V 5 6 3 8 Battery or Power Source CIN 22 PF 15V, 220mA D 301k SW FSLCT VIN SHDN SS 7 LM3224 FB VC 2 GND 1 4 COUT RC 40.2k 27.4k 22 PF ceramic CC 1.5 nF Figure 29. 1.25MHz, 15V Output 20 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 LM3224 www.ti.com SNVS277C - DECEMBER 2004 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM3224 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) LM3224MM-ADJ/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3224MMX-ADJ/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM (4) -40 to 125 SEKB SEKB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM3224MM-ADJ/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3224MMX-ADJ/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3224MM-ADJ/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM3224MMX-ADJ/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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