Features
•EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
•Supports both 3.3V and 5.0V Operating Voltage Applications
•In-System Programmable (ISP) via Two-Wire Bus
•Simple Interface to SRAM FPGAs
•Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera® FLEX®, APEX™
Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs
•Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
•Very Low-power CMOS EEPROM Process
•Programmable Reset Polarity
•Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP
Packages
•Emulation of Atmel’s AT24CXXX Serial EEPROMs
•Low-power Standby Mode
•High-reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
•Green (Pb/Halide-free/RoHS Compliant) Package Options Available
1. Description
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-
lead PLCC, 20-lead SOIC and 44-lead TQFP, see Table 1-1. The AT17LV series
Configurators uses a simple serial-access procedure to configure one or more FPGA
devices. The user can select the polarity of the reset function by programming four
EEPROM bytes. These devices also support a write-protection mechanism within its
programming mode.
The AT17LV series configurators can be programmed with industry-standard pro-
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
FPGA
Configuration
EEPROM
Memory
AT17LV65
AT17LV128
AT17LV256
AT17LV512
AT17LV010
AT17LV002
AT17LV040
3.3V and 5V
System Support
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Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC
package is not available for the AT17LV512/010/002 devices, it is possible to use an 8-lead
LAP package instead.
2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the
AT17LV512/010/002 devices.
3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.
2. Pin Configuration
Figure 2-1. 8-lead LAP
Figure 2-2. 8-lead SOIC
Figure 2-3. 8-lead PDIP
Table 1-1. AT17LV Series Packages
Package
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010 AT17LV002 AT17LV040
8-lead LAP Yes Yes Yes (3)
8-lead PDIP Yes Yes – –
8-lead SOIC Yes Use 8-lead
LAP(1)
Use 8-lead
LAP(1) (3)
20-lead PLCC Yes Yes Yes –
20-lead SOIC Yes(2) Ye s (2) Ye s (2) –
44-lead TQFP – – Yes Yes
8
7
6
5
1
2
3
4
DATA
CLK
(WP(1)) RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
1
2
3
4
8
7
6
5
DATA
CLK
(WP(1)) RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
1
2
3
4
8
7
6
5
DATA
CLK
(WP(1)) RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
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AT17LV65/128/256/512/010/002/040
Figure 2-4. 20-lead PLCC
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
3. The CEO feature is not available on the AT17LV65 device.
Figure 2-5. 20-lead SOIC(1)
Note: 1. This pinout only applies to AT17LV65/128/256 devices.
4
5
6
7
8
18
17
16
15
14
CLK
(WP1(2)) NC
(WP(1)) RESET/OE
(WP2(2)) NC
CE
NC
SER_EN
NC
NC (READY(2))
CEO (A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
NC
NC
NC
NC
DATA
NC
VCC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
DATA
NC
CLK
NC
RESET/OE
NC
CE
NC
GND
VCC
NC
NC
SER_EN
NC
NC
CEO (A2)
NC
NC
NC
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AT17LV65/128/256/512/010/002/040
Figure 2-6. 20-lead SOIC(1)
Notes: 1. This pinout only applies to AT17LV512/010/002 devices.
2. The CEO feature is not available on the AT17LV65 device.
Figure 2-7. 44 TQFP
Note: 1. This pin is only available on AT17LV002 devices.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA
NC
CLK
NC
NC
NC
NC
RESET/OE
NC
CE
VCC
NC
SER_EN
NC
NC
NC
NC
CEO
NC
GND
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO(A2)
NC
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
(WP1(1))
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
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AT17LV65/128/256/512/010/002/040
Figure 2-8. Block Diagram
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
3. The CEO feature is not available on the AT17LV65 device.
POWER ON
RESET
SER_EN
WP1(2)
WP2(2)
(1)
READY(2)
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3. Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly
with the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA
output pin and enable the address counter. When RESET/OE is driven High, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the
output of the AT17LV series configurator. If CE is held High after the RESET/OE reset pulse, the
counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low,
the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the
address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
Note: 1. The CEO feature is not available on the AT17LV65 device.
4. Pin Description
Name I/O
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010 AT17LV002 AT17LV040
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
8
DIP/
LAP
20
PLCC
20
SOIC
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
44
TQFP
44
TQFP
DATAI/O12212112140 40
CLKI24424324343 43
WP1I––––5––5–– –
RESET/OEI36636836813 13
WP2I –7––7–– –
CE I4884810481015 15
GND 51010510115101118 18
CEO O
61414614
13
614
13
21 21
A2 I – –
READYO––––15––15–23 23
SER_EN I71717717187171835 35
VCC 82020820208202038 38
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4.1 DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4.2 CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
4.3 WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
4.4 RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
4.5 WP
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low). When WP
is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on AT17LV65/128/256 devices.
4.6 WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010 devices.
4.7 CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low).
4.8 GND
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
4.9 CEO
Chip Enable Output (active Low). This output goes Low when the address counter has reached
its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of one device must
be connected to the CE input of the next device in the chain. It will stay Low as long as CE is
Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until
the entire EEPROM is read again. This CEO feature is not available on the AT17LV65 device.
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AT17LV65/128/256/512/010/002/040
4.10 A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
4.11 READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used.
4.12 SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC.
4.13 VCC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
5. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17LV Serial Configuration EEPROM has
been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
6. Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and
self-explanatory.
• The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.
• The CEO output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
•SER_EN
must be connected to VCC (except during ISP).
• The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Note: 1. This pin is not available for the AT17LV65/128/256 devices.
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AT17LV65/128/256/512/010/002/040
7. Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
CEO output Low and disables its DATA line driver. The second configurator recognizes the Low
level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (High) level.
The AT17LV65 devices do not have the CEO feature to perform cascaded configurations.
8. AT17LV Series Reset Polarity
The AT17LV series configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro-
grammed by the Two-Wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip.
10. Standby Mode
The AT17LV series configurators enter a low-power standby mode whenever CE is asserted
High. In this mode, the AT17LV65/128/256 configurator consumes less than 50 µA of current at
3.3V (100 µA for the AT17LV512/010 and 200 µA for the AT17LV002/040). The output remains
in a high-impedance state regardless of the state of the OE input.
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AT17LV65/128/256/512/010/002/040
11. Absolute Maximum Ratings*
Operating Temperature................................... -40°C to +85°C*NOTICE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature .................................... -65 °C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
12. Operating Conditions
Symbol Description
3.3V 5V
UnitsMin Max Min Max
VCC
Commercial Supply voltage relative to GND
-0°C to +70°C3.0 3.6 4.75 5.25 V
Industrial Supply voltage relative to GND
-40°C to +85°C3.0 3.6 4.5 5.5 V
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AT17LV65/128/256/512/010/002/040
13. DC Characteristics
VCC = 3.3V ± 10%
Symbol Description
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002/
AT17LV040
UnitsMin Max Min Max Min Max
VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V
VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V
VOH High-level Output Voltage (IOH = -2.5 mA)
Commercial
2.4 2.4 2.4 V
VOL Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 0.4 V
VOH High-level Output Voltage (IOH = -2 mA)
Industrial
2.4 2.4 2.4 V
VOL Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 0.4 V
ICCA Supply Current, Active Mode 5 5 5 mA
ILInput or Output Leakage Current (VIN = VCC or GND) -10 10 -10 10 -10 10 µA
ICCS Supply Current, Standby Mode
Commercial 50 100 150 µA
Industrial 100 100 150 µA
14. DC Characteristics
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol Description
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002/
AT17LV040
UnitsMin Max Min Max Min Max
VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V
VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V
VOH High-level Output Voltage (IOH = -2.5 mA)
Commercial
3.7 3.86 3.86 V
VOL Low-level Output Voltage (IOL = +3 mA) 0.32 0.32 0.32 V
VOH High-level Output Voltage (IOH = -2 mA)
Industrial
3.6 3.76 3.76 V
VOL Low-level Output Voltage (IOL = +3 mA) 0.37 0.37 0.37 V
ICCA Supply Current, Active Mode 10 10 10 mA
ILInput or Output Leakage Current (VIN = VCC or GND) -10 10 -10 10 -10 10 µA
ICCS Supply Current, Standby Mode
Commercial 75 200 350 µA
Industrial 150 200 350 µA
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AT17LV65/128/256/512/010/002/040
15. AC Waveforms
16. AC Waveforms when Cascading
CE
RESET/OE
CLK
DATA
TSCE
TLC THC
TCAC
TOE
TCE
TOH
THOE
TSCE THCE
TDF
TOH
CE
RESET/OE
CLK
DATA
CEO
T
CDF
T
OCK
T
OCE
T
OCE
T
OOE
LAST BIT FIRST BIT
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AT17LV65/128/256/512/010/002/040
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
17. AC Characteristics
VCC = 3.3V ± 10%
Symbol Description
AT17LV65/128/256 AT17LV512/010/002/040
Units
Commercial Industrial Commercial Industrial
Min Max Min Max Min Max Min Max
TOE(1) OE to Data Delay 50 55 50 55 ns
TCE(1) CE to Data Delay 60 60 55 60 ns
TCAC(1) CLK to Data Delay 75 80 55 60 ns
TOH Data Hold from CE, OE, or CLK 0 0 0 0 ns
TDF(2) CE or OE to Data Float Delay 55 55 50 50 ns
TLC CLK Low Time 25 25 25 25 ns
THC CLK High Time 25 25 25 25 ns
TSCE
CE Setup Time to CLK
(to guarantee proper counting) 35 60 30 35 ns
THCE
CE Hold Time from CLK
(to guarantee proper counting) 0000 ns
THOE OE High Time (guarantees counter is reset) 25 25 25 25 ns
FMAX Maximum Clock Frequency 10 10 15 10 MHz
18. AC Characteristics when Cascading
VCC = 3.3V ± 10%
Symbol Description
AT17LV65/128/256 AT17LV512/010/002/040
Units
Commercial Industrial Commercial Industrial
Min Max Min Max Min Max Min Max
TCDF(2) CLK to Data Float Delay 60 60 50 50 ns
TOCK(1) CLK to CEO Delay 55605055ns
TOCE(1) CE to CEO Delay 55603540ns
TOOE(1) RESET/OE to CEO Delay 40453535ns
FMAX Maximum Clock Frequency 8 8 12.5 10 MHz
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AT17LV65/128/256/512/010/002/040
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
19. AC Characteristics
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol Description
AT17LV65/128/256 AT17LV512/010/002/040
Units
Commercial Industrial Commercial Industrial
Min Max Min Max Min Max Min Max
TOE(1) OE to Data Delay 30 35 30 35 ns
TCE(1) CE to Data Delay 45 45 45 45 ns
TCAC(1) CLK to Data Delay 50 55 50 50 ns
TOH Data Hold from CE, OE, or CLK 0 0 0 0 ns
TDF(2) CE or OE to Data Float Delay 50 50 50 50 ns
TLC CLK Low Time 20 20 20 20 ns
THC CLK High Time 20 20 20 20 ns
TSCE
CE Setup Time to CLK (to guarantee proper
counting) 35 40 20 25 ns
THCE
CE Hold Time from CLK (to guarantee proper
counting) 0000 ns
THOE OE High Time (guarantees counter is reset) 20 20 20 20 ns
FMAX Maximum Clock Frequency 12.5 12.5 15 15 MHz
20. AC Characteristics when Cascading
VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol Description
AT17LV65/128/256 AT17LV512/010/002/040
Units
Commercial Industrial Commercial Industrial
Min Max Min Max Min Max Min Max
TCDF(2) CLK to Data Float Delay 50 50 50 50 ns
TOCK(1) CLK to CEO Delay 35403540ns
TOCE(1) CE to CEO Delay 35 35 35 35 ns
TOOE(1) RESET/OE to CEO Delay 30 35 30 30 ns
FMAX Maximum Clock Frequency 10 10 12.5 12.5 MHz
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Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site.
2. Airflow = 0 ft/min.
21. Thermal Resistance Coefficients(1)
Package Type
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010 AT17LV002 AT17LV040
8CN
4Leadless Array Package (LAP)
θJC [°C/W] 45 45 45 –
θJA
[°C/W](2) 115.71 135.71 159.60 –
8P3 Plastic Dual Inline Package
(PDIP)
θJC [°C/W] 37 37 – –
θJA
[°C/W](2) 107 107 – –
8S1 Plastic Gull Wing Small Outline
(SOIC)
θJC [°C/W]45–––
θJA
[°C/W](2) 150–––
20J Plastic Leaded Chip Carrier
(PLCC)
θJC [°C/W] 35 35 35 –
θJA
[°C/W](2) 90 90 90 –
20S2 Plastic Gull Wing Small Outline
(SOIC)
θJC [°C/W] –
θJA
[°C/W](2) –
44A Thin Plastic Quad Flat
Package (TQFP)
θJC [°C/W] – – 17 17
θJA
[°C/W](2) – – 62 62
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AT17LV65/128/256/512/010/002/040
Figure 21-1. Ordering Code
Package Type
8CN4 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)
20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
Vo l t a g e Size (Bits) Special Pinouts Package Te m p e r a t u r e
65 = 65K A = Altera 8CN4 C = Commercial
128 = 128K Blank = Xilinx/Atmel/ = 8P3 I = Industrial
256 = 256K = 8S1
512 = 512K = 20J
010 = 1M
= 44A
002 = 2M
= 44J
040 = 4M
AT17LV65A-10PC
C
P
N
J
S
TQ
BJ
=
3.0V to 5.5V
Other
= 20S2
U = Fully Green
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22. Ordering Information
Notes: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics.
2. For the -10SC and -10SI packages, customers may migrate to the AT17LVXXX-10SU.
3. For the -10TQC and -10TQI packages, customers may migrate to the AT17LVXXX-10TQU.
22.1 Standard Package Options
Memory Size Ordering Code Package(2)(3) Operation Range
64-Kbit(1)
AT17LV65-10PC 8P3 Commercial
(0°C to 70°C)
AT17LV65-10NC 8S1
AT17LV65-10JC 20J
AT17LV65-10PI 8P3 Industrial
(-40°C to 85°C)
AT17LV65-10NI 8S1
AT17LV65-10JI 20J
128-Kbit(1)
AT17LV128-10PC 8P3
Commercial
(0°C to 70°C)
AT17LV128-10NC 8S1
AT17LV128-10JC 20J
AT17LV128-10SC 20S2
AT17LV128-10PI 8P3
Industrial
(-40°C to 85°C)
AT17LV128-10NI 8S1
AT17LV128-10JI 20J
AT17LV128-10SI 20S2
256-Kbit(1)
AT17LV256-10PC 8P3
Commercial
(0°C to 70°C)
AT17LV256-10NC 8S1
AT17LV256-10JC 20J
AT17LV256-10SC 20S2
AT17LV256-10PI 8P3
Industrial
(-40°C to 85°C)
AT17LV256-10NI 8S1
AT17LV256-10JI 20J
AT17LV256-10SI 20S2
512-Kbit(1)
AT17LV512-10PC 8P3 Commercial
(0°C to 70°C)
AT17LV512-10JC 20J
AT17LV512-10PI 8P3 Industrial
(-40°C to 85°C)
AT17LV512-10JI 20J
1-Mbit(1)
AT17LV010-10PC 8P3 Commercial
(0°C to 70°C)
AT17LV010-10JC 20J
AT17LV010-10PI 8P3 Industrial
(-40°C to 85°C)
AT17LV010-10JI 20J
2-Mbit(1)
AT17LV002-10JC 20J Commercial
(0°C to 70°C)
AT17LV002-10JI 20J Industrial
(-40°C to 85°C)
18
2321I–CNFG–2/08
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Note: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics.
22.2 Green Package Options (Pb/Halide-free/RoHS Compliant)
Memory Size Ordering Code Package Operation Range
256-Kbit(1)
AT17LV256-10CU 8CN4
Industrial
(-40°C to 85°C)
AT17LV256-10JU 20J
AT17LV256-10NU 8S1
AT17LV256-10PU 8P3
AT17LV256-10SU 20S2
512-Kbit(1) AT17LV512-10CU 8CN4
AT17LV512-10JU 20J
1-Mbit(1)
AT17LV010-10CU 8CN4
AT17LV010-10JU 20J
AT17LV010-10PU 8P3
2-Mbit(1)
AT17LV002-10CU 8CN4
AT17LV002-10JU 20J
AT17LV002-10SU 20S2
AT17LV002-10TQU 44A
4-Mbit(1) AT17LV040-10TQU 44A
19
2321I–CNFG–2/08
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23. Packaging Information
23.1 8CN4 – LAP
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8CN4DMH D
8CN4, 8-lead (6 x 6 x 1.04 mm Body),
Lead Pitch 1.27mm,
Leadless Array Package (LAP)
2/15/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.94 1.04 1.14
A1 0.30 0.34 0.38
b 0.45 0.50 0.55 1
D 5.89 5.99 6.09
E 5.89 5.99 6.09
e 1.27 BSC
e1 1.10 REF
L 0.95 1.00 1.05 1
L1 1.25 1.30 1.35 1
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
Pin1 Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
20
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23.2 8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
21
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23.3 8S1 – SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
3/17/05
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
Ø
Ø
E
E
1
1
N
N
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
22
2321I–CNFG–2/08
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23.4 20J – PLCC
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE DRAWING NO. REV.
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 9.779 – 10.033
D1 8.890 – 9.042 Note 2
E 9.779 – 10.033
E1 8.890 – 9.042 Note 2
D2/E2 7.366 – 8.382
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1
D2/E2
B
e
E1 E
D1
D
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B
20J
10/04/01
23
2321I–CNFG–2/08
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23.5 20S2 – SOIC
24
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23.6 44A – TQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
44A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
25
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24. Revision History
Revision Level – Release Date History
H – March 2006 Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI.
I – February 2008 Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI
devices from ordering information.
2321I–CNFG–2/08
Headquarters International
Atmel Corporation
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USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Fax: (33) 1-30-60-71-11
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Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Product Contact
Web Site
www.atmel.com
Technical Support
configurator@atmel.com
Sales Contact
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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