DC918C-G - Linear Technology

LTC2205/LTC2204

22054fc

16-Bit, 65Msps/40Msps

ADCs

The LTC

2205/LTC2204 are sampling 16-bit A/D converters

designed for digitizing high frequency, wide dynamic range

signals up to input frequencies of 700MHz. The input range

of the ADC can be optimized with the PGA front end.

The LTC2205/LTC2204 are perfect for demanding

communications applications, with AC performance that

includes 79dB SNR and 100dB spurious free dynamic range

(SFDR). Ultralow jitter of 90fsRMS allows undersampling of

high input frequencies with excellent noise performance.

Maximum DC specs include ±4LSB INL, ±1LSB DNL (no

missing codes).

A separate output power supply allows the CMOS output

swing to range from 0.5V to 3.6V.

The ENC+ and ENC– inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An optional clock duty cycle stabilizer allows

high performance at full speed with a wide range of clock

duty cycles.

n Telecommunications

n Receivers

n Cellular Base Stations

n Spectrum Analysis

n Imaging Systems

n ATE

n Sample Rate: 65Msps/40Msps

n 79dB SNR and 100dB SFDR (2.25VP-P Range)

n SFDR >92dB at 140MHz (1.5VP-P Input Range)

n PGA Front End (2.25VP-P or 1.5VP-P Input Range)

n 700MHz Full Power Bandwidth S/H

n Optional Internal Dither

n Optional Data Output Randomizer

n Single 3.3V Supply

n Power Dissipation: 610mW/480mW

n Optional Clock Duty Cycle Stabilizer

n Out-of-Range Indicator

n Pin Compatible Family

105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)

80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)

65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)

40Msps: LTC2204 (16-Bit)

n 48-Pin (7mm × 7mm) QFN Package

–

S/H

AMP

CORRECTION

LOGIC AND

SHIFT REGISTER

OUTPUT

DRIVERS

16-BIT

PIPELINED

ADC CORE

INTERNAL ADC

REFERENCE

GENERATOR

1.25V

COMMON MODE

BIAS VOLTAGE

CLOCK/DUTY

CYCLE

CONTROL

D15

•

ENC PGA SHDN DITH MODE OE RANDENC

VCM

ANALOG

INPUT

22076 TA01

0.5V TO 3.6V

3.3V

SENSE

OGND

OVDD

2.2μF 0.1μF

0.1μF 0.1μF 0.1μF

VDD

GND

ADC CONTROL INPUTS

AIN+

AIN–

CLKOUT

LTC2205: 64K Point FFT,

fIN = 5.1MHz, –1dBFS,

PGA = 0, DITH = 0

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 TA01b

510 20 30

AMPLITUDE (dBFS)

FEATURES

TYPICAL APPLICATION

DESCRIPTION

APPLICATIONS

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

LTC2205/LTC2204

22054fc

PIN CONFIGURATION

CONVERTER CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ................................... –0.3V to 4V

Digital Output Ground Voltage (OGND) ........ –0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)

Digital Input Voltage .................... –0.3V to (VDD + 0.3V)

Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)

Power Dissipation .............................................2000mW

Operating Temperature Range

LTC2205C/LTC2204C ............................... 0°C to 70°C

LTC2205I/LTC2204I ..............................–40°C to 85°C

Storage Temperature Range ..................–65°C to 150°C

Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V

OVDD = VDD (Notes 1 and 2)

The

l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

TOP VIEW

UK PACKAGE

48-LEAD (7mm s 7mm) PLASTIC QFN

SENSE 1

VCM 2

VDD 3

VDD 4

GND 5

AIN+ 6

AIN–7

GND 8

ENC+ 9

ENC– 10

GND 11

VDD 12

36 OVDD

35 D11

34 D10

33 D9

32 D8

31 OGND

30 CLKOUT+

29 CLKOUT–

28 D7

27 D6

26 D5

25 OVDD

48 GND

47 PGA

46 RAND

45 MODE

44 OE

43 OF

42 D15

41 D14

40 D13

39 D12

38 OGND

37 OVDD

VDD 13

VDD 14

GND 15

SHDN 16

DITH 17

D0 18

D1 19

D2 20

D3 21

D4 22

OGND 23

OVDD 24

EXPOSED PAD IS GND (PIN 49) MUST BE SOLDERED TO PCB BOARD

TJMAX = 150°C, θJA = 29°C/W

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2205CUK#PBF LTC2205CUK#TRPBF LTC2205UK 48-Lead (7mm × 7mm) Plastic DFN 0°C to 70°C

LTC2204CUK#PBF LTC2204CUK#TRPBF LTC2204UK 48-Lead (7mm × 7mm) Plastic DFN 0°C to 70°C

LTC2205IUK#PBF LTC2205IUK#TRPBF LTC2205UK 48-Lead (7mm × 7mm) Plastic DFN –40°C to 85°C

LTC2204IUK#PBF LTC2204IUK#TRPBF LTC2204UK 48-Lead (7mm × 7mm) Plastic DFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2205CUK LTC2205CUK#TR LTC2205UK 48-Lead (7mm × 7mm) Plastic DFN 0°C to 70°C

LTC2204CUK LTC2204CUK#TR LTC2204UK 48-Lead (7mm × 7mm) Plastic DFN 0°C to 70°C

LTC2205IUK LTC2205IUK#TR LTC2205UK 48-Lead (7mm × 7mm) Plastic DFN –40°C to 85°C

LTC2204IUK LTC2204IUK#TR LTC2204UK 48-Lead (7mm × 7mm) Plastic DFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) l16 Bits

Integral Linearity Error Differential Analog Input (Note 5) l±0.7 ±4.5 LSB

Integral Linearity Error Differential Analog Input (Note 5), TA = 25°C ±0.7 ±4 LSB

Differential Linearity Error Differential Analog Input l±0.3 ±1 LSB

Offset Error (Note 6) l±1 ±8.5 mV

Offset Drift ±10 μV/°C

Gain Error External Reference l±0.2 ±1.9 %FS

Full-Scale Drift Internal Reference

External Reference

±30

±10

ppm/°C

Transition Noise 2.5 LSBRMS

LTC2205/LTC2204

22054fc

ANALOG INPUT

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise

speciﬁ cations are at TA = 25°C. (Note 4)

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN

LTC2204

TYP MAX MIN

LTC2205

TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

79.1

76.5

79.0

76.4

dBFS

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

l77.6

79.0

76.5

77.5

77.9

78.9

76.4

dBFS

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

l74.6

78.5

76.3 74.6

78.4

76.2

dBFS

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

77.4

75.5

77.3

75.4

dBFS

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

76.5

74.9

76.5

74.8

dBFS

SFDR Spurious Free

Dynamic Range

2nd or 3rd

Harmonic

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

100

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (2.25V Range, PGA = 0

15MHz Input (1.5V Range, PGA = 1)

l87

100

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

l84.5

84.5

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN–)3.135V ≤ VDD ≤ 3.465V l1.5 to 2.25 VP-P

VIN, CM Analog Input Common Mode Differential Input (Note 7) l1 1.25 1.5 V

IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD l–1 1 μA

ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD l–3 3 μA

IMODE MODE Pin Pull-Down Current to GND 10 μA

CIN Analog Input Capacitance Sample Mode ENC+ < ENC–

Hold Mode ENC+ > ENC–6.5

1.8

tAP Sample-and-Hold

Aperture Delay Time

0.7 ns

tJITTER Sample-and-Hold

Aperture Delay Time Jitter

90 fsRMS

CMRR Analog Input

Common Mode Rejection Ratio

1V < (AIN+ = AIN–) <1.5V 60 dB

BW-3dB Full Power Bandwidth 700 MHz

LTC2205/LTC2204

22054fc

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN

LTC2204

TYP MAX MIN

LTC2205

TYP MAX UNITS

SFDR Spurious Free

Dynamic Range

4th Harmonic

or Higher

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

105

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

l90 100

100

90 100

100

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1) l88.5

100

100 88.5

100

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

S/(N+D) Signal-to-Noise

Plus Distortion Ratio

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

79.1

76.5

79.0

76.4

dBFS

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

l77.5

77.7

79.0

76.5

77.4

77.6

78.9

76.4

dBFS

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

l73.8

74.2

78.5

76.2

73.8

74.2

78.4

76.2

dBFS

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

77.3

75.4

77.0

75.3

dBFS

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

76.5

75.4

76.0

75.2

dBFS

SFDR Spurious Free

Dynamic Range

at –25dBFS

Dither “OFF”

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

105

dBFS

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

105

dBFS

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

105

dBFS

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

100

dBFS

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

100

dBFS

SFDR Spurious Free

Dynamic Range

at –25dBFS

Dither “ON”

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

115

dBFS

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

l98 115

115

98 115

115

dBFS

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

115

dBFS

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

115

dBFS

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

105

dBFS

LTC2205/LTC2204

22054fc

COMMON MODE BIAS CHARACTERISTICS

The l denotes the speciﬁ cations which apply over

the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

POWER REQUIREMENTS

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the speciﬁ cations which apply over the

full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN

LTC2204

TYP MAX MIN

LTC2205

TYP MAX UNITS

VDD Analog Supply Voltage 3.135 3.3 3.465 3.315 3.3 3.465 V

PSHDN Shutdown Power SHDN = VDD 0.2 0.2 mW

OVDD Output Supply Voltage l0.5V 3.6 0.5V 3.3 3.6 V

IVDD Analog Supply Current l145 200 185 235 mA

PDIS Power Dissipation l480 660 610 776 mW

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 1.15 1.25 1.35 V

VCM Output Tempco IOUT = 0 ±40 ppm/°C

VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 1 mV/ V

VCM Output Resistance 1mA ≤ | IOUT | ≤ 1mA 1 Ω

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ENCODE INPUTS (ENC+, ENC–)

VID Differential Input Voltage (Note 7) l0.2 V

VICM Common Mode Input Voltage Internally Set

Externally Set (Note 7) 1.2

1.6

3.0

RIN Input Resistance (See Figure 2) 6 kΩ

CIN Input Capacitance (Note 7) 3 pF

LOGIC INPUTS (DITH, PGA, SHDN, RAND)

VIH High Level Input Voltage VDD = 3.3V l2V

VIL Low Level Input Voltage VDD = 3.3V l0.8 V

IIN Digital Input Current VIN = 0V to VDD l±10 μA

CIN Digital Input Capacitance (Note 7) 1.5 pF

LOGIC OUTPUTS

OVDD = 3.3V

VOH High Level Output Voltage VDD = 3.3V IO = –10μA

O = –200μA l3.1

3.299

3.29

VOL Low Level Output Voltage VDD = 3.3V IO = –160μA

O = –1.6μA l

0.01

0.10 0.4

ISOURCE Output Source Current VOUT = 0V –50 mA

ISINK Output Sink Current VOUT = 3.3V 50 mA

OVDD = 2.5V

VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V

VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

OVDD = 1.8V

VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V

VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

LTC2205/LTC2204

22054fc

TIMING DIAGRAM

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND, with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 3.3V, fSAMPLE = 65MHz (LTC2205), 40MHz (LTC2204)

differential ENC+/ENC– = 2VP-P sine wave with 1.6V common mode,

input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise

speciﬁ ed.

Note 5: Integral nonlinearity is deﬁ ned as the deviation of a code from

a “best ﬁ t straight line” to the transfer curve. The deviation is measured

from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –1/2LSB when the

output code ﬂ ickers between 0000 0000 0000 0000 and 1111 1111 1111

1111 in 2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.

Note 8: Recommended operating conditions.

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN

LTC2204

TYP MAX MIN

LTC2205

TYP MAX UNITS

fSSampling Frequency l1 40 1 65 MHz

tLENC Low Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

10.4

2.7

12.5

500

6.40

2.70

7.69

500

tHENC High Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

l10.4

2.7

12.5

500

6.40

2.70

7.69

500

tAP Sample-and-Hold

Aperture Delay

0.7 0.7 ns

tDENC to DATA Delay (Note 7) l1.3 2.7 4.0 1.3 2.7 4.0 ns

tCENC to CLKOUT Delay (Note 7) l1.3 2.7 4.0 1.3 2.7 4.0 ns

tSKEW DATA to CLKOUT Skew (tD – tC) (Note 7) l–0.6 0 0.6 –0.6 0 0.6 ns

tOE DATA Access Time

Bus Relinquish Time

CL = 5pf (Note 7)

(Note 7)

Pipeline

Latency

7 7 Cycles

TIMING CHARACTERISTICS

N – 7 N – 6 N – 5 N – 4 N – 3

ANALOG

INPUT

ENC–

ENC+

CLKOUT–

CLKOUT+

D0-D15, OF

22054 TD01

tAP N + 1

N + 2

N + 4

N + 3

LTC2205/LTC2204

22054fc

TYPICAL PERFORMANCE CHARACTERISTICS

CODE

INL (LSB)

1.0

65536

22054 G01

–1.0

–2.0 16384 32768 49152

8192 24576 40960 57344

2.0

–0.5

0.5

–1.5

1.5

CODE

DNL (LSB)

0.50

65536

22054 G02

–0.50

–1.00 16384 32768 49152

8192 24576 40960 57344

1.00

–0.25

0.25

–0.75

0.75

CODE FROM MID-SCALE

–10

COUNT

100,000

120,000

22054 G03

60,000

0–8 –6 –2–4 02 6

160,000

140,000

80,000

40,000

20,000

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G04

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G06

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G07

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G08

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G09

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G05

510 20 30

AMPLITUDE (dBFS)

LTC2205: INL (Integral Non-

Linearity) vs Code

LTC2205: DNL (Differential Non-

Linearity) vs Code

LTC2205: Grounded Input

Histogram

LTC2205: 64K Point FFT,

fIN = 5.1MHz, –1dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 5.1MHz, –1dBFS,

PGA = 1, DITH = 0

LTC2205: 64K Point FFT,

fIN = 5.1MHz, –25dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

fIN = 5.1MHz, –25dBFS,

PGA = 0, DITH = 1

LTC2205: 64K Point FFT,

fIN = 5.1MHz, –40dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

fIN = 5.1MHz, –40dBFS,

PGA = 0, DITH = 1

LTC2205/LTC2204

22054fc

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G10

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G11

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G12

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G13

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G14

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G15

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G16

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G17

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G18

510 20 30

AMPLITUDE (dBFS)

LTC2205: 64K Point FFT,

65Msps, fIN = 15.1MHz, –1dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 15.1MHz, –1dBFS,

PGA = 1, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 15.1MHz, –25dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 15.1MHz, –25dBFS,

PGA = 0, DITH = 1

LTC2205: 64K Point FFT,

65Msps, fIN = 15.1MHz, –40dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 15.1MHz, –40dBFS,

PGA = 0, DITH = 1

LTC2205: 64K Point FFT,

65Msps, fIN = 70.1MHz, –1dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 70.1MHz, –1dBFS,

PGA = 1, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 70.1MHz, –25dBFS,

PGA = 0, DITH = 0

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2205/LTC2204

22054fc

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G19

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G20

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G21

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G22

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G23

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G24

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G25

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G26

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G27

510 20 30

AMPLITUDE (dBFS)

LTC2205: 64K Point FFT,

65Msps, fIN = 70.1MHz, –25dBFS,

PGA = 0, DITH = 1

LTC2205: 64K Point FFT,

65Msps, fIN = 70.1MHz, –40dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 70.1MHz, –40dBFS,

PGA = 0, DITH = 1

LTC2205: 64K Point FFT,

65Msps, fIN = 140.1MHz, –1dBFS,

PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

fIN = 140.1MHz, –1dBFS,

PGA = 1, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 140.1MHz,

–25dBFS, PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 140.1MHz,

–25dBFS, PGA = 0, DITH = 1

LTC2205: 64K Point FFT,

65Msps, fIN = 140.1MHz,

–40dBFS, PGA = 0, DITH = 0

LTC2205: 64K Point FFT,

65Msps, fIN = 140.1MHz,

–40dBFS, PGA = 0, DITH = 1

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2205/LTC2204

22054fc

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G28

510 20 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15 25

22054 G29

510 20 30

AMPLITUDE (dBFS)

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G30

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G31

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G32

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G33

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G34

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G35

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G36

100

–70 –50 –20 –10 0

LTC2205: 64K Point FFT,

fIN1 = 14.9MHz, –7dBFS,

fIN2 = 20.1MHz, –7dBFS, PGA = 0

LTC2205: 64K Point FFT,

fIN1 = 64.1MHz, –7dBFS,

fIN2 = 20.1MHz, –7dBFS, PGA = 0

LTC2205: SFDR vs Input Level,

fIN = 5.1MHz,

DITH = 0, RAND = 1, PGA = 0

LTC2205: SFDR vs Input Level,

fIN = 5.1MHz,

DITH = 1, RAND = 1, PGA = 0

LTC2205: SFDR vs Input Level,

fIN = 15.1MHz,

DITH = 0, RAND = 1, PGA = 0

LTC2205: SFDR vs Input Level,

fIN = 15.1MHz,

DITH = 1, RAND = 1, PGA = 0

LTC2205: SFDR vs Input Level,

fIN = 70.1MHz,

DITH = 0, RAND = 1, PGA = 0

LTC2205: SFDR vs Input Level,

fIN = 70.1MHz,

DITH = 1, RAND = 1, PGA = 0

LTC2205: SFDR vs Input Level,

fIN = 140.1MHz,

DITH = 0, RAND = 1, PGA = 0

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2205/LTC2204

22054fc

TEMPERATURE (°C)

GAIN DRIFT (mV)

22054 G44

–60 –40

–1.2

–1.0

–0.8

–0.6

–0.4

–0.2

0.8

0.6

0.4

0.2

–20 0 20 40 60 10080

TEMPERATURE (°C)

DRIFT (mV)

22054 G43

–60 –40

–7

–4

–3

–6

–5

–2

–1

–20 0 20 40 60 10080

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G37

100

–70 –50 –20 –10 0

INPUT FREQUENCY (MHz)

SFDR (dBc)

100

200

22054 G38

70 50 100 150 250

110

PGA = 0

PGA = 1

INPUT FREQUENCY (MHz)

SNR (dBFS)

100 200

22054 G39

300 400

PGA = 0

PGA = 1

SAMPLE RATE (Msps)

SFDR (dBc) AND SNR (dBFS)

100

22054 G40

70 20 40 50 110

110

10 30 90 100

SNR

SFDR

SUPPLY VOLTAGE

SFDR (dBc) AND SNR (dBFS)

22054 G41

2.4

100

110

2.6 2.8 3.0 3.2 3.4 3.6

SNR

SFDR

SAMPLE RATE (Msps)

IVDD (mA)

180

190

200

110

22054 G42

160

130 20 3010 40 6050 8070 10090

210

170

150

140

VDD = 3.3V

VDD = 3.47V

VDD = 3.13V

TEMPERATURE (°C)

VCM (mV)

22054 G45

–40

–4

–3

–2

–1

–200 20406080

LTC2205: SFDR vs Input Level,

fIN = 140.1MHz,

DITH = 1, RAND = 1, PGA = 0

LTC2205: SFDR vs Input

Frequency, DITH = 0, RAND = 0

LTC2205: SNR vs Input Frequency,

DITH = 0, RAND = 0

LTC2205: SFDR and SNR vs

Sample Rate, fIN = 5.1MHz,

–1dBFS, PGA = 0

LTC2205: SFDR and SNR vs

Supply Voltage, fIN = 5.1MHz,

65Msps, PGA = 0

LTC2205: IVDD vs Sample Rate,

fIN = 5.1MHz, –1dBFS

LTC2205: VCM Drift vs Temperature

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2205: Gain Error Drift with

Internal Reference vs Temperature

LTC2205: Gain Drift with External

Reference vs Temperature

LTC2205/LTC2204

22054fc

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G47

510 20

AMPLITUDE (dBFS)

TEMPERATURE (°C)

–40

SFDR (dBc) AND (dBFS)

100

110

120

–20 02040

22054 G46

60 80

SNR

SFDR

INPUT COMMON MODE VOLTAGE (V)

SNR (dBFS) AND SFDR (dBc)

29701 G46b

0.50

100

110

0.75 1.00 1.25 1.50 1.75 2.00

SNR

SFDR

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G48

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G49

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G50

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G51

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G52

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G53

510 20

AMPLITUDE (dBFS)

LTC2204: 64K Point FFT,

40Msps, fIN = 5.1MHz, –1dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 5.1MHz, –1dBFS,

PGA = 1, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 5.1MHz, –25dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 5.1MHz, –25dBFS,

PGA = 0, DITH = 1

LTC2204: 64K Point FFT,

40Msps, fIN = 5.1MHz, –40dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 5.1MHz, –40dBFS,

PGA = 0, DITH = 1

LTC2204: 64K Point FFT,

40Msps, fIN = 15.1MHz, –1dBFS,

PGA = 0, DITH = 0

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2205: SFDR and SNR vs

Temperature, fIN = 5.1MHz

LTC2205: SFDR and SNR vs

Input Common Mode Voltage,

fIN = 5.1MHz

LTC2205/LTC2204

22054fc

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G56

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G57

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G58

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G59

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G60

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G61

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G62

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G54

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G55

510 20

AMPLITUDE (dBFS)

LTC2204: 64K Point FFT,

40Msps, fIN = 15.1MHz, –1dBFS,

PGA = 1, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 15.1MHz, –25dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 15.1MHz, –25dBFS,

PGA = 0, DITH = 1

LTC2204: 64K Point FFT,

40Msps, fIN = 15.1MHz, –40dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 15.1MHz, –40dBFS,

PGA = 0, DITH = 1

LTC2204: 64K Point FFT,

40Msps, fIN = 70.1MHz,

–1dBFS, PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 70.1MHz,

–1dBFS, PGA = 1, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 70.1MHz, –25dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 70.1MHz, –25dBFS,

PGA = 0, DITH = 1

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2205/LTC2204

22054fc

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G65

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G66

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G67

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G68

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G69

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G70

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G71

510 20

AMPLITUDE (dBFS)

LTC2204: 64K Point FFT,

40Msps, fIN = 140.1MHz, –1dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 140.1MHz, –1dBFS,

PGA = 1, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 140.1MHz,

–25dBFS, PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 140.1MHz,

–25dBFS, PGA = 0, DITH = 1

LTC2204: 64K Point FFT,

40Msps, fIN = 140.1MHz,

–25dBFS, PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 140.1MHz,

–40dBFS, PGA = 0, DITH = 1

LTC2204: 64K Point FFT,fIN1 =

14.9MHz, –7dBFS,fIN2 = 20.1MHz,

–7dBFS, PGA = 0, DITH = 0

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G63

510 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G64

510 20

AMPLITUDE (dBFS)

LTC2204: 64K Point FFT,

40Msps, fIN = 70.1MHz, –40dBFS,

PGA = 0, DITH = 0

LTC2204: 64K Point FFT,

40Msps, fIN = 70.1MHz, –40dBFS,

PGA = 0, DITH = 1

LTC2205/LTC2204

22054fc

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

–140 15

22054 G72

510 20

AMPLITUDE (dBFS)

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G73

100

–70 –50 –20 –10 0

LTC2204: 64K Point FFT, fIN1 =

65.1MHz, –7dBFS, fIN2 = 70.1MHz,

–7dBFS, PGA = 0, DITH = 0

LTC2204: SFDR vs Input Level,

fIN = 5.1MHz, DITH = 0, RAND = 1

LTC2204: SFDR vs Input Level,

fIN = 5.1MHz, DITH = 1, RAND = 1

LTC2204: SFDR vs Input Level,

fIN = 5.1MHz, DITH = 0, RAND = 1

LTC2204: SFDR vs Input Level,

fIN = 15.1MHz,

DITH = 1, RAND = 1

LTC2204: SFDR vs Input Level,

fIN = 70.1MHz,

DITH = 0, RAND = 1

LTC2204: SFDR vs Input Level,

fIN = 70.1MHz,

DITH = 1, RAND = 1

LTC2204: SFDR vs Input Level,

fIN = 140.1MHz,

DITH = 0, RAND = 1

LTC2204: SFDR vs Input Level,

fIN = 140.1MHz,

DITH = 1, RAND = 1

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G74

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G75

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G76

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G77

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G78

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G79

100

–70 –50 –20 –10 0

INPUT LEVEL (dBFS)

–80

SFDR (dBFS AND dBc)

110

120

130

–60 –40 –30

22054 G80

100

–70 –50 –20 –10 0

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2205/LTC2204

22054fc

LTC2204: SFDR and SNR vs Sample

Rate, fIN = 5.1MHz, –1dBFS,

PGA = 0, DITH = 0, RAND = 0

LTC2204: SFDR and SNR vs

Supply Voltage, DITH = 0,

RAND = 0

LTC2204: IVDD vs Sample Rate,

fIN = 5.1MHz, dBFS, DITH = 0,

RAND = 0

LTC2204: SNR and SFDR vs

Input Common Mode Voltage,

DITH = 0, RAND = 0

SAMPLE RATE (Msps)

SFDR (dBc) AND SNR (dBFS)

100

110

10 20 30 40

22054 G83

50 60 70 80 90

SNR

SFDR

SUPPLY VOLTAGE (V)

SFDR (dBC) AND SNR (dBFS)

22054 G84

2.4

100

110

2.6 2.8 3.0 3.2 3.4 3.6

SNR

SFDR

SAMPLE RATE (Msps)

120

IVDD (mA)

130

150

160

170

20 40 50 90

22054 G85

140

10 30 60 70 80

180

VDD = 3.3V

VDD = 3.47V

VDD = 3.13V

INPUT COMMON MODE VOLTAGE (V)

SNR (dBFS) AND SFDR (dBc)

22054 G86

0.50

100

110

0.75 1.00 1.25 1.50 1.75 2.00

SNR

SFDR

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2204: SFDR vs Input

Frequency, DITH = 0, RAND = 0

LTC2204: SNR vs Input Frequency,

DITH = 0, RAND = 0

INPUT FREQUENCY (MHz)

SFDR (dBc)

100

110

200

22054 G81

60 50 100 150 250

PGA = 0

PGA = 1

INPUT FREQUENCY (MHz)

SNR (dBFS)

100 200

22054 G82

300 400

PGA = 0

PGA = 1

TIME AFTER WAKE-UP OR CLOCK START (μs)

FULL-SCALE ERROR (%)

0.2

0.6

1.0

400

22054 G87

–0.2

–0.6

0.4

0.8

–0.4

–0.8

–1.0 10050 200150 300 350 450

250 500

TIME FROM WAKE-UP OR CLOCK START (μs)

FULL-SCALE ERROR (%)

800

22054 G88

–1

–3

–2

–4

–5 200100 400300 600 700 900

500 1000

Mid-Scale Settling After Wake

Up from Shutdown or Starting

Encode Clock

Full-Scale Settling After Wake

Up from Shutdown or Starting

Encode Clock

LTC2205/LTC2204

22054fc

OVDD (Pins 24, 25, 36, 37): Positive Supply for the

Output Drivers. Bypass to ground with 0.1μF ceramic

chip capacitors.

CLKOUT– (Pin 29): Data Valid Output. CLKOUT– will toggle

at the sample rate. Latch the data on the falling edge of

CLKOUT–.

CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+

will toggle at the sample rate. Latch the data on the rising

edge of CLKOUT+.

OF (Pin 43): Over/Under Flow Digital Output. OF is high

when an over or under ﬂ ow has occurred.

OE (Pin 44): Output Enable Pin. Low enables the digital

output drivers. High puts digital outputs in Hi-Z state.

MODE (Pin 45): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and disables the clock duty cycle

stabilizer. Connecting MODE to 1/3VDD selects offset binary

output format and enables the clock duty cycle stabilizer.

Connecting MODE to 2/3VDD selects 2’s complement

output format and enables the clock duty cycle stabilizer.

Connecting MODE to VDD selects 2’s complement output

format and disables the clock duty cycle stabilizer.

RAND (Pin 46): Digital Output Randomization Selection

Pin. RAND low results in normal operation. RAND high

selects D1-D15 to be EXCLUSIVE-ORed with D0 (the

LSB). The output can be decoded by again applying an

XOR operation between the LSB and all other bits. This

mode of operation reduces the effects of digital output

interference.

PGA (Pin 47): Programmable Gain Ampliﬁ er Control Pin.

Low selects a front-end gain of 1, input range of 2.25VP-P.

High selects a front-end gain of 1.5, input range of 1.5VP-P.

GND (Exposed Pad, Pin 49): ADC Power Ground. The

exposed pad on the bottom of the package must be

soldered to ground.

SENSE (Pin 1): Reference Mode Select and External

Reference Input. Tie SENSE to VDD to select the internal

2.5V bandgap reference. An external reference of 2.5V or

1.25V may be used; both reference values will set a full

scale ADC range of 2.25V (PGA = 0).

VCM (Pin 2): 1.25V Output. Optimum voltage for input com-

mon mode. Must be bypassed to ground with a minimum

of 2.2μF. Ceramic chip capacitors are recommended.

VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.

Bypass to GND with 0.1μF ceramic chip capacitors.

GND (Pins 5, 8, 11, 15, 48, 49): ADC Power Ground.

AIN+ (Pin 6): Positive Differential Analog Input.

AIN– (Pin 7): Negative Differential Analog Input.

ENC+ (Pin 9): Positive Differential Encode Input. The

sampled analog input is held on the rising edge of ENC+.

Internally biased to 1.6V through a 6.2kΩ resistor. Output

data can be latched on the rising edge of ENC+.

ENC– (Pin 10): Negative Differential Encode Input. The

sampled analog input is held on the falling edge of ENC–.

Internally biased to 1.6V through a 6.2kΩ resistor. By-

pass to ground with a 0.1μF capacitor for a single-ended

Encode signal.

SHDN (Pin 16): Power Shutdown Pin. SHDN = low results

in normal operation. SHDN = high results in powered down

analog circuitry and the digital outputs placed in a high

impedance state.

DITH (Pin 17): Internal Dither Enable Pin. DITH = low

disables internal dither. DITH = high enables internal

dither. Refer to Internal Dither section of this data sheet

for details on dither operation.

D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital

Outputs. D15 is the MSB.

OGND (Pins 23, 31 and 38): Output Driver Ground.

PIN FUNCTIONS

LTC2205/LTC2204

22054fc

ADC CLOCKS

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

DITHER

SIGNAL

GENERATOR

FIRST PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

ENC+ENC–

CORRECTION LOGIC

AND

SHIFT REGISTER

DITHM0DE

OGND

CLKOUT+

CLKOUT–

D15

D14

OVDD

22054 F01

INPUT

S/H

AIN–

AIN+

THIRD PIPELINED

ADC STAGE

OUTPUT

DRIVERS

CONTROL

LOGIC

PGA RAND OESHDN

•

VDD

GND

PGA

SENSE

VCM BUFFER

ADC

REFERENCE

VOLTAGE

REFERENCE

RANGE

SELECT

Figure 1. Functional Block Diagram

BLOCK DIAGRAM

LTC2205/LTC2204

22054fc

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer function

can create distortion products at the sum and difference

frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 3rd order IMD terms include (2fa + fb),

(fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is

deﬁ ned as the ratio of the RMS value of either input tone

to the RMS value of the largest 3rd order IMD product.

Spurious Free Dynamic Range (SFDR)

The ratio of the RMS input signal amplitude to the RMS

value of the peak spurious spectral component expressed

in dBc. SFDR may also be calculated relative to full scale

and expressed in dBFS.

Full Power Bandwidth

The Full Power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is reduced

by 3dB for a full scale input signal.

Aperture Delay Time

The time from when a rising ENC+ equals the ENC– voltage

to the instant that the input signal is held by the sample-

and-hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion

to conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N+D)] is the

ratio between the RMS amplitude of the fundamental

input frequency and the RMS amplitude of all other

frequency components at the ADC output. The output is

band limited to frequencies above DC to below half the

sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise (SNR) is the ratio between the RMS

amplitude of the fundamental input frequency and the RMS

amplitude of all other frequency components, except the

ﬁ rst ﬁ ve harmonics.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

THD = –20Log(√(V22 + V32 + V42 + ... VN2)/V12)

where V1 is the RMS amplitude of the fundamental

frequency and V2 through VN are the amplitudes of the

second through nth harmonics.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

OPERATION

LTC2205/LTC2204

22054fc

CONVERTER OPERATION

The LTC2205/LTC2204 are CMOS pipelined multistep

converters with a front-end PGA. As shown in Figure 1, the

converter has ﬁ ve pipelined ADC stages; a sampled analog

input will result in a digitized value seven cycles later (see the

Timing Diagram section). The analog input is differential for

improved common mode noise immunity and to maximize

the input range. Additionally, the differential input drive

will reduce even order harmonics of the sample and hold

circuit. The encode input is also differential for improved

common mode noise immunity.

The LTC2205/LTC2204 have two phases of operation,

determined by the state of the differential ENC+/ENC– input

pins. For brevity, the text will refer to ENC+ greater

than ENC– as ENC high and ENC+ less than ENC– as

ENC low.

Each pipelined stage shown in Figure 1 contains an

ADC, a reconstruction DAC and a residue ampliﬁ er. In

operation, the ADC quantizes the input to the stage, and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is ampliﬁ ed and

output by the residue ampliﬁ er. Successive stages operate

out of phase so that when odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the voltage on the

sample capacitors is held. While ENC is high, the held

input voltage is buffered by the S/H ampliﬁ er which drives

the ﬁ rst pipelined ADC stage. The ﬁ rst stage acquires

the output of the S/H ampliﬁ er during the high phase of

ENC. When ENC goes back low, the ﬁ rst stage produces

its residue which is acquired by the second stage. At

the same time, the input S/H goes back to acquiring the

analog input. When ENC goes high, the second stage

produces its residue which is acquired by the third stage.

An identical process is repeated for the third and fourth

stages, resulting in a fourth stage residue that is sent to

the ﬁ fth stage for ﬁ nal evaluation.

Each ADC stage following the ﬁ rst has additional range to

accommodate ﬂ ash and ampliﬁ er offset errors. Results

from all of the ADC stages are digitally delayed such that

the results can be properly combined in the correction

logic before being sent to the output buffer.

Figure 2. Equivalent Input Circuit

CSAMPLE

4.9pF

VDD

LTC2005/LTC2004

AIN+

22054 F02

CSAMPLE

4.9pF

VDD

AIN–

ENC–

ENC+

1.6V

CPARASITIC

1.8pF

RPARASITIC

3Ω

RON

20Ω

RON

20Ω

RPARASITIC

3Ω

CPARASITIC

1.8pF

APPLICATIONS INFORMATION

LTC2205/LTC2204

22054fc

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2205/

LTC2204 CMOS differential sample and hold. The

differential analog inputs are sampled directly onto

sampling capacitors (CSAMPLE) through NMOS transistors.

The capacitors shown attached to each input (CPARASITIC)

are the summation of all other capacitance associated

with each input.

During the sample phase when ENC is low, the NMOS

transistors connect the analog inputs to the sampling

capacitors which charge to, and track the differential

input voltage. When ENC transitions from low to high, the

sampled input voltage is held on the sampling capacitors.

During the hold phase when ENC is high, the sampling

capacitors are disconnected from the input and the held

voltage is passed to the ADC core for processing. As ENC

transitions for high to low, the inputs are reconnected to

the sampling capacitors to acquire a new sample. Since

the sampling capacitors still hold the previous sample,

a charging glitch proportional to the change in voltage

between samples will be seen at this time. If the change

between the last sample and the new sample is small,

the charging glitch seen at the input will be small. If the

input change is large, such as the change seen with input

frequencies near Nyquist, then a larger charging glitch

will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential

drive to achieve speciﬁ ed performance. Each input should

swing ±0.5625V for the 2.25V range (PGA = 0) or ± 0.375V

for the 1.5V range (PGA = 1), around a common mode

voltage of 1.25V. The VCM output pin (Pin 2) is designed

to provide the common mode bias level. VCM can be tied

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The VCM pin must be bypassed to ground

close to the ADC with 2.2μF or greater.

Input Drive Impedance

As with all high performance, high speed ADCs the

dynamic performance of the LTC2205/LTC2204 can be

inﬂ uenced by the input drive circuitry, particularly the

second and third harmonics. Source impedance and

input reactance can inﬂ uence SFDR. At the falling edge

of ENC the sample-and-hold circuit will connect the 4.9pF

sampling capacitor to the input pin and start the sampling

period. The sampling period ends when ENC rises, holding

the sampled input on the sampling capacitor. Ideally,

the input circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

1/(2FENCODE); however, this is not always possible and the

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

INPUT DRIVE CIRCUITS

Input Filtering

A ﬁ rst order RC lowpass ﬁ lter at the input of the ADC can

serve two functions: limit the noise from input circuitry and

provide isolation from ADC S/H switching. The LTC2205/

LTC2204 have a very broadband S/H circuit, DC to 700MHz;

it can be used in a wide range of applications; therefore, it is

not possible to provide a single recommended RC ﬁ lter.

Figures 3, 4a and 4b show three examples of input RC

ﬁ ltering at three ranges of input frequencies. In general

it is desirable to make the capacitors as large as can be

tolerated—this will help suppress random noise as well

as noise coupled from the digital circuitry. The LTC2205/

LTC2204 do not require any input ﬁ lter to achieve data sheet

speciﬁ cations; however, no ﬁ ltering will put more stringent

noise requirements on the input drive circuitry.

APPLICATIONS INFORMATION

LTC2205/LTC2204

22054fc

Transformer Coupled Circuits

Figure 3 shows the LTC2205/LTC2204 being driven by

an RF transformer with a center-tapped secondary. The

secondary center tap is DC biased with VCM, setting the

ADC input signal at its optimum DC level. Figure 3 shows

a 1:1 turns ratio transformer. Other turns ratios can be

used; however, as the turns ratio increases so does the

impedance seen by the ADC. Source impedance greater

than 50Ω can reduce the input bandwidth and increase

high frequency distortion. A disadvantage of using a

transformer is the loss of low frequency response. Most

small RF transformers have poor performance at frequen-

cies below 1MHz.

0.1μF

AIN+

AIN–

4.7pF

2.2μF

4.7pF

VCM

LTC2205/

LTC2204

ANALOG

INPUT

0.1μF

1:1

T1 = MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

22054 F04a

5Ω10Ω

25Ω

25Ω10Ω5Ω

Figure 4a. Using a Transmission Line Balun Transformer.

Recommended for Input Frequencies from 70MHz to 250MHz

0.1μF

AIN+

AIN–

2.2μF

2.2pF

VCM

LTC2205/

LTC2204

ANALOG

INPUT

0.1μF

1:1

T1 = MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

22054 F04b

5Ω

25Ω

25Ω 5Ω

Figure 4b. Using a Transmission Line Balun Transformer.

Recommended for Input Frequencies from 250MHz to 500MHz

Center-tapped transformers provide a convenient means

of DC biasing the secondary; however, they often show

poor balance at high input frequencies, resulting in large

2nd order harmonics.

Figure 4a shows transformer coupling using a transmission

line balun transformer. This type of transformer has much

better high frequency response and balance than ﬂ ux

coupled center tap transformers. Coupling capacitors are

added at the ground and input primary terminals to allow

the secondary terminals to be biased at 1.25V. Figure

4b shows the same circuit with components suitable for

higher input frequencies.

APPLICATIONS INFORMATION

Figure 3. Single-Ended to Differential Conversion Using a Transformer.

Recommended for Input Frequencies from 5MHz to 150MHz

35Ω

5Ω

35Ω

10Ω

5Ω

0.1μF

AIN+

AIN–

8.2pF

2.2μF

8.2pF

VCM

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

22054 F03

LTC2205/

LTC2204

LTC2205/LTC2204

22054fc

Figure 5. DC Coupled Input with Differential Ampliﬁ er

––

AIN+

AIN–

2.2μF

12pF

VCM

LTC2205/

LTC2204

ANALOG

INPUT

22054 F05

AMPLIFIER = LTC6600-20,

LTC1993, ETC.

HIGH SPEED

DIFFERENTIAL

AMPLIFIER 25Ω

25Ω PGA

1.25V

SENSE

VCM BUFFER

INTERNAL

ADC

REFERENCE

RANGE

SELECT

AND GAIN

CONTROL

2.5V

BANDGAP

REFERENCE

2.2μF

TIE TO VDD TO USE

INTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 1.25V

REFERENCE

22054 F06

LTC2205/

LTC2204

Figure 6. Reference Circuit

Direct Coupled Circuits

Figure 5 demonstrates the use of a differential ampliﬁ er to

convert a single ended input signal into a differential input

signal. The advantage of this method is that it provides

low frequency input response; however, the limited gain

bandwidth of any op amp or closed-loop ampliﬁ er will

degrade the ADC SFDR at high input frequencies. Additionally,

wideband op amps or differential ampliﬁ ers tend to have

high noise. As a result, the SNR will be degraded unless the

noise bandwidth is limited prior to the ADC input.

APPLICATIONS INFORMATION

very stringent settling requirements and is not accessible

for external use.

The SENSE pin can be driven ±5% around the nominal 2.5V

or 1.25V external reference inputs. This adjustment range

can be used to trim the ADC gain error or other system

gain errors. When selecting the internal reference, the

SENSE pin should be tied to VDD as close to the converter

as possible. If the sense pin is driven externally it should

be bypassed to ground as close to the device as possible

with 1μF (or larger) ceramic capacitor.

Reference Operation

Figure 6 shows the LTC2205/LTC2204 reference circuitry

consisting of a 2.5V bandgap reference, a programmable

gain ampliﬁ er and control circuit. The LTC2205/LTC2204

have three modes of reference operation: Internal

Reference, 1.25V external reference or 2.5V external

reference. To use the internal reference, tie the SENSE pin

to VDD. To use an external reference, simply apply either

a 1.25V or 2.5V reference voltage to the SENSE input

pin. Both 1.25V and 2.5V applied to SENSE will result in

a full scale range of 2.25VP-P (PGA = 0). A 1.25V output,

VCM is provided for a common mode bias for input drive

circuitry. An external bypass capacitor is required for the

VCM output. This provides a high frequency low impedance

path to ground for internal and external circuitry. This is

also the compensation capacitor for the reference; it will

not be stable without this capacitor. The minimum value

required for stability is 2.2μF.

The internal programmable gain ampliﬁ er provides the

internal reference voltage for the ADC. This ampliﬁ er has

Figure 7. A 2.25V Range ADC with

an External 2.5V Reference

VCM

SENSE

1.25V

3.3V

2.2μF

1μF

22054 F07

LTC2205/

LTC2204

LT1461-2.5

LTC2205/LTC2204

22054fc

PGA Pin

The PGA pin selects between two gain settings for

the ADC front-end. PGA = 0 selects an input range of

2.25VP-P; PGA = 1 selects an input range of 1.5VP-P. The

2.25V input range has the best SNR; however, the distortion

will be higher for input frequencies above 100MHz. For

applications with high input frequencies, the low input

range will have improved distortion; however, the SNR

will be worse by up to approximately 2dB to 6dB. See the

typical performance curves section.

Driving the Encode Inputs

The noise performance of the LTC2205/LTC2204 can depend

on the encode signal quality as much as on the analog input.

The encode inputs are intended to be driven differentially,

primarily for noise immunity from common mode noise

sources. Each input is biased through a 6k resistor to a

1.6V bias. The bias resistors set the DC operating point

for transformer coupled drive circuits and can set the logic

threshold for single-ended drive circuits.

Any noise present on the encode signal will result in

additional aperture jitter that will be RMS summed with

the inherent ADC aperture jitter.

In applications where jitter is critical (high input

frequencies), take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude possible. If using transformer

coupling, use a higher turns ratio to increase the

amplitude.

3. If the ADC is clocked with a ﬁ xed frequency sinusoidal

signal, ﬁ lter the encode signal to reduce wideband

noise.

4. Balance the capacitance and series resistance at both

encode inputs such that any coupled noise will appear

at both inputs as common mode noise.

The encode inputs have a common mode range of 1.2V

to 3V. Each input may be driven from ground to VDD for

single-ended drive.

Figure 8. Transformer Driven Encode

VDD

LTC2205/

LTC2204

22054 F08

VDD

ENC–

ENC+

1.6V

ETC1-1T

0.1μF

33pF

ENCODE

INPUT

100Ω

50Ω

TO INTERNAL

ADC CLOCK

DRIVERS

0.1μF

50Ω

••

APPLICATIONS INFORMATION

LTC2205/LTC2204

22054fc

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 30% to 70% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin must be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2205/LTC2204 sample rate is

determined by droop of the sample and hold circuits. The

pipelined architecture of this ADC relies on storing analog

signals on small valued capacitors. Junction leakage will

discharge the capacitors. The speciﬁ ed minimum operating

frequency for the LTC2205/LTC2204 is 1Msps.

22054 F10

ENC–

ENC+

3.3V

130Ω 130Ω

83Ω 83Ω

MC100LVELT22

LTC2205/

LTC2204

Figure 10. ENC Drive Using a CMOS to PECL Translator

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2205 is 65Msps.

The maximum encode rate for the LTC2204 is 40Msps.

For the ADC to operate properly the encode signal should

have a 50% (±2.5%) duty cycle. Achieving a precise 50%

duty cycle is easy with differential sinusoidal drive using

a transformer or using symmetric differential logic such

as PECL or LVDS. When using a single-ended ENCODE

signal asymmetric rise and fall times can result in duty

cycles that are far from 50%.

An optional clock duty cycle stabilizer can be used if the

input clock does not have a 50% duty cycle. This circuit

uses the rising edge of ENC pin to sample the analog input.

The falling edge of ENC is ignored and an internal falling

Figure 9. Single-Ended ENC Drive,

Not Recommended for Low Jitter

22054 F09

ENC–

1.6V

VTHRESHOLD = 1.6V ENC+

0.1μF

LTC2205/

LTC2204

APPLICATIONS INFORMATION

LTC2205/LTC2204

22054fc

Data Format

The LTC2205/LTC2204 parallel digital output can be

selected for offset binary or 2’s complement format. The

format is selected with the MODE pin. This pin has a four

level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD.

An external resistor divider can be user to set the 1/3VDD

and 2/3VDD logic levels. Table 1 shows the logic states

for the MODE pin.

Table 1. MODE Pin Function

MODE Output Format

Clock Duty

Cycle Stabilizer

0(GND) Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

Overﬂ ow Bit

An overﬂ ow output bit (OF) indicates when the converter

is over-ranged or under-ranged. A logic high on the OF

pin indicates an overﬂ ow or underﬂ ow.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 11 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, isolated

from the ADC power and ground. The additional N-channel

transistor in the output driver allows operation down to

low voltages. The internal resistor in series with the output

eliminates the need for external damping resistors.

As with all high speed/high resolution converters, the digital

output loading can affect the performance. The digital

outputs of the LTC2205/LTC2204 should drive a minimum

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as a ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

output may be used but is not required since the ADC has

a series resistor of 33Ω on chip.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

APPLICATIONS INFORMATION

LTC2205/LTC2204

22054 F11

OVDD

VDD VDD

0.1μF

TYPICAL

DATA

OUTPUT

OGND

OVDD 0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

33Ω

Figure 11. Equivalent Circuit for a Digital Output Buffer

LTC2205/LTC2204

22054fc

Output Clock

The ADC has a delayed version of the encode input available

as a digital output. Both a noninverted version, CLKOUT+

and an inverted version CLKOUT– are provided. The

CLKOUT+/CLKOUT– can be used to synchronize the

converter data to the digital system. This is necessary

when using a sinusoidal encode. Data can be latched

on the rising edge of CLKOUT+ or the falling edge of

CLKOUT–. CLKOUT+ falls and CLKOUT– rises as the data

outputs are updated.

Digital Output Randomizer

Interference from the ADC digital outputs is sometimes

unavoidable. Interference from the digital outputs may be

APPLICATIONS INFORMATION

Figure 12. Functional Equivalent of Digital Output Randomizer

•

CLKOUT

D15/D0

D14/D0

D2/D0

D1/D0

D0D0

RAND = HIGH,

SCRAMBLE

ENABLED

D14

D15

LTC2205/LTC2204

CLKOUT

RAND

22054 F12

from capacitive or inductive coupling or coupling through

the ground plane. Even a tiny coupling factor can result in

discernible unwanted tones in the ADC output spectrum.

By randomizing the digital output before it is transmitted

off chip, these unwanted tones can be randomized, trading

a slight increase in the noise ﬂ oor for a large reduction in

unwanted tone amplitude.

The digital output is “Randomized” by applying an

exclusive-OR logic operation between the LSB and all

other data output bits. To decode, the reverse operation

is applied; that is, an exclusive-OR operation is applied

between the LSB and all other bits. The LSB, OF and

CLKOUT output are not affected. The output Randomizer

function is active when the RAND pin is high.

LTC2205/LTC2204

22054fc

usually a result of ADC element mismatches. An optional

internal dither mode can be enabled to randomize the input

location on the ADC transfer curve, resulting in improved

SFDR for low signal levels.

As shown in Figure 14, the output of the sample-and-hold

ampliﬁ er is summed with the output of a dither DAC. The

dither DAC is driven by a long sequence pseudo-random

number generator; the random number fed to the dither

DAC is also subtracted from the ADC result. If the dither

DAC is precisely calibrated to the ADC, very little of the

dither signal will be seen at the output. The dither signal

that does leak through will appear as white noise. The

dither DAC is calibrated to result in less than 0.5dB

elevation in the noise ﬂ oor of the ADC, as compared to

the noise ﬂ oor with dither off.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven.

OVDD can be powered with any logic voltage up to the VDD

of the ADC. OGND can be powered with any voltage from

ground up to 1V and must be less than OVDD. The logic

outputs will swing between OGND and OVDD.

Internal Dither

The LTC2205/LTC2204 are 16-bit ADCs with very linear

transfer functions; however, at low input levels even

slight imperfections in the transfer function will result in

unwanted tones. Small errors in the transfer function are

APPLICATIONS INFORMATION

Figure 13. Descrambling a Scrambled Digital Output

•

D14

D15

LTC2205/

LTC2204

PC BOARD

FPGA

CLKOUT

D15/D0

D14/D0

D2/D0

D1/D0

22054 F13

LTC2205/LTC2204

22054fc

Grounding and Bypassing

The LTC2205/LTC2204 require a printed circuit board with a

clean unbroken ground plane; a multilayer board with an

internal ground plane is recommended. The pinout of the

LTC2205/LTC2204 has been optimized for a ﬂ owthrough

layout so that the interaction between inputs and digital

outputs is minimized. Layout for the printed circuit board

should ensure that digital and analog signal lines are

separated as much as possible. In particular, care should

be taken not to run any digital track alongside an analog

signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used

at the VDD, VCM, and OVDD pins. Bypass capacitors must

be located as close to the pins as possible. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The LTC2205/LTC2204 differential inputs should run

parallel and close to each other. The input traces should

be as short as possible to minimize capacitance and to

minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2205/LTC2204 is

transferred from the die through the bottom-side exposed

pad. For good electrical and thermal performance, the

exposed pad must be soldered to a large grounded pad

on the PC board. It is critical that the exposed pad and all

ground pins are connected to a ground plane of sufﬁ cient

area with as many vias as possible.

Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit

+–

AIN–

AIN+

S/H

AMP

DIGITAL

SUMMATION OUTPUT

DRIVERS

MULTIBIT DEEP

PSEUDO-RANDOM

NUMBER

GENERATOR

16-BIT

PIPELINED

ADC CORE

PRECISION

DAC

CLOCK/DUTY

CYCLE

CONTROL

CLKOUT

D15

•

ENC

DITHER ENABLE

HIGH = DITHER ON

LOW = DITHER OFF

DITH

ENC

ANALOG

INPUT

22054 F14

LTC2205/LTC2204

APPLICATIONS INFORMATION

LTC2205/LTC2204

22054fc

APPLICATIONS INFORMATION

Ordering Guide:

DEMO BOARD NUMBER PART NUMBER RESOLUTION SPEED INPUT FREQUENCY USB I/F BOARD

DC918C-A LTC2207CUK 16-Bit 105Msps 1MHz to 70MHz DC718

DC918C-B LTC2207CUK 16-Bit 105Msps 70MHz to 140MHz DC718

DC918C-C LTC2206CUK 16-Bit 80Msps 1MHz to 70MHz DC718

DC918C-D LTC2206CUK 16-Bit 80Msps 70MHz to 140MHz DC718

DC918C-E LTC2205CUK 16-Bit 65Msps 1MHz to 70MHz DC718

DC918C-F LTC2205CUK 16-Bit 65Msps 70MHz to 140MHz DC718

DC918C-G LTC2204CUK 16-Bit 40Msps 1MHz to 70MHz DC718

DC918C-H LTC2207CUK-14 14-Bit 105Msps 1MHz to 70MHz DC718

DC918C-I LTC2207CUK-14 14-Bit 105Msps 70MHz to 140MHz DC718

DC918C-J LTC2206CUK-14 14-Bit 80Msps 1MHz to 70MHz DC718

DC918C-K LTC2206CUK-14 14-Bit 80Msps 70MHz to 140MHz DC718

DC918C-L LTC2205CUK-14 14-Bit 65Msps 1MHz to 70MHz DC718

See Web site for ordering details or contact local sales.

3.3V

NOT PROVIDED

BY DC718

CLOCK OUT

DITHER

SHUTDOWN

LSB ENABLE

MSB

CLOCK POLARITY0V

PGA

SENSE

ANALOG INPUT

(50Ω)

ENC CLOCK INPUT

(50Ω)

22076 DC918C

JUMPERS ARE SHOWN

IN DEFAULT POSITIONS

RANDOMIZER

(REQUIRES CHANGE IN

SELECTED DEVICE IN PSCOPE)

DIGITAL OUTPUTS TO

DC718 (2.5V CMOS)

LTC2205/LTC2204

22054fc

Top Side

APPLICATIONS INFORMATION

Silkscreen Top

LTC2205/LTC2204

22054fc

APPLICATIONS INFORMATION

Inner Layer 3Inner Layer 2

Inner Layer 5Inner Layer 4

LTC2205/LTC2204

22054fc

Bottom Side

Silkscreen Bottom

APPLICATIONS INFORMATION

LTC2205/LTC2204

22054fc

APPLICATIONS INFORMATION

JP5

SHDN

C15

0.1μF

C12

0.01μF

* VERSION TABLE

2.2μF

0.01μF

C10

0.01μF

ANALOG

INPUT

C28

R31

* R30

* L1

R32

T2 3

MABA-007159-

000000

*T3 3

MABA-

007159-

000000

ENCODE

INPUT

C30

0.01μF

C16

0.1μF

C17

0.1μF

R20

10k

R29

5.1Ω

R26

5.1Ω

R27

49.9Ω

R14

10Ω

R13

10Ω

R10

10Ω

R12

33.2Ω

R11

33.2Ω

100Ω

C11

8.2pF

R33

100Ω

R28

49.9Ω

R21, 10k

GND

VDD

GND

VDD

JP6

DITH

JP2

SHDN

OPEN

VDD

2.2μF

0.1μF

JP3

PGA

10k

OPEN

VDD

GND

JP4

RAND

VDD

GND

JP1 U4

NC7SV-

86P5X

OVP

GND

OVP

74VCX245BQX

3201S-40G1

RN1A 33

RN1B 33

RN1C 33

RN1D 33

RN2A 33

RN2B 33

RN2C 33

RN2D 33

RN3A 33

RN3B 33

RN3C 33

RN3D 33

RN4A 33

RN4B 33

RN4C 33

RN4D 33

20U2

OGND

OVP

74VCX245BQX

NC7S-

V86P5X

24LC025

C14

0.1μF

C19

0.1μF

C18

0.1μF

R17

10k

R18

10k

R19

10k

C13

0.1μF

20U2

VDD

T/R

GND

VCC

T/R

GND

VCC

U1*

SENSE

VCM

VDD

GND

AIN+

AIN–

GND

ENC+

ENC–

GND

VDD

OVDD

D11

D10

OGND

CLKOUT+

CLKOUT–

OVDD

VDD

GND

SHDN

DITH

OGND

OVDD

GND

PGA

RAND

MODE

D15

D14

D13

D12

OGND

OVDD

VDD

VCC

SCL

SDA

R25

1Ω

VDD

LT1763

C22

1μFC21, 0.01μF

R22

105k

R23

100k

C20

10μF

6.3V

C23

4.7μF

C27

100μF

6.3V

OPT.

C25

0.1μF

C26

0.1μF

VDD

3.3V

GND

OVP

VDD U7

OUT

ADJ

GND

BYP

GND

SHDN

22054 F15

ASSEMBLY

TYPE U1 T3 C5

C7,

C28 R30

R31,

R32 L1 INPUT FREQUENCY BITS Msps

DC918C-A LTC2207CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < AIN < 70MHz 16 105

DC918C-B LTC2207CUK WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < AIN < 140MHz 16 105

DC918C-C LTC2206CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < AIN < 70MHz 16 80

DC918C-D LTC2206CUK WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < AIN < 140MHz 16 80

DC918C-E LTC2205CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < AIN < 70MHz 16 65

DC918C-F LTC2205CUK WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < AIN < 140MHz 16 65

DC918C-G LTC2204CUK MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < AIN < 70MHz 16 40

DC918C-H LTC2207CUK-14 MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < AIN < 70MHz 14 105

DC918C-I LTC2207CUK-14 WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < AIN < 140MHz 14 105

DC918C-J LTC2206CUK-14 MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < AIN < 70MHz 14 80

DC918C-K LTC2206CUK-14 WBC1-1L 1.8pF 3.9pF 182 43.2 18nH 70MHz < AIN < 140MHz 14 80

DC918C-L LTC2205CUK-14 MABAES0060 4.7pF 8.2pF 86.6 86.6 56nH 1MHz < AIN < 70MHz 14 65

LTC2205/LTC2204

22054fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,

no responsibility is assumed for its use. Linear Technology Corporation makes no representation that

the interconnection of its circuits as described herein will not infringe on existing patent rights.

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-1704)

PACKAGE DESCRIPTION

7.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1

CHAMFER

C = 0.35

0.40 ± 0.1

4847

BOTTOM VIEW—EXPOSED PAD

5.50 REF

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UK48) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

5.50 REF

(4 SIDES) 6.10 ±0.05 7.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

5.15 ± 0.10

5.15 ± 0.05

R = 0.10

TYP

LTC2205/LTC2204

22054fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0109 REV C • PRINTED IN USA

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