LTC1407-1/LTC1407A-1
1
14071fb
BLOCK DIAGRAM
DESCRIPTION
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
The LTC
®
1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps
ADCs with two 1.5Msps simultaneously sampled differ-
ential inputs. The devices draw only 4.7mA from a single
3V supply and come in a tiny 10-lead MS package. A sleep
shutdown feature lowers power consumption to 10µW.
The combination of speed, low power and tiny package
makes the LTC1407-1/LTC1407A-1 suitable for high speed,
portable applications.
The LTC1407-1/LTC1407A-1 contain two separate differ-
ential inputs that are sampled simultaneously on the rising
edge of the CONV signal. These two sampled inputs are
then converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert –1.25V to 1.25V bipolar inputs differ-
entially. The absolute voltage swing for CH0+, CH0–, CH1+
and CH1– extends from ground to the supply voltage.
The serial interface sends out the two conversion results in 32
clocks for compatibility with standard serial interfaces.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
THD, 2nd and 3rd vs Input Frequency
for Differential Input Signals
FEATURES
APPLICATIONS
n 3Msps Sampling ADC with Two Simultaneous
Differential Inputs
n 1.5Msps Throughput per Channel
n Low Power Dissipation: 14mW (Typ)
n 3V Single Supply Operation
n ±1.25V Differential Input Range
n Pin Compatible 0V to 2.5V Input Range Version
(LTC1407/LTC1407A)
n 2.5V Internal Bandgap Reference with External
Overdrive
n 3-Wire Serial Interface
n Sleep (10µW) Shutdown Mode
n Nap (3mW) Shutdown Mode
n 80dB Common Mode Rejection at 100kHz
n Tiny 10-Lead MS Package
n Telecommunications
n Data Acquisition Systems
n Uninterrupted Power Supplies
n Multiphase Motor Control
n I & Q Demodulation
n Industrial Radio
–
+
1
2
7
3
6
S & H
–
+
4
5
S & H
GND
11 EXPOSED PAD
VREF
10µF
CH0–
CH0+
CH1–
CH1+
3V10µF
LTC1407A-1
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
1407A1 BD
3Msps
14-BIT ADC
14-BIT LATCH14-BIT LATCH
FREQUENCY (MHz)
0.1
–80
THD, 2ND, 3RD (dB)
–74
–68
–62
–56
11020
14071 TA01b
–86
–92
–98
–104
–50
–44
THD 3RD
2ND
LTC1407-1/LTC1407A-1
2
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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) .................................................4V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................. –0.3V to (VDD + 0.3V)
Power Dissipation ...............................................100mW
Operation Temperature Range
LTC1407C-1/LTC1407AC-1 ...................... 0°C to 70°C
LTC1407I-1/LTC1407AI-1 .....................–40°C to 85°C
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Notes 1, 2)
1
2
3
4
5
CH0+
CH0–
VREF
CH1+
CH1–
10
9
8
7
6
CONV
SCK
SDO
VDD
GND
TOP VIEW
11
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD IS GND (PIN 11), MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1407CMSE-1#PBF LTC1407CMSE-1#TRPBF LTBGT 10-Lead Plastic MSOP 0°C to 70°C
LTC1407IMSE-1#PBF LTC1407IMSE-1#TRPBF LTBGV 10-Lead Plastic MSOP –40°C to 85°C
LTC1407ACMSE-1#PBF LTC1407ACMSE-1#TRPBF LTBGW 10-Lead Plastic MSOP 0°C to 70°C
LTC1407AIMSE-1#PBF LTC1407AIMSE-1#TRPBF LTBGX 10-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
LTC1407-1 LTC1407A-1
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l12 14 Bits
Integral Linearity Error (Notes 5, 17) l–2 ±0.25 2 –4 ±0.5 4 LSB
Offset Error (Notes 4, 17) l–10 ±1 10 –20 ±2 20 LSB
Offset Match from CH0 to CH1 (Note 17) –5 ±0.5 5 –10 ±1 10 LSB
Gain Error (Notes 4, 17) l–30 ±5 30 –60 ±10 60 LSB
Gain Match from CH0 to CH1 (Note 17) –5 ±1 5 –10 ±2 10 LSB
Gain Tempco Internal Reference (Note 4)
External Reference ±15
±1 ±15
±1 ppm/°C
ppm/°C
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. With internal reference, VDD = 3V.
LTC1407-1/LTC1407A-1
3
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DYNAMIC ACCURACY
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. With internal reference, VDD = 3V. Single-ended signal drive CH0+/CH1+ with
CHO–/CH1– = 1.5V DC. Differential signals drive both inputs of each channel with VCM = 1.5V DC.
LTC1407-1 LTC1407A-1
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
SINAD Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal (Note 19)
750kHz Input Signal (Note 19)
100kHz Input Signal, External VREF = 3.3V,
VDD ≥ 3.3V (Note 19)
750kHz Input Signal, External VREF = 3.3V,
VDD ≥ 3.3V (Note 19)
l68
70.5
70.5
72.0
72.0
70
73.5
73.5
76.3
76.3
dB
dB
dB
dB
THD Total Harmonic
Distortion
100kHz First 5 Harmonics (Note 19)
750kHz First 5 Harmonics (Note 19) l
–87
–83 –77
–90
–86 –80
dB
dB
SFDR Spurious Free
Dynamic Range
100kHz Input Signal (Note 19)
750kHz Input Signal (Note 19)
87
83
90
86
dB
dB
IMD Intermodulation
Distortion
0.625VP-P 1.4MHz Summed with 0.625VP-P, 1.56MHz
into CH0+ and Inverted into CHO–. Also Applicable
to CH1+ and CH1–
–82 –82 dB
Code-to-Code
Transition Noise
VREF = 2.5V (Note 17) 0.25 1 LSBRMS
Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15) 50 50 MHz
Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Differential Input Range (Notes 3, 8, 9) 2.7V ≤ VDD ≤ 3.3V –1.25 to 1.25 V
VCM Analog Common Mode + Differential
Input Range (Note 10) 0 to VDD V
IIN Analog Input Leakage Current l1µA
CIN Analog Input Capacitance (Note 18) 13 pF
tACQ Sample-and-Hold Acquisition Time (Note 6) l39 ns
tAP Sample-and-Hold Aperture Delay Time 1 ns
tJITTER Sample-and-Hold Aperture Delay Time Jitter 0.3 ps
tSK Sample-and-Hold Aperture Skew from CH0 to CH1 200 ps
CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V
fIN = 100MHz, VIN = 0V to 3V –60
–15 dB
dB
ANALOG INPUT
LTC1407-1/LTC1407A-1
4
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INTERNAL REFERENCE CHARACTERISTICS
TA = 25°C. VDD = 3V.
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 2.5 V
VREF Output Tempco 15 ppm/°C
VREF Line Regulation VDD = 2.7V to 3.6V, VREF = 2.5V 600 µV/V
VREF Output Resistance Load Current = 0.5mA 0.2 Ω
VREF Setting Time 2ms
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 3.3V l2.4 V
VIL Low Level Input Voltage VDD = 2.7V l0.6 V
IIN Digital Input Current VIN = 0V to VDD l±10 µA
CIN Digital Input Capacitance 5pF
VOH High Level Output Voltage VDD = 3V, IOUT = –200µA l2.5 2.9 V
VOL Low Level Output Voltage VDD = 2.7V, IOUT = 160µA
VDD = 2.7V, IOUT = 1.6mA l
0.05
0.10 0.4
V
V
IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD l±10 µA
COZ Hi-Z Output Capacitance DOUT 1pF
ISOURCE Output Short-Circuit Source Current VOUT = 0V, VDD = 3V 20 mA
ISINK Output Short-Circuit Sink Current VOUT = VDD = 3V 15 mA
POWER REQUIREMENTS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 2.7 3.6 V
IDD Supply Current Active Mode, fSAMPLE = 1.5Msps
Nap Mode
Sleep Mode (LTC1407)
Sleep Mode (LTC1407A)
l
l
4.7
1.1
2.0
2.0
7.0
1.5
15
10
mA
mA
µA
µA
PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 12 mW
LTC1407-1/LTC1407A-1
5
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specifi cations apply for a single-ended CH0+
or CH1+ input with CH0– or CH1– grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defi ned as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defi ned for the voltage difference
between CH0+ and CH0– or CH1+ and CH1–. Performance is specifi ed
with CHO– = 1.5V DC while driving CHO+ and with CH1– = 1.5V DC while
driving CH1+.
Note 9: The absolute voltage at CH0+, CH0–, CH1+ and CH1– must be
within this range.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel
(Conversion Rate)
l1.5 MHz
tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l667 ns
tSCK Clock Period (Note 16) l19.6 10000 ns
tCONV Conversion Time (Note 6) 32 34 SCLK cycles
t1Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns
t2CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns
t3SCK Before CONV (Note 6) 0 ns
t4Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns
t5SCK to Sample Mode (Note 6) 4 ns
t6CONV to Hold Mode (Notes 6, 11) 1.2 ns
t732nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns
t8Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns
t9SCK to Hi-Z at SDO (Notes 6, 12) 6 ns
t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. VDD = 3V.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A-1 is measured and specifi ed with 14-bit
Resolution (1LSB = 152µV) and the LTC1407-1 is measured and specifi ed
with 12-bit Resolution (1LSB = 610µV).
Note 18: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
Note 19: Full-scale sinewaves are fed into the noninverting inputs while
the inverting inputs are kept at 1.5V DC.
LTC1407-1/LTC1407A-1
6
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TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
ENOBs and SINAD
vs Input Sinewave Frequency
for Differential Input Signals
THD, 2nd and 3rd
vs Input Frequency for
Differential Input Signals
SFDR vs Input Frequency for
Differential Input Signals
98kHz Sine Wave 4096 Point
FFT Plot
748kHz Sine Wave 4096 Point
FFT Plot
ENOBs and SINAD
vs Input Sinewave Frequency
THD, 2nd and 3rd
vs Input Frequency SFDR vs Input Frequency
VDD = 3V, TA = 25°C. Single-ended signals drive
+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1)
FREQUENCY (MHz)
0.1
10.0
ENOBs (BITS)
SINAD (dB)
11.0
12.0
1 10 100
14071 G01
9.0
9.5
10.5
11.5
8.5
8.0
62
68
74
56
59
65
71
53
50
FREQUENCY (MHz)
0.1
–80
THD, 2ND, 3RD (dB)
–74
–68
–62
–56
1 10 100
14071 G02
–86
–92
–98
–104
–50
–44
THD
3RD
2ND
FREQUENCY (MHz)
0.1
62
SNR (dB)
56
50 1 10 100
14071 G04
68
65
59
53
71
74
FREQUENCY (MHz)
0.1
10.0
ENOBs (BITS)
SINAD (dB)
11.0
12.0
1 10 100
14071 G05
9.0
9.5
10.5
11.5
8.5
8.0
62
68
74
56
59
65
71
53
50
FREQUENCY (MHz)
0.1
68
SFDR (dB)
56
44 1 10 100
14071 G03
80
74
62
50
86
92
98
104
FREQUENCY (MHz)
0.1
–80
THD, 2nd, 3rd (dB)
–74
–68
–62
–56
11020
14071 G06
–86
–92
–98
–104
–50
–44
THD 3RD
2ND
FREQUENCY (MHz)
0.1
68
SFDR (dB)
56
44 1 10 100
14071 G07
80
74
62
50
86
92
98
104
FREQUENCY (kHz)
MAGNITUDE (dB)
–60
–30
–20
14071 G08
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0200 400100 300 600500 700
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–60
–30
–20
14071 G09
–70
–80
–120 200 400100 300 600500 700
–100
0
–10
–40
–50
–90
–110
LTC1407-1/LTC1407A-1
7
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TYPICAL PERFORMANCE CHARACTERISTICS
Differential Linearity for CH0 with
Internal 2.5V Reference
Integral Linearity End Point Fit for
CH0 with Internal 2.5V Reference
Integral Linearity End Point Fit for
CH0 with Internal 2.5V Reference
for Differential Input Signals
Differential Linearity for CH1 with
Internal 2.5V Reference
Integral Linearity End Point Fit for
CH1 with Internal 2.5V Reference
1403kHz Input Summed with
1563kHz Input IMD 4096 Point FFT
Plot for Differential Input Signals
748kHz Sine Wave 4096 Point FFT
Plot for Differential Input Signals
10.7MHz Sine Wave 4096 Point
FFT Plot for Differential Input
Signals
VDD = 3V, TA = 25°C. Single-ended signals drive
+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1)
Integral Linearity End Point Fit for
CH1 with Internal 2.5V Reference
for Differential Input Signals
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–60
–30
–20
14071 G10
–70
–80
–120 200 400100 300 600500 700
–100
0
–10
–40
–50
–90
–110
FREQUENCY (Hz)
MAGNITUDE (dB)
–60
–30
–20
14071 G11
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0371k185k 556k 741k
FREQUENCY (Hz)
MAGNITUDE (dB)
–60
–30
–20
14071 G12
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0371k185k 556k 741k
OUTPUT CODE
0
–1.0
DIFFERENTIAL LINEARITY (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
14071 G13
–0.6
0.6
0.8
0.2
12288 16384
OUTPUT CODE
0
–4.0
INTEGRAL LINEARITY (LSB)
–3.2
–1.6
–0.8
0
4.0
1.6
4096 8192
14071 G14
–2.4
2.4
3.2
0.8
12288 16384
OUTPUT CODE
0
–4.0
INTEGRAL LINEARITY (LSB)
–3.2
–1.6
–0.8
0
4.0
1.6
4096 8192
14071 G15
–2.4
2.4
3.2
0.8
12288 16384
OUTPUT CODE
0
–1.0
DIFFERENTIAL LINEARITY (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
14071 G16
–0.6
0.6
0.8
0.2
12288 16384
OUTPUT CODE
0
–4.0
INTEGRAL LINEARITY (LSB)
–3.2
–1.6
–0.8
0
4.0
1.6
4096 8192
14071 G17
–2.4
2.4
3.2
0.8
12288 16384
OUTPUT CODE
0
–4.0
INTEGRAL LINEARITY (LSB)
–3.2
–1.6
–0.8
0
4.0
1.6
4096 8192
14071 G18
–2.4
2.4
3.2
0.8
12288 16384
LTC1407-1/LTC1407A-1
8
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TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3V, TA = 25°C. Single ended signals drive
+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1)
Full-Scale Signal Frequency
Response CMRR vs Frequency Crosstalk vs Frequency
Output Match with Simultaneous
Input Steps at CH0 and CH1
from 25Ω PSSR vs Frequency
Differential and Integral Linearity
vs Conversion Rate SINAD vs Conversion Rate
VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1)
CONVERSION RATE (MSPS)
2
LINEARITY (LSB)
2
5
6
4
14071 G19
1
0
–4 2.5 2.752.25 3 3.25 3.5 3.75
–2
8
7
4
3
–1
–3
MAX INL
MAX DNL
MIN DNL
MIN INL
CONVERSION RATE (Msps)
2 2.5 3 3.5 4
68
S/(N+D) (dB)
69
71
72
73
78
75
14071 G20
70
76
77
74
EXTERNAL VREF = 3.3V, fIN ~ fS/3
EXTERNAL VREF = 3.3V, fIN ~ fS/40
INTERNAL VREF = 2.5V, fIN ~ fS/3
INTERNAL VREF = 2.5V, fIN ~ fS/40
FREQUENCY (Hz)
1M 10M 100M 1G
–18
AMPLITUDE (dB)
–12
–6
0
14071 G21
–24
–30
–36
6
12
FREQUENCY (Hz)
–80
CMRR (dB)
–40
0
–100
–60
–20
100 1k
14071 G22
–120 10k 100k 1M 10M 100M
CH0 CH1
FREQUENCY (Hz)
–70
CROSSTALK (dB)
–50
–20
–80
–60
–40
–30
100 1k 10k 100k 1M 10M
14071 G23
–90
CH0 TO CH1
CH1 TO CH0
TIME (ns)
–5
OUTPUT CODE
6144
8192
10240
10 20
14071 G24
4096
2048
005 15
12288
14336
16384
25
CH0 AND CH1
RISING
CH0
CH1
CH0 AND CH1
FALLING
FREQUENCY (Hz)
110
–50
PSRR (dB)
–45
–40
–35
–30
100 1k 10k 100k 1M
14071 G25
–55
–60
–65
–70
–25
LTC1407-1/LTC1407A-1
9
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TYPICAL PERFORMANCE CHARACTERISTICS
CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates
fully differentially with respect to CH0–, with a –1.25V to
1.25V differential swing with respect to CH0– and a 0 to
VDD absolute input range.
CH0– (Pin 2): Inverting Channel 0. CH0– operates fully
differentially with respect to CH0+, with a 1.25V to –1.25V
differential swing with respect to CH0+ and a 0 to VDD
absolute input range.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and
a solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Can be
overdriven by an external reference voltage ≥2.55V and
≤VDD.
CH1+ (Pin 4): Noninverting Channel 1. CH1+ operates
fully differentially with respect to CH1–, with a –1.25V to
1.25V differential swing with respect to CH1– and a 0 to
VDD absolute input range.
CH1– (Pin 5): Inverting Channel 1. CH1– operates fully
differentially with respect to CH1+, with a 1.25V to –1.25V
differential swing with respect to CH1+ and a 0 to VDD
absolute input range.
GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
fl ow through these connections.
VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND pin and
solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum) in parallel with 0.1µF ceramic. Keep in
mind that internal analog currents and digital output signal
currents fl ow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each pair of
output data words represent the two analog input channels
at the start of the previous conversion. The output format
is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fi xed high or fi xed low state starts nap
mode. Four or more pulses with SCK in fi xed high or fi xed
low state starts sleep mode.
VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1)
Reference Voltage vs VDD
Reference Voltage
vs Load Current
PIN FUNCTIONS
VDD (V)
2.4890
VREF (V)
2.4894
2.4898
2.4902
2.4892
2.4896
2.4900
2.8 3.0 3.2 3.4
14071 G26
2.6 3.6
LOAD CURRENT (mA)
0.4 0.8 1.2 1.6
14071 G27
2.00.20 0.6 1.0 1.4 1.8
2.4890
VREF (V)
2.4894
2.4898
2.4902
2.4892
2.4896
2.4900
LTC1407-1/LTC1407A-1
10
14071fb
BLOCK DIAGRAM
–
+
1
2
7
3
6
S & H
–
+
4
5
S & H
GND
11 EXPOSED PAD
VREF
10µF
CH0–
CH0+
CH1–
CH1+
3V10µF
LTC1407A-1
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
1407A1 BD
3Msps
14-BIT ADC
14-BIT LATCH14-BIT LATCH
LTC1407-1/LTC1407A-1
11
14071fb
TIMING DIAGRAMS
SCK
CONV
INTERNAL
S/H STATUS
SDO
*BITS MARKED “X” AFTER D0 SHOULD BE IGNORED
t7
t3t1
13433 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2120 22 23 24 25 26 27 28 29 30 31 32 33 34 1
t2
t6
t8t9t9
t8
t4t5
t8
SAMPLE HOLD HOLD HOLD
Hi-Z Hi-Z Hi-Z
tCONV
12-BIT DATA WORD 12-BIT DATA WORD
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
tTHROUGHPUT
14071 TD01
D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X*D9 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X*D9
SAMPLE
tACQ
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
SCK
CONV
INTERNAL
S/H STATUS
SDO
t7
t3t1
13433 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2120 22 23 24 25 26 27 28 29 30 31 32 33 34 1
t2
t6
t8t9t9
t8
t4t5
t8
SAMPLE HOLD HOLD HOLD
Hi-Z Hi-Z Hi-Z
tCONV
14-BIT DATA WORD 14-BIT DATA WORD
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
tTHROUGHPUT
1407A1 TD01
D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D11 D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D11
SAMPLE
tACQ
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
LTC1407-1 Timing Diagram
LTC1407A-1 Timing Diagram
LTC1407-1/LTC1407A-1
12
14071fb
TIMING DIAGRAMS
Nap Mode Waveforms
SCK
CONV
NAP
SCK
CONV
NAP
SLEEP
VREF
t1t1
t12
t1
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
1407 TD02
Sleep Mode Waveforms
SCK to SDO Delay
t8
t10
SCK
SDO
14071 TD03
VIH
VOH
VOL
t9
SCK
SDO
VIH
90%
10%
LTC1407-1/LTC1407A-1
13
14071fb
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1407-1/LTC1407A-1
are easy to drive. The inputs may be driven differentially or
as a single-ended input (i.e., the CH0– input is AC grounded
at VCC/2). All four analog inputs of both differential analog
input pairs, CH0+ with CH0– and CH1+ with CH1–, are
sampled at the same instant. Any unwanted signal that is
common to both inputs of each input pair will be reduced by
the common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charging
the sample-and-hold capacitors at the end of conversion.
During conversion, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low, then the LTC1407-1/LTC1407A-1 inputs can
be driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with high
source impedance, a buffer amplifi er must be used. The
main requirement is that the amplifi er driving the analog
input(s) must settle after the small current spike before
the next conversion starts (settling time must be 39ns for
full throughput rate). Also keep in mind, while choosing
an input amplifi er, the amount of noise and harmonic
distortion added by the amplifi er.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifi er is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifi er from charging
the sampling capacitor, choose an amplifi er that has a low
output impedance (<100) at the closed-loop bandwidth
frequency. For example, if an amplifi er is used in a gain
of 1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100. The
second requirement is that the closed-loop bandwidth must
be greater than 40MHz to ensure adequate small-signal
settling for full throughput rate. If slower op amps are
used, more time for settling can be provided by increasing
the time between conversions. The best choice for an op
amp to drive the LTC1407-1/LTC1407A-1 depends on the
application. Generally, applications fall into two categories:
AC applications where dynamic specifi cations are most
critical and time domain applications where DC accuracy
and settling time are most critical. The following list is a
summary of the op amps that are suitable for driving the
LTC1407-1/LTC1407A-1.
LTC1566-1: Low Noise 2.3MHz Continuous Time Low-
pass Filter.
LT
®
1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifi er.
2.7V to ±15V supplies. Very high AVOL, 500µV offset and
520ns settling to 0.5LSB for a 4V swing. THD and noise
are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2VP-P into 1k, VS = 5V), making the part excellent for
AC applications (to 1/3 Nyquist) where rail-to-rail perfor-
mance is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifi er.
2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and
400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
–93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into 1k, VS = 5V), making the part excellent for
AC applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/ampli-
fi er, 8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc distortion at
5MHz, unity-gain stable, rail-to-rail in and out, 10mA/am-
plifi er, 3.5nV/√
Hz
.
LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,
unity-gain stable, rail-to-rail in and out, 15mA/amplifi er,
16nV/√Hz.
LinearView is a trademark of Linear Technology Corporation.
LTC1407-1/LTC1407A-1
14
14071fb
APPLICATIONS INFORMATION
LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual
Voltage Mode Operational Amplifi er.
LT6200: 165MHz GBWP, –85dBc distortion at 1MHz,
unity-gain stable, rail-to-rail in and out, 15mA/amplifi er,
0.95nV/√Hz.
LT6203: 100MHz GBWP, –80dBc distortion at 1MHz,
unity-gain stable, rail-to-rail in and out, 3mA/amplifi er,
1.9nV/√Hz.
LT6600: Amplifi er/Filter Differential In/Out with 10MHz
Cutoff.
INPUT FILTERING AND SOURCE IMPEDANCE
The noise and the distortion of the input amplifi er and
other circuitry must be considered since they will add
to the LTC1407-1/LTC1407A-1 noise and distortion. The
small-signal bandwidth of the sample-and-hold circuit is
50MHz. Any noise or distortion products that are pres-
ent at the analog inputs will be summed over this entire
bandwidth. Noisy input circuitry should be fi ltered prior
to the analog inputs to minimize noise. A simple 1-pole
RC fi lter is suffi cient for many applications. For example,
Figure 1 shows a 47pF capacitor from CHO+ to ground
and a 51 source resistor to limit the net input bandwidth
to 30MHz. The 47pF capacitor also acts as a charge
reservoir for the input sample-and-hold and isolates the
ADC input from sampling-glitch sensitive circuitry. High
quality capacitors and resistors should be used since these
Figure 1. RC Input Filter
components can add distortion. NPO and silvermica type
dielectric capacitors have excellent linearity. Carbon surface
mount resistors can generate distortion from self heating
and from damage that may occur during soldering. Metal
fi lm surface mount resistors are much less susceptible to
both problems. When high amplitude unwanted signals
are close in frequency to the desired signal frequency a
multiple pole fi lter is required.
High external source resistance, combined with 13pF
of input capacitance, will reduce the rated 50MHz input
bandwidth and increase acquisition time beyond 39ns.
INPUT RANGE
The analog inputs of the LTC1407-1/LTC1407A-1 may be
driven fully differentially with a single supply. Either input
may swing up to 3V, provided the differential swing is no
greater than 1.25V. In the valid input range, each input of
each channel is always up to ±1.25V away from the other
input of each channel. The –1.25V to 1.25V range is also
ideally suited for AC-coupled signals in single supply
applications. Figure 2 shows how to AC-couple signals
in a single supply system without needing a mid-supply
1.5V DC external reference. The DC common mode level
is supplied by the previous stage that is already bounded
by single supply voltage of the system. The common
mode range of the inputs extends from ground to the
supply voltage VDD. If the difference between the CH0+
and CH0– inputs or the CH1+ and CH1– inputs exceeds
1.25V, the output code will stay fi xed at zero and all ones,
and if this difference goes below –1.25V, the output code
will stay fi xed at one and all zeros.
Figure 2. AC Coupling of AC Signals with 1kHz Low Cut
LTC1407-1/
LTC1407A-1
CH0+
CH0–
VREF
GND
14071 F01
1
2
11
3
10µF
47pF*
51*
CH1+
CH1–
4
5
47pF*
*TIGHT TOLERANCE REQUIRED TO AVOID
APERTURE SKEW DEGRADATION
51Ω*
ANALOG
INPUT
ANALOG
INPUT
VCM
1.5V DC
VCM
1.5V DC
+
CHO+
4.09V
C4
10µF14071 F02
R2
1.6k
C2
1µF
C1
1µF
C1, C2: FILM TYPE
C3: COG TYPE
C4: CERAMIC BYPASS
R1
1.6k
1
2
3
LTC1407-1/
LTC1407A-1
CHO–
VREF
R3
51Ω
C3
56pF
VIN
LTC1407-1/LTC1407A-1
15
14071fb
APPLICATIONS INFORMATION
INTERNAL REFERENCE
The LTC1407-1/LTC1407A-1 have an on-chip, temperature
compensated, bandgap reference that is factory trimmed
near 2.5V to obtain a precise ±1.25V input span. The ref-
erence amplifi er output VREF, (Pin 3) must be bypassed
with a capacitor to ground. The reference amplifier is
stable with capacitors of 1µF or greater. For the best noise
performance, a 10µF ceramic or a 10µF tantalum in paral-
lel with a 0.1µF ceramic is recommended. The VREF pin
can be overdriven with an external reference as shown
in Figure 3. The voltage of the external reference must be
higher than the 2.5V of the open-drain P-channel output
of the internal reference. The recommended range for an
external reference is 2.55V to VDD. An external reference
at 2.55V will see a DC quiescent load of 0.75mA and as
much as 3mA during conversion.
errors (DNL) are largely independent of the common
mode voltage. However, the offset error will vary. CMRR
is typically better than 60dB.
Figure 5 shows the ideal input/output characteristics for
the LTC1407-1/LTC1407A-1. The code transitions occur
midway between successive integer LSB values (i.e.,
0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code
is 2’s complement with 1LSB = 2.5V/16384 = 153µV for
the LTC1407A-1 and 1LSB = 2.5V/4096 = 610µV for the
LTC1407-1. The LTC1407A-1 has 1LSB RMS of Gaussian
white noise. Figure 6a shows the LTC1819 converting a
single-ended input signal to differential input signals for
optimum THD and SFDR performance as shown in the
FFT plot (Figure 6b).
Figure 4. CMRR vs Frequency
Figure 3
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a unipolar voltage span that
equals the difference between the voltage at the reference
buffer output VREF (Pin 3) and the voltage at the Exposed
Pad ground. The differential input range of ADC is –1.25V
to 1.25V when using the internal reference. The internal
ADC is referenced to these two nodes. This relationship
also holds true with an external reference.
DIFFERENTIAL INPUTS
The ADC will always convert the bipolar difference of CH0+
minus CH0– or the bipolar difference of CH1+ minus CH1–,
independent of the common mode voltage at either set
of inputs. The common mode rejection holds up at high
frequencies (see Figure 4). The only requirement is that
both inputs not go below ground or exceed VDD. Integral
nonlinearity errors (INL) and differential nonlinearity
LTC1407-1/
LTC1407A-1
VREF
GND
14071 F02
3
11
10µF
3V REF
Figure 5. LTC1407-1/LTC1407A-1 Transfer Characteristic
FREQUENCY (Hz)
–80
CMRR (dB)
–40
0
–100
–60
–20
100 1k
14071 F04
–120 10k 100k 1M 10M 100M
CH0 CH1
INPUT VOLTAGE (V)
2’s COMPLEMENT OUTPUT CODE
14071 F05
011...111
011...110
011...101
100...000
100...001
100...010
FS – 1LSB–FS
LTC1407-1/LTC1407A-1
16
14071fb
APPLICATIONS INFORMATION
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1407-1/LTC1407A-1, a printed
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the four input
wires of the two input channels should be kept matched.
But each pair of input wires to the two input channels
should be kept separated by a ground trace to avoid high
frequency crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Block Diagram on the fi rst page of this data sheet. For
optimum performance, a 10µF surface mount tantalum
capacitor with a 0.1µF ceramic is recommended for the VDD
and VREF pins. Alternatively, 10µF ceramic chip capacitors
such as X5R or X7R may be used. The capacitors must be
located as close to the pins as possible. The traces con-
necting the pins and the bypass capacitors must be kept
short and should be made as wide as possible. The VDD
bypass capacitor returns to GND (Pin 6) and the VREF by-
pass capacitor returns to the Exposed Pad ground (Pin 11).
Care should be taken to place the 0.1µF VDD bypass ca-
pacitor as close to Pins 6 and 7 as possible.
Figure 7 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated
Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially
Figure 6b. LTC1407-1 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
Figure 7. Recommended Layout
–CH0 OR
–CH1
LTC1407A-1
+CH0 OR
+CH1
C1
47pF
R1
51
C3
1µF
C5
0.1µF
5V
–5V
C4
1µF
R5
1k
1.5VCM
R3
499
R4
499 R6
1k
C2
47pF
R2
51
C6
0.1µF
VIN
1.25VP-P
MAX
1407A F06a
–
+
U1
1/2 LT1819
–
+
U2
1/2 LT1819
FREQUENCY (Hz)
MAGNITUDE (dB)
–60
–30
–20
14031 F06b
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0371k185k 556k 741k
1407-1 F07
LTC1407-1/LTC1407A-1
17
14071fb
APPLICATIONS INFORMATION
at the LTC1407-1/LTC1407A-1 Exposed Pad. The ground
return from the LTC1407-1/LTC1407A-1 Pin 6 to the power
supply should be low impedance for noise-free operation.
The Exposed Pad of the 10-lead MSE package is also tied
to Pin 6 and the LTC1407-1/LTC1407A-1 GND. The Exposed
Pad should be soldered on the PC board to reduce ground
connection inductance. Digital circuitry grounds must be
connected to the digital supply common.
POWER-DOWN MODES
Upon power-up, the LTC1407-1/LTC1407A-1 are initialized
to the active state and are ready for conversion. The nap
and sleep mode waveforms show the power-down modes
for the LTC1407-1/LTC1407A-1. The SCK and CONV inputs
control the power-down modes (see Timing Diagrams). Two
rising edges at CONV, without any intervening rising edges
at SCK, put the LTC1407-1/LTC1407A-1 in nap mode and
the power drain drops from 14mW to 6mW. The internal
reference remains powered in nap mode. One or more
rising edges at SCK wake up the LTC1407-1/LTC1407A-1
for service very quickly and CONV can start an accurate
conversion within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407-1/LTC1407A-1 in sleep mode
and the power drain drops from 14mW to 10µW. To bring the
part out of sleep mode requires one or more rising SCK edges
followed by a nap request. Then one or more rising edges
at SCK wake up the LTC1407-1/LTC1407A-1 for operation.
When nap mode is entered after sleep mode, the reference
that was shut down in sleep mode is reactivated.
The internal reference (VREF ) takes 2ms to slew and settle
with a 10µF load. Using sleep mode more frequently com-
promises the settled accuracy of the internal reference.
Note that for slower conversion rates, the nap and sleep
modes can be used for substantial reductions in power
consumption.
DIGITAL INTERFACE
The LTC1407-1/LTC1407A-1 have a 3-wire SPI (serial
protocol interface) interface. The SCK and CONV inputs
and SDO output implement this interface. The SCK and
CONV inputs accept swings from 3V logic and are TTL
compatible, if the logic swing does not exceed VDD. A de-
tailed description of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC1407-1/
LTC1407A-1 until the following 32 SCK rising edges have
occurred. The duty cycle of CONV can be arbitrarily chosen
to be used as a frame sync signal for the processor serial
port. A simple approach to generate CONV is to create a pulse
that is one SCK wide to drive the LTC1407-1/LTC1407A-1
and then buffer this signal to drive the frame sync input
of the processor serial port. It is good practice to drive the
LTC1407-1/LTC1407A-1 CONV input fi rst to avoid digital
noise interference during the sample-to-hold transition
triggered by CONV at the start of conversion. It is also good
practice to keep the width of the low portion of the CONV
signal greater than 15ns to avoid introducing glitches in
the front end of the ADC just before the sample-and-hold
goes into hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. As shown in the interface
circuit examples, the SCK and CONV inputs should be
driven fi rst, with digital buffers used to drive the serial port
interface. Also note that the master clock in the DSP may
already be corrupted with jitter, even if it comes directly
from the DSP crystal. Another problem with high speed
processor clocks is that they often use a low cost, low
speed crystal (i.e., 10MHz) to generate a fast, but jittery,
phase-locked-loop system clock (i.e., 40MHz). The jitter
in these PLL-generated high speed clocks can be several
nanoseconds. Note that if you choose to use the frame
sync signal generated by the DSP port, this signal will
have the same jitter of the DSP’s master clock.
LTC1407-1/LTC1407A-1
18
14071fb
APPLICATIONS INFORMATION
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also updates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out two
sets of 12/14 data bits, with the MSB sent fi rst. A simple
approach is to generate SCK to drive the LTC1407-1/
LTC1407A-1 fi rst and then buffer this signal with the
appropriate number of inverters to drive the serial clock
input of the processor serial port. Use the falling edge of
the clock to latch data from the serial data output (SDO)
into your processor serial port. The 14-bit serial data will
be received right justifi ed, in two 16-bit words with 32 or
more clocks per frame sync. It is good practice to drive
the LTC1407-1/LTC1407A-1 SCK input fi rst to avoid digi-
tal noise interference during the internal bit comparison
decision by the internal high speed comparator. Unlike the
CONV input, the SCK input is not sensitive to jitter because
the input signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out two sets of 12/14 bits in 2’s complement format in the
output data stream after the third rising edge of SCK after
the start of conversion with the rising edge of CONV. The
two 12-/14-bit words are separated by two clock cycles in
high impedance mode. Please note the delay specifi cation
from SCK to a valid SDO. SDO is always guaranteed to
be valid by the next rising edge of SCK. The 32-bit output
data stream is compatible with the 16-bit or 32-bit serial
port of most processors.
HARDWARE INTERFACE TO TMS320C54x
The LTC1407-1/LTC1407A-1 are serial output ADCs
whose interface has been designed for high speed buff-
ered serial ports in fast digital signal processors (DSPs).
Figure 8 shows an example of this interface using a
TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments,
in real time, at the full 3Msps conversion rate of the
LTC1407-1/LTC1407A-1. The DSP assembly code sets
frame sync mode at the BFSR pin to accept an external
positive going pulse and the serial clock at the BCLKR
pin to accept an external positive edge clock. Buffers near
the LTC1407-1/LTC1407A-1 may be added to drive long
tracks to the DSP to prevent corruption of the signal to
LTC1407-1/LTC1407A-1. This confi guration is adequate
to traverse a typical system board, but source resistors
at the buffer outputs and termination resistors at the DSP,
may be needed to match the characteristic impedance
of very long transmission lines. If you need to terminate
the SDO transmission line, buffer it fi rst with one or two
74ACxx gates. The TTL threshold inputs of the DSP port
respond properly to the 3V swing used with the LTC1407-1/
LTC1407A-1.
Figure 8. DSP Serial Interface to TMS320C54x
14071 F08
7
10
9
8
6
3-WIRE SERIAL
INTERFACELINK
VDD
CONV
SCK
LTC1407-1/
LTC1407A-1
SDO
VCC
BFSR
BCLKR
TMS320C54x
BDR
GND
CONV
0V TO 3V LOGIC SWING
CLK
5V3V
B13 B12
LTC1407-1/LTC1407A-1
19
14071fb
APPLICATIONS INFORMATION
; 12-03-03 ******************************************************************
; Files: 014SIAB.ASM -> 1407A Sine wave collection with Serial Port interface
; bvectors.asm both channels collected in sequence in the same 2k record.
; s2k14ini.asm Buffered mode 2k buffer size.
; First element at 1024, last element at 1023, two middles at 2047 and 0000
; bipolar mode
; Works 16 or 64 clock frames.
; negative edge BCLKR
; negative BFSR pulse
; -0 data shifted
; ***************************************************************************
.width 160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”, 0x500,0 ;Set address of executable
.setsect “vectors”, 0x180,0 ;Set address of incoming 1403 data
.setsect “buffer”, 0x800,0 ;Set address of BSP buffer for clearing
.setsect “result”, 0x1800,0 ;Set address of result for clearing
.text ;.text marks start of code
start:
;this label seems necessary
;Make sure /PWRDWN is low at J1-9
;to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h ; stop timer
tspc = #0h ; stop TDM serial port to AC01
pmst = #01a0h ; set up iptr. Processor Mode STatus register
sp = #0700h ; init stack pointer.
dp = #0 ; data page
ar2 = #1800h ; pointer to computed receive buffer.
ar3 = #0800h ; pointer to Buffered Serial Port receive buffer
ar4 = #0h ; reset record counter
call sineinit ; Double clutch the initialization to insure a proper
sinepeek:
call sineinit ; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
wait goto wait
; ———————— Buffered Receive Interrupt Routine —————————
breceive:
ifr = #10h ; clear interrupt fl ags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull ; if this still the fi rst half get next half
bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))
return_enable
LTC1407-1/LTC1407A-1
20
14071fb
APPLICATIONS INFORMATION
; ——————— mask and shift input data ——————————————
bufull:
b = *ar3+ << -0 ; load acc b with BSP buffer and shift right -0
b = #07FFFh & b ; mask out the TRISTATE bits with #03FFFh
b = b ^ #2000h ; invert the MSB for bipolar operation
;
*ar2+ = data(#0bh) ; store B to out buffer and advance AR2 pointer
TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h
if (TC) goto start ; restart if out buffer is at 1fffh
goto bufull
; ————————— dummy bsend return ————————————
bsend return_enable ;this is also a dummy return to defi ne bsend
;in vector table fi le BVECTORS.ASM
; ——————————— end ISR ——————————————
.copy “c:\dskplus\1403\s2k14ini.asm” ;initialize buffered serial port
.space 16*32 ;clear a chunk at the end to mark the end
;======================================================================
;
; VECTORS
;
;======================================================================
.sect “vectors” ;The vectors start here
.copy “c:\dskplus\1403\bvectors.asm” ;get BSP vectors
.sect “buffer” ;Set address of BSP buffer for clearing
.space 16*0x800
.sect “result” ;Set address of result for clearing
.space 16*0x800
.end
; ***************************************************************************
; File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus 10.Jul.96
; BSP vectors and Debugger vectors
; TDM vectors just return
; ***************************************************************************
; The vectors in this table can be confi gured for processing external and
; internal software interrupts. The DSKplus debugger uses four interrupt
; vectors. These are RESET, TRAP2, INT2, and HPIINT.
; * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
;
; All other vector locations are free to use. When programming always be sure
; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
;
;
;
LTC1407-1/LTC1407A-1
21
14071fb
APPLICATIONS INFORMATION
.title “Vector Table”
.mmregs
reset goto #80h ;00; RESET * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
nmi return_enable ;04; non-maskable external interrupt
nop
nop
nop
trap2 goto #88h ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
.space 52*16 ;0C-3F: vectors for software interrupts 18-30
int0 return_enable ;40; external interrupt int0
nop
nop
nop
int1 return_enable ;44; external interrupt int1
nop
nop
nop
int2 return_enable ;48; external interrupt int2
nop
nop
nop
tint return_enable ;4C; internal timer interrupt
nop
nop
nop
brint goto breceive ;50; BSP receive interrupt
nop
nop
nop
bxint goto bsend ;54; BSP transmit interrupt
nop
nop
nop
trint return_enable ;58; TDM receive interrupt
nop
nop
nop
txint return_enable ;5C; TDM transmit interrupt
nop
nop
int3 return_enable ;60; external interrupt int3
nop
nop
nop
hpiint dgoto #0e4h ;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
LTC1407-1/LTC1407A-1
22
14071fb
APPLICATIONS INFORMATION
.space 24*16 ;68-7F; reserved area
**********************************************************************
* (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 *
**********************************************************************
* *
* File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus *
* for use with 1407 in buffered mode *
* BSPC and SPC are the same in the ‘C542 *
* BSPCE and SPCE seem the same in the ‘C542 *
**********************************************************************
.title “Buffered Serial Port Initialization Routine”
ON .set 1
OFF .set !ON
YES .set 1
NO .set !YES
BIT_8 .set 2
BIT_10 .set 1
BIT_12 .set 3
BIT_16 .set 0
GO .set 0x80
**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled.
*
*******************************************************************************************
*LTC1407 timing from board with 10MHz crystal.
*
*10MHz, divided from 40MHz, forced to CLKIN by 1407 board.
*
*Horizontal scale is 25ns/chr or 100ns period at BCLKR
*
*Timing measured at DSP pins. Jxx pin labels for jumper cable.
*
*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/
~~~~~~~~~~~*
*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/
~\_/~\_/~*
*BDR Pin J1-26 _—_—_—<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—<B13-
B12*
*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/
~~~~~~~\_______/~~~~~*
*C542 read 0 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0 0
B13 B12*
*
*
* negative edge BCLKR
* negative BFSR pulse
* no data shifted
* 1’ cable from counter to CONV at DUT
LTC1407-1/LTC1407A-1
23
14071fb
APPLICATIONS INFORMATION
* 2’ cable from counter to CLK at DUT
*No right shift is needed to right justify the input data in the main program
*
*the two msbs should also be masked
*
*******************************************************************************************
*
Loopback .set NO ;(digital looback mode?) DLB bit
Format .set BIT_16 ;(Data format? 16,12,10,8) FO bit
IntSync .set NO ;(internal Frame syncs generated?) TXM bit
IntCLK .set NO ;(internal clks generated?) MCM bit
BurstMode .set YES ;(if BurstMode=NO, then Continuous) FSM bit
CLKDIV .set 3 ;(3=default value, 1/4 CLOCKOUT)
PCM_Mode .set NO ;(Turn on PCM mode?)
FS_polarity .set YES ;(change polarity)YES=^^^\_/^^^, NO=___/^\___
CLK_polarity .set NO ;(change polarity)for BCLKR YES=_/^, NO=~\_
Frame_ignore .set !YES ;(inverted !YES -ignores frame)
XMTautobuf .set NO ;(transmit autobuffering)
RCVautobuf .set YES ;(receive autobuffering)
XMThalt .set NO ;(transmit buff halt if XMT buff is full)
RCVhalt .set NO ;(receive buff halt if RCV buff is full)
XMTbufAddr .set 0x800 ;(address of transmit buffer)
XMTbufSize .set 0x000 ;(length of transmit buffer)
RCVbufAddr .set 0x800 ;(address of receive buffer)
RCVbufSize .set 0x800 ;(length of receive buffer)works up to 800
*
* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up
* valid buffer start and length values. Page 9-44
*
*
**********************************************************************
.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync
<<5)) ,SPCval
.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format &
1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval
.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)),
SPCEval
sineinit:
bspc = #SPCval ; places buffered serial port in reset
ifr = #10h ; clear interrupt fl ags
imr = #210h ; Enable HPINT,enable BRINT0
intm = 0 ; all unmasked interrupts are enabled.
bspce = #SPCEval ; programs BSPCE and ABU
axr = #XMTbufAddr ; initializes transmit buffer start address
bkx = #XMTbufSize ; initializes transmit buffer size
arr = #RCVbufAddr ; initializes receive buffer start address
bkr = #RCVbufSize ; initializes receive buffer size
bspc = #(SPCval | GO) ; bring buffered serial port out of reset
return ;for transmit and receive because GO=0xC0
LTC1407-1/LTC1407A-1
24
14071fb
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1664 Rev C)
MSOP (MSE) 0908 REV C
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 p 0.152
(.193 p .006)
0.497 p 0.076
(.0196 p .003)
REF
8910
10
1
76
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
2.083 p 0.102
(.082 p .004)
2.794 p 0.102
(.110 p .004)
0.50
(.0197)
BSC
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.83 p 0.102
(.072 p .004)
2.06 p 0.102
(.081 p .004)
0.1016 p 0.0508
(.004 p .002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
LTC1407-1/LTC1407A-1
25
14071fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 12/09 Update Pin Confi guration 2
(Revision history begins at Rev B)
LTC1407-1/LTC1407A-1
26
14071fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0110 REV B • PRINTED IN USA
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD
LTC1609 16-Bit, 250ksps Serial ADC 5V Confi gurable Bipolar/Unipolar Inputs
LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Unipolar Inputs, MSOP Package
LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Bipolar Inputs, MSOP Package
LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 14mW, 2-Channel Unipolar Input Range
LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD
LTC1420 12-Bit, 10Msps Parallel ADC 5V, Selectable Spans, 72dB SINAD
LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW
LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD
LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span
LTC1864/LTC1865
LTC1864L/LTC1865L
16-Bit, 250ksps 1-/2-Channel Serial ADCs 5V or 3V (L-Version), Micropower, MSOP Package
DACs
LTC1666/LTC1667
LTC1668
12-/14-/16-Bit, 50Msps DAC 87dB SFDR, 20ns Settling Time
LTC1592 16-Bit, Serial SoftSpan™ IOUT DAC ±1LSB INL/DNL, Software Selectable Spans
References
LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift
LT1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift
LT1460-2.5 Micropower Series Voltage Reference 0.10% Initial Accuracy, 10ppm Drift
SoftSpan is a trademark of Linear Technology Corporation.
