General Description
The DS4420 is a fully differential, programmable-gain
amplifier for audio applications. It features a -35dB to
+25dB gain range controlled by an I2C interface and it
is optimized to drive loads as low as 50Ω. The gain is
adjustable in 3dB increments across the entire range.
Three address inputs, used to select the I2C slave
address, enable up to eight devices on a common bus.
The product operates from a single 5V supply over a
-20°C to +70°C temperature range. It is offered in a
3mm x 3mm TDFN package.
Applications
Telephone Headsets
Audio Volume Control
Microphone Gain Control
Features
Differential Inputs and Outputs
-35dB to +25dB Adjustable Gain
Low Output Noise
Low-Distortion Driving into a 50ΩLoad
3dB Gain Steps Programmed through I2C Interface
5V Single Supply
20kHz Bandwidth for All Gain Settings
Small 3mm x 3mm x 0.8mm TDFN Package
Up to Eight DS4420s can be Placed on the Same
I2C Bus
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
______________________________________________
Maxim Integrated Products
1
Rev 0; 9/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
DS4420+ -20°C to +70°C 14 TDFN-EP*
+
Denotes lead-free package.
*
EP = Exposed paddle.
DS4420
-35dB
TO +25dB
GAIN
A2
A1
A0
SDA
SCL
IN+
OUT+
OUT-
IN-
GND
VCC AGND AVCC
AUDIO
AMPLIFIER
AUDIO
SOURCE
MICROPR0CESSOR-
CONTROLLED GAIN
I2C INTERFACE
Typical Operating Circuit
TDFN
(3mm x 3mm x 0.8mm)
TOP VIEW
2
4
5
13
11
10
OUT+
AGND
N.C.
A1
SCL
SDA
1
+
14 AVCC
OUT-
A2
312
A0
69IN-VCC
78IN+GND
DS4420
Pin Configuration
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
2 _____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(TA= -20°C to +70°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on VCC, SDA, and SCL
Relative to GND.................................................-0.5V to +6.0V
Voltage on A0, A1, and A2
Relative to GND......................................-0.5V to (VCC + 0.5V;
not to exceed 6.0V)
Voltage on IN+, IN-, OUT-, and OUT+
Relative to AGND .................................-0.5V to (AVCC + 0.5V;
not to exceed 6.0V)
Voltage on AVCC Relative to VCC..........................-0.3V to +0.3V
Voltage on AGND Relative to GND .......................-0.3V to +0.3V
Output Current ..................................................................150mA
Operating Temperature Range ...........................-20°C to +70°C
Storage Temperature .....................See J-STD-020 Specification
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital Supply Voltage VCC (Note 1) +4.5 +5.5 V
Analog Supply Voltage AVCC VCC V
Analog Ground AGND (See Figure 5) GND V
Input Logic 1 (SCL, SDA, A0, A1, A2) VIH 2.0 VCC
+ 0.3 V
Input Logic 0 (SCL, SDA, A0, A1, A2) VIL -0.3 +0.8 V
ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, TA = -20°C to +70°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC VCC = 5.5V, RL = ∞, VIN = 0V differential
(Note 9) 1.7 3 mA
Standby Current ISTBY VCC = 5.5V (Notes 2, 9) 140 µA
Input Leakage (SDA, SCL, A2, A1, A0) IIL VCC = 5.5V 1 µA
Output Leakage (SDA) IL1µA
VOL = 0.4V 3
Output-Current Low (SDA) IOL VOL = 0.6V 6 mA
Input Voltage Range VIN Differential -19 +1 dBV
Max Peak-to-Peak Input Level VINP-P Differential 3.2 V
Input Resistance RIN Differential, active mode (Note 3) 29 49 60 kΩ
Input Common-Mode Voltage VIN:CM 0.45 x
VCC
0.55 x
VCC V
Output Voltage VORL = 50Ω differential 6 dBV
Output Peak-to-Peak Signal Swing VOP-P Differential 5.6 V
Output Common-Mode Voltage VO:CM 0.45 x
VCC
0.5 x
VCC
0.55 x
VCC V
Output Offset Voltage VO:OS AV = +25dB -20 +20 mV
VOUT = GND 95
Amplifier Output Current
(Sourcing) IOS1 VOUT = VCC - 0.75V 64 mA
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
_____________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.5V to +5.5V, TA = -20°C to +70°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VOUT = VCC 89
Amplifier Output Current
(Sinking) IOS2 VOUT = 0.75V 64 mA
Resistive Load Range RLDifferential 50 50k Ω
Capacitive Load CLCap to GND (Note 4) 100 pF
Closed-Loop Bandwidth All gain settings (Note 5) 20 20k Hz
Passband Flatness 20Hz to 20kHz (Notes 2, 5) -1 +1 dB
A = -35dB, 300Hz to 3.4kHz -123
Output Noise (Note 5) NOA = +25dB, 300Hz to 3.4kHz -88 dBV
RL = 50Ω, VO ≤ +6dBV,
f = 1kHz, A = ±16dB 0.03 1.0
Total Harmonic Distortion (Note 5) THD
RL = 1kΩ, VO ≤ +6dBV,
f = 1kHz, A = ±16dB 0.01
%
Gain Range A -35 +25 dB
Gain Step Size AS2.0 3.0 4.0 dB
Gain Accuracy AERR1 (Note 10) -2.5 +2.5 dB
Mute and Standby Mode Gain AMUTE (Note 5) -90 dB
S tand b y M od e E xi t Ti m et
PU (Note 6) 10 µs
I
2
C AC ELECTRICAL CHARACTERISTICS (See Figure 3)
(VCC = +4.5V to +5.5V, TA= -20°C to +70°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 7) 0 400 kHz
Bus Free Time Between STOP and
START Conditions tBUF 1.3 µs
Hold Time (Repeated) START
Condition tHD:STA 0.6 µs
Low Period of SCL tLOW 1.3 µs
High Period of SCL tHIGH 0.6 µs
Data Hold Time tHD:DAT 0 0.9 µs
Data Setup Time tSU:DAT 100 ns
Start Setup Time tSU:STA 0.6 µs
SDA and SCL Rise Time tR(Note 8) 20 +
0.1CB300 ns
SDA and SCL Fall Time tF(Note 8) 20 +
0.1CB300 ns
STOP Setup Time tSU:STO 0.6 µs
SDA and SCL Capacitive Loading CB(Note 8) 400 pF
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
4 _____________________________________________________________________
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Standby supply current specified with SDA = SCL = VCC, the output disconnected, and A0, A1, and A2 driven to within
100mV of VCC or GND.
Note 3: Input resistance during mute and power-down is approximately one-half of the active-mode resistance.
Note 4: Each output is capable of driving a 100nF capacitive load to ground using an external 10Ω series resistor. However, output
capacitance should be minimal for optimal distortion performance.
Note 5: Guaranteed by design.
Note 6: This is the time it takes for the output to become active after exiting standby mode.
Note 7: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-
mode timing.
Note 8: CB= total capacitance of one bus line in picofarads.
Note 9: The current specified is the sum of VCC and AVCC supply currents.
Note 10: Gain accuracy specified assuming the output impedance of signal source driving of the DS4420 is ≤ 2.5kΩ.
Typical Operating Characteristics
(TA= +25°C, VCC = AVCC = 5.0V, unless otherwise noted.)
70
74
72
78
76
82
80
84
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(STANDBY MODE ENABLED)
DS4420 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
4.50 4.75 5.00 5.25 5.50
VCC = AVCC = SDA = SCL
NO LOAD
IN+ AND IN- SHORTED
TOGETHER
+25°C
+70°C
-20°C
1.8
1.7
1.6
1.5
1.4
4.50 5.004.75 5.25 5.50
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(SETTING AT -11dB)
DS4420 toc02
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
VCC = AVCC = SDA = SCL
NO LOAD
IN+ AND IN- SHORTED
TOGETHER +25°C-20°C
+70°C
0
0.6
0.4
0.2
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 5 10 15 20
SUPPLY CURRENT vs. GAIN SETTING
DS4420 toc03
GAIN SETTING
SUPPLY CURRENT (mA)
IN+ AND IN- SHORTED
TOGETHER
NO LOAD
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
_____________________________________________________________________
5
0
40
20
80
60
100
120
01051520
POWER-SUPPLY REJECTION RATIO
vs. GAIN SETTING
DS4420 toc04
GAIN SETTING
PSRR (dB)
1kHz
50Ω LOAD
20kHz
50Ω LOAD
0
-80
1000 10,000 100,000
COMMON-MODE FREQUENCY RESPONSE
SWEEP AT -11dB
-60
-70
DS4420 toc05
FREQUENCY (Hz)
CMRR (dB)
-40
-50
-30
-20
-10
NO LOAD
1000 100,000 1,000,000
GAIN vs. FREQUENCY RESPONSE
DS4420 toc06
FREQUENCY (Hz)
GAIN (dB)
10,000
30
-40
-30
-20
-10
0
20
10
50Ω LOAD
-2dB SETTING
-35dB SETTING
+25dB SETTING
-40
-20
-30
0
-10
20
10
30
GAIN vs. SETTING
DS4420 toc07
GAIN SETTING
GAIN (dB)
0 5 10 15 20
IN+ AND IN- SHORTED TOGETHER
ACROSS -20°C TO +70°C
WITH 50Ω LOAD, 1kΩ LOAD,
AND NO LOAD
-140
-100
-120
-60
-80
-20
-40
0
CCITT NOISE vs. GAIN SETTING
DS4420 toc08
GAIN SETTING
CCITT NOISE (dBV)
0 5 10 15 20
NO LOAD 0.018
0.000
10 1000100 10,000 100,000
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
0.004
0.002
DS4420 toc09
FREQUENCY (Hz)
THD+N (%)
0.008
0.006
0.012
0.010
0.014
0.016
WITH 50Ω LOAD
AND 1kΩ LOAD
1VRMS INPUT
-11dB SETTING
0.09
0.00
10 1000100 10,000 100,000
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
0.02
0.01
DS4420 toc10
FREQUENCY (Hz)
THD+N (%)
0.04
0.03
0.06
0.05
0.07
0.08
WITH 50Ω LOAD
AND 1kΩ LOAD
1VRMS INPUT
+10dB SETTING
-40
-30
-35
-15
-20
-25
-10
-5
5
0
10
2 4 6 8 10 12 14 16 18 20
TOTAL HARMONIC DISTORTION vs. VOUT
DS4420 toc11
GAIN SETTING
VOUT (dB)
0.000
0.004
0.002
0.010
0.008
0.006
0.012
0.014
0.018
0.016
0.020
THD+N (%)
50Ω LOAD
1kHz 2VRMS
INPUT VOUT
THD+N
Typical Operating Characteristics (continued)
(TA= +25°C, VCC = AVCC = 5.0V, unless otherwise noted.)
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
6 _____________________________________________________________________
Detailed Description
The key features of the DS4420 are illustrated in the
Block Diagram
.
Controlling the DS4420
The DS4420 is controlled through the I2C serial inter-
face. Gain, mute, and standby settings all reside in one
control register located at memory address F8h (see
Figure 1). Writes to other memory addresses are invalid.
Programmable Gain
The gain is adjustable from -35dB to +25dB in 3dB
increments. The gain is determined by the five LSBs of
the control register as shown in Figure 1. Gain settings
greater than 14h are invalid.
Mute Mode
The DS4420 is placed in mute mode by setting the mute
bit located in the control register (see Figure 1). When in
this mode, the output of the amplifier is muted and is
independent of the gain setting. The input-to-output
attenuation is specified in the
Electrical Characteristics
table as AMUTE.
Standby Mode
Standby mode is entered by setting the standby control
bit (see Figure 1). Setting the standby control bit mutes
the output of the amplifier and places the DS4420 into a
low-current (ISTBY) consumption state. Unlike mute
mode, however, standby mode is intended for use when
no input signal is present. While in standby mode, the
DS4420 maintains input and output common-mode bias
voltages. The device produces no audible clicks or
pops when entering or exiting the standby state. The
time required for the output to become active when
exiting standby mode is specified as tPU.
Pin Description
PIN NAME FUNCTION
1A2
2A1
3A0
Address Select Inputs—Determine I2C Slave Address. Device address is 1010A2A1A0.
4 SCL I2C Serial Clock—Input for I2C Clock
5 SDA I2C Serial Data—Input/Output for I2C Data
6V
CC Digital Power-Supply Terminal
7 GND Ground
8 IN+
9 IN- Differential Audio Input Signal
10 N.C. No Connection
11 AGND Analog Ground (Must be Connected to GND)
12 OUT-
13 OUT+ Differential Audio Output Signal
14 AVCC Analog Power Supply (Must be Connected to VCC)
EP EP Exposed Paddle. Connect to GND and AGND.
Block Diagram
DS4420
3dB
GAIN
STEPS
AVCC
AGNDGND
VCC
A2A1A0
SDA
SCL
IN+
IN-
OUT+
OUT-
I2C INTERFACE
-35dB
TO +25dB
GAIN
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
_____________________________________________________________________ 7
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave
address plus a R/Wbit (see Figure 2). The DS4420’s
slave address is determined by the state of the A0, A1,
and A2 address pins. These pins allow up to eight
DS4420s to reside on the same I2C bus. Address pins
connected to GND result in a ‘0’ in the corresponding
bit position in the slave address. Conversely, address
pins connected to VCC result in a ‘1’ in the correspond-
ing bit positions. For example, the DS4420’s slave
address byte is A0h when A0, A1, and A2 pins are
grounded. I2C communication is described in detail in
the
I
2
C Serial Interface Description
section.
Figure 1. Control Register Description
Control Register (F8h)
Power-Up Default: 1000 0000 b
F8h Standby x Mute Gain Setting[4:0]
bit 7 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
Standby: Places the DS4420 in standby mode.
0 = Normal operation.
1 = Places the DS4420 in standby mode. (Power-up default.)
bit 6 Don’t care.
bit 5
Mute: Mutes the amplifier output, regardless of the current gain setting.
0 = Normal operation. (Power-up default.)
1 = Mutes the amplifier output.
bit 4:0 Gain Setting: Five-bit gain setting. The power-up default is setting 00h.
GAIN
SETTING
(hex)
GAIN
(dB)
GAIN
SETTING
(hex)
GAIN
(dB)
00h -35 0Bh -2
01h -32 0Ch +1
02h -29 0Dh +4
03h -26 0Eh +7
04h -23 0Fh +10
05h -20 10h +13
06h -17 11h +16
07h -14 12h +19
08h -11 13h +22
09h -8 14h +25
0Ah -5 15h to 1Fh Illegal
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
1
MSB
SLAVE
ADDRESS*
LSB
010
A2 A1 A0 R/W
READ/WRITE
BIT
Figure 2. DS4420 Slave Address Byte
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
8 _____________________________________________________________________
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers. See the timing diagram
(Figure 3) and the
I
2
C AC Electrical Characteristics
table for additional information.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated start condition is issued identically to a nor-
mal start condition.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into
the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock
pulses including when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave dur-
ing a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one (done by releasing SDA) during the 9th
bit. Timing (Figure 3) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
SDA
SCL
tHD:STA
tLOW
tHIGH
tRtF
tBUF
tHD:DAT
tSU:DAT REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP START
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
Figure 3. I2C Timing Diagram
DS4420
I2C Programmable-Gain Amplifier
for Audio Applications
_____________________________________________________________________ 9
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minate communication so the slave will return control of
SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/Wbit in the least significant bit.
The DS4420’s slave address is determined by the state
of the A0, A1, and A2 address pins as shown in Figure
2. Address pins connected to GND result in a ‘0’ in the
corresponding bit position in the slave address.
Conversely, address pins connected to VCC result in a
‘1’ in the corresponding bit positions.
When the R/Wbit is 0 (such as in A0h), the master is indi-
cating it will write data to the slave. If R/Wis set to a 1,
(A1h in this case), the master is indicating it wants to read
from the slave.
If an incorrect (nonmatching) slave address is written,
the DS4420 will assume the master is communicating
with another I2C device and ignore the communication
until the next start condition is sent.
Memory Address: During an I2C write operation to the
DS4420, the master must transmit a memory address to
identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
I2C Communication
Writing a Single Byte to a Slave: The master must gen-
erate a start condition, write the slave address byte (R/W
= 0), write the memory address, write the byte of data,
and generate a stop condition. The master must read the
slave’s acknowledgement during all byte write operations.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read oper-
ation occurs at the present value of the memory
address counter. A dummy write cycle can be used to
force the address pointer to a desired location. To do
this, the master generates a start condition, writes the
slave address byte (R/W=0), writes the memory
address where it desires to read, generates a repeated
start condition, writes the slave address byte (R/W= 1),
reads the data byte with a NACK to indicate the end of
the transfer, and generates a stop condition.
See Figure 4 for I2C communication examples.
Applications Information
Power-Supply Decoupling
The DS4420 has separate supply voltages for its ana-
log and digital circuitry. For best noise and distortion
performance, place a 0.1µF or 0.01µF capacitor from
VCC to GND and from AVCC to AGND. These capaci-
tors should be placed as close as possible to the sup-
ply and ground pins of the device.
XXXXXXXX
101 0 A
00A1
A2111 1 0001
101 0 A
00A1
A2111 1 0001
101 0 A
01
A1
A2
COMMUNICATIONS KEY
WRITE THE GAIN SETTING F8h
READ THE GAIN SETTING F8h
8-BITS ADDRESS OR DATA
NOTE 2: THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
START ACK
NOT
ACK
S
S
S
A
A
AA
P
ASr AN
P
REGISTER SETTING
REGISTER SETTING
A
PN
Sr
STOP
REPEATED
START
NOTE 1: ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
Figure 4. I2C Communication Examples
Exposed Paddle
The DS4420 exposed paddle is not electrically isolated.
It must be soldered to ground for proper operation.
Input-Coupling Capacitors
The DS4420 is designed to be operated with an AC-
coupled input signal. The input resistance, RIN, is suffi-
ciently large to allow the use of small and inexpensive
external capacitors. The input resistance combined
with the AC-coupling capacitor will create a highpass
filter. The -3dB cutoff frequency of the highpass, fC, is
given by:
where CIN is the external coupling capacitor and RIN is
the internal input resistance.
At the cutoff frequency, the input signal will be attenuat-
ed 3dB, with less attenuation as the signal’s frequency
increases beyond the cutoff frequency. To guarantee
passband flatness, the cutoff frequency of the filter
should be designed using the specified minimum input
resistance, and placed well below the desired flat band
of the circuit. The typical input resistance should only
be used to estimate typical performance.
Internal Ground Connections
The DS4420’s ground pins, GND and AGND, must be
connected together externally. Internally, they are con-
nected as shown in Figure 5.
Chip Topology
TRANSISTOR COUNT: 5347
SUBSTRATE CONNECTED TO: Ground
Package Information
For the latest package outline information, go to www.maxim-
ic.com/DallasPackInfo.
fCR
CIN IN
1
2
=××πGND AGND
13Ω
TYPICAL
Figure 5. Internal Ground Connections
Springer
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
I2C Programmable-Gain Amplifier
for Audio Applications
DS4420
