TPS62800YKAT - TEXAS INSTRUMENTS

October, 2017 − Rev. 1 1Publication Order Number:

DTC115EP/D

MUN5336DW1,

NSBC115EPDXV6

Complementary Bias

Resistor Transistors

R1 = 100 kW, R2 = 100 kW

NPN and PNP Transistors with Monolithic

Bias Resistor Network

This series of digital transistors is designed to replace a single

device and its external resistor bias network. The Bias Resistor

Transistor (BRT) contains a single transistor with a monolithic bias

network consisting of two resistors; a series base resistor and a

base-emitter resistor. The BRT eliminates these individual

components b y integrating them into a single device. The use of a BRT

can reduce both system cost and board space.

Features

•Simplifies Circuit Design

•Reduces Board Space

•Reduces Component Count

•NSV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q101

Qualified and PPAP Capable

•These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS

Compliant

MAXIMUM RATINGS

(TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)

Rating Symbol Max Unit

Collector-Base Voltage VCBO 50 Vdc

Collector-Emitter Voltage VCEO 50 Vdc

Collector Current − Continuous IC100 mAdc

Input Forward Voltage VIN(fwd) 40 Vdc

Input Reverse Voltage VIN(rev) 10 Vdc

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

ORDERING INFORMATION

Device Package Shipping†

MUN5336DW1T1G,

NSVMUN5336DW1T1G* SOT−363 3,000 / Tape & Reel

NSBC115EPDXV6T1G,

NSVBC115EPDXV6T1G* SOT−563 4,000 / Tape & Reel

† For information on tape and reel specifications, including part orientation and

tape sizes, please refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

*This document contains information on some products that are still under development.

ON Semiconductor reserves the right to change or discontinue these products without

notice.

www.onsemi.com

MARKING

DIAGRAMS

PIN CONNECTIONS

36 M G

36 = Specific Device Code

M = Date Code*

G= Pb-Free Package

(Note: Microdot may be in either location)

*Date Code orientation may vary depending up-

on manufacturing location.

SOT−363

CASE 419B

(1)(2)(3)

(6)(5)(4)

6SOT−563

CASE 463A 36 MG

36 = Specific Device Code

M = Month Code

G= Pb−Free Package

MUN5336DW1, NSBC115EPDXV6

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THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

MUN5336DW1 (SOT−363) ONE JUNCTION HEATED

Total Device Dissipation

TA = 25°C (Note 1)

(Note 2)

Derate above 25°C (Note 1)

(Note 2)

PD187

256

1.5

2.0

mW/°C

Thermal Resistance, (Note 1)

Junction to Ambient (Note 2) RqJA 670

490 °C/W

MUN5336DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3)

Total Device Dissipation

TA = 25°C (Note 1)

(Note 2)

Derate above 25°C (Note 1)

(Note 2)

PD250

385

2.0

3.0

mW/°C

Thermal Resistance,

Junction to Ambient (Note 1)

(Note 2)

RqJA 493

325

°C/W

Thermal Resistance,

Junction to Lead (Note 1)

(Note 2)

RqJL 188

208

°C/W

Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C

NSBC115EPDXV6 (SOT−563) ONE JUNCTION HEATED

Total Device Dissipation

TA = 25°C (Note 1)

Derate above 25°C (Note 1)

PD357

2.9 mW

mW/°C

Thermal Resistance,

Junction to Ambient (Note 1) RqJA 350 °C/W

NSBC115EPDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3)

Total Device Dissipation

TA = 25°C (Note 1)

Derate above 25°C (Note 1)

PD500

4.0 mW

mW/°C

Thermal Resistance,

Junction to Ambient (Note 1) RqJA 250 °C/W

Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C

1. FR−4 @ Minimum Pad.

2. FR−4 @ 1.0 ×1.0 Inch Pad.

3. Both junction heated values assume total power is sum of two equally powered channels.

MUN5336DW1, NSBC115EPDXV6

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ELECTRICAL CHARACTERISTICS (TA=25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Collector-Base Cutoff Current

(VCB =50V, I

E=0) ICBO − − 100 nAdc

Collector-Emitter Cutoff Current

(VCE =50V, I

B=0) ICEO − − 500 nAdc

Emitter-Base Cutoff Current

(VEB = 6.0 V, IC=0) IEBO − − 0.05 mAdc

Collector-Base Breakdown Voltage

(IC=10mA, IE=0) V(BR)CBO 50 − − Vdc

Collector-Emitter Breakdown Voltage (Note 4)

(IC= 2.0 mA, IB=0) V(BR)CEO 50 − − Vdc

ON CHARACTERISTICS

DC Current Gain (Note 4)

(IC= 5.0 mA, VCE =10V) hFE 80 150 −

Collector-Emitter Saturation Voltage (Note 4)

(IC= 10 mA, IB= 0.3 mA) VCE(sat) − − 0.25 V

Input Voltage (Off)

(VCE = 5.0 V, IC= 100 mA) (NPN)

(VCE = 5.0 V, IC= 100 mA) (PNP)

Vi(off) −

−1.2

1.2 0.5

0.5

Vdc

Input Voltage (On)

(VCE = 0.3 V, IC= 3.0 mA) (NPN)

(VCE = 0.3 V, IC= 3.0 mA) (PNP)

Vi(on) 3.0

3.0 1.7

1.6 −

−

Vdc

Output Voltage (On)

(VCC = 5.0 V, VB= 5.5 V, RL= 1.0 kW)VOL − − 0.2 Vdc

Output Voltage (Off)

(VCC = 5.0 V, VB= 0.5 V, RL= 1.0 kW)VOH 4.9 − − Vdc

Input Resistor R1 70 100 130 kW

Resistor Ratio R1/R20.8 1.0 1.2

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤2%.

Figure 1. Derating Curve

AMBIENT TEMPERATURE (°C)

1251007550250−25−50

100

150

200

250

300

PD, POWER DISSIPATION (mW)

150

(1) (2) (1) SOT−363; 1.0 ×1.0 Inch Pad

(2) SOT−563; Minimum Pad

350

400

MUN5336DW1, NSBC115EPDXV6

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TYPICAL CHARACTERISTICS − NPN TRANSISTOR

MUN5336DW1, NSBC115EPDXV6

100

0.1 0102030355

100

0510

2.8

2.4

1.6

1.2

0.8

0.4

001020304050

VR, REVERSE VOLTAGE (V)

Figure 2. VCE(sat) vs. IC

IC, COLLECTOR CURRENT (mA)

010203040

Figure 3. DC Current Gain

0.1 1 10

IC, COLLECTOR CURRENT (mA)

Figure 4. Output Capacitance Figure 5. Output Current vs. Input Voltage

Vin, INPUT VOLTAGE (V)

Figure 6. Input Voltage vs. Output Current

IC, COLLECTOR CURRENT (mA)

0.1

0.01

VCE = 10 V

1000

100

10 10

f = 10 kHz

lE = 0 A

TA = 25°C

TA= −25°C25°C

75°C

25°C

TA= −25°C

VO = 5 V

VO = 0.2 V TA= −25°C25°C

75°C

VCE(sat), COLLECTOR−EMITTER VOLTAGE (V

)

IC/IB = 10

hFE, DC CURRENT GAIN

TA= −25°C25°C

75°C

, CAPACITANCE (pF)

3.6

3.2

15 20 25 30 35 4

0.1

IC, COLLECTOR CURRENT (mA)

15 25

Vin, INPUT VOLTAGE (V)

5152535

2.0

MUN5336DW1, NSBC115EPDXV6

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TYPICAL CHARACTERISTICS − PNP TRANSISTOR

MUN5336DW1, NSBC115EPDXV6

Figure 7. VCE(sat) vs. ICFigure 8. DC Current Gain

IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)

403020 50100

0.01

0.1

100100.1

100

1000

Figure 9. Output Capacitance Figure 10. Output Current vs. Input Voltage

VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)

50403020100

2016 2812840

0.1

100

Figure 11. Input Voltage vs. Output Current

IC, COLLECTOR CURRENT (mA)

4030 5020100

0.1

100

VCE(sat), COLLECTOR−EMITTER

VOLTAGE (V)

hFE, DC CURRENT GAIN

Cob, OUTPUT CAPACITANCE (pF)

IC, COLLECTOR CURRENT (mA)

Vin, INPUT VOLTAGE (V)

IC/IB = 10

150°C

−55°C

25°C

VCE = 10 V

150°C

−55°C

25°C

f = 10 kHz

IE = 0 A

TA = 25°C

VO = 5 V

150°C

−55°C

25°C

VO = 0.2 V

150°C

−55°C

25°C

0.01

MUN5336DW1, NSBC115EPDXV6

www.onsemi.com

PACKAGE DIMENSIONS

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-

SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.

4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY AND DATUM H.

5. DATUMS A AND B ARE DETERMINED AT DATUM H.

6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE

LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.

7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN

EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-

TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OF THE FOOT.

Cddd M

123

654

6X DIM MIN NOM MAX

MILLIMETERS

A−−− −−− 1.10

A1 0.00 −−− 0.10

ddd

b0.15 0.20 0.25

C0.08 0.15 0.22

D1.80 2.00 2.20

−−− −−− 0.043

0.000 −−− 0.004

0.006 0.008 0.010

0.003 0.006 0.009

0.070 0.078 0.086

MIN NOM MAX

INCHES

0.10 0.004

E1 1.15 1.25 1.35

e0.65 BSC

L0.26 0.36 0.46

2.00 2.10 2.20 0.045 0.049 0.053

0.026 BSC

0.010 0.014 0.018

0.078 0.082 0.086

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.65

0.66

DIMENSIONS: MILLIMETERS

0.30

PITCH

2.50

RECOMMENDED

TOP VIEW

SIDE VIEW END VIEW

bbb H

SEATING

PLANE

DET AIL A E

A2 0.70 0.90 1.00 0.027 0.035 0.039

L2 0.15 BSC 0.006 BSC

aaa 0.15 0.006

bbb 0.30 0.012

ccc 0.10 0.004

A-B D

aaa C

2X 3 TIPS

aaa H D

PLANE

DETAIL A

GAGE

ccc C

MUN5336DW1, NSBC115EPDXV6

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PACKAGE DIMENSIONS

SOT−563, 6 LEAD

CASE 463A

ISSUE G

DIM MIN NOM MAX

MILLIMETERS

A0.50 0.55 0.60

b0.17 0.22 0.27

D1.50 1.60 1.70

E1.10 1.20 1.30

e0.5 BSC

L0.10 0.20 0.30

1.50 1.60 1.70

0.020 0.021 0.023

0.007 0.009 0.011

0.059 0.062 0.066

0.043 0.047 0.051

0.02 BSC

0.004 0.008 0.012

0.059 0.062 0.066

MIN NOM MAX

INCHES

0.08 (0.003) X

b6 5 PL

−X−

−Y−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE MATERIAL.

12 3

1.35

0.0531

0.5

0.0197

ǒmm

inchesǓ

SCALE 20:1

0.5

0.0197

1.0

0.0394

0.45

0.0177

0.3

0.0118

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.08 0.12 0.18 0.003 0.005 0.007

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DTC115EP/D

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