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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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April 1st, 2010
Renesas Electronics Corporation
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April 1, 2003
To all our customers
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
* Typical parameter indicates the value for the
center of distribution, and not 100% tested.
1
DESCRIPTION
The M5M5W816TP is a family of low voltage 8-Mbit static
RAMs organized as 524288-words by 16-bit, fabricated by
Mitsubishi's high-performance 0.18µm CMOS technology.
The M5M5W816TP is suitable for memory applications
where a simple interfacing , battery operating and battery
backup are the important design objectives.
The M5M5W816TP is packaged in a 44pin thin small
outline mount device, with the outline of 400mil TSOP
TYPE(II). It gives the best solution for a compaction of
mounting area as well as flexibility of wiring pattern of
printed circuit boards.
FEATURES
- Single 2.7~3.6V power supply
- Small stand-by current: 0.1µA (2.0V, typ.)
- No clocks, No refresh
- Data retention supply voltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S#, BC1# and BC2#
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE# prevents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 44pin 400mil TSOP TYPE(II)
PIN CONFIGURATION
A0 ~ A18
DQ1 ~ DQ16
S#
W#
OE#
BC1#
Address input
Data input / output
Chip select input
Write control input
Output enable input
Lower Byte (DQ1 ~ 8)
Pin Function
Vcc
GND Power supply
Ground supply
BC2# Upper Byte (DQ9 ~ 16)
Outline: 44P3W
30mA
(10MHz)
5mA
(1MHz)
Version,
Operating
temperature Part name Power
Supply Access time
max.
Stand-by current
Ratings (max. @3.6V)
Active
current
*(3.0V typ.)
Icc1
70°C 85°C25°C
I-version
-40~+85°C M5M5W816TP -70HI
M5M5W816TP -85HI 85ns
2.7~3.6V 70ns
* Typ. (@ 3.0V) 40°C25°C 40°C
40208.05.0
1.00.5
44Pin 400mil TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ1
GND
S#
W#
A4
A3
A2
A1
A0
DQ2
DQ4
DQ3
VCC
DQ5
DQ6
DQ8
DQ7
32
31
30
29
28
27
26
25
24
23
36
35
34
33
41
40
39
38
37
44
43
42
OE#
GND
BC1#
BC2#
A
5
A
6
A
7
DQ16
DQ15
DQ14
DQ13
V
CC
DQ12
DQ11
DQ10
DQ9
A8
A
9
A10
A11
A17
A18
A16
A12
A13
A14
A15
M5M5W816TP -55HI 55ns
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
2
FUNCTION
The M5M5W816TP is organized as 524288-words by 16-
bit. These devices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1# , BC2# , S# , W# and
OE#. Each mode is summarized in the function table.
A write operation is executed whenever the low level W#
overlaps with the low level BC1# and/or BC2# and the low
level S#. The address(A0~A18) must be set up before the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W# at a high
level and OE# at a low level while BC1# and/or BC2# and
S# are in an active state(S#=L).
When setting BC1# at the high level and other pins are
in an active stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high level and other pins are in an active stage, lower-
byte are in a selectable mode and upper-byte are in a
non-selectable mode.
When setting BC1# and BC2# at a high level or S# at a high
level, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with other
chips and memory expansion by BC1#, BC2# and S#.
The power supply current is reduced as low as 0.1µA(25°C,
typical), and the memory data can be held at +2.0V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
BLOCK DIAGRAM
MEMORY ARRAY
524288 WORDS
x 16 BITS
CLOCK
GENERATOR
A0
A1
A17
A18
BC1#
W#
OE#
DQ
8
DQ
1
DQ
16
DQ
9
-
Vcc
GND
S#
FUNCTION TABLE
S#
Mode
W#
BC1# BC2# OE# DQ1~8 DQ9~16 Icc
L
L
L
L
L
L
L
X
L
L
High-Z High-Z
XLL HDin High-Z Active
HLHRead High-ZDout ActiveL
HLActive
HLActive
L
High-Z
High-Z ActiveHL
H
HHigh-Z
LDoutHL L Read Dout Active
LDinLL XWrite Din Active
HHigh-Z
HHHigh-Z High-Z
Non selection
HHX X Standby
Write
HL L Write Din ActiveX
LHRead High-Z ActiveLDout
HHigh-Z
X X High-Z
X X Non selection High-Z StandbyH
BC2#
(note) "H" and "L" in this table mean VIH or VIL, respectively .
"X" in this table should be "H"or "L".
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
3
ABSOLUTE MAXIMUM RATINGS
pF
10
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
CO
Symbol Parameter Limits
Conditions Units
µA
mA
mA
V
Icc1
Icc2
Icc4
VIH
VIL
IO
Icc3
VOH IOH= - 0.5mA
VOL IOL=2mA
IIVI =0 ~ Vcc
BC1# and BC2#=VIH or S#=VIH or OE#=VIH, VI/O=0 ~ Vcc
Vcc+0.2V
0.6
2.2
-0.2 *
2.4
2
0.4
±1
5030 ±1
15
MaxTypMin
DC ELECTRICAL CHARACTERISTICS
f= 10MHz
f= 1MHz
-
-
-
-
-
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
Storage temperature
V
mW
Conditions
Ta= 25 °C700
- 65 ~ +150
Ratings
Vcc
VI
VO
Pd
Ta
Tstg
-0.3* ~ +4.6
-0.3* ~ Vcc + 0.3 (max. 4.6V)
0 ~ Vcc
Symbol Parameter Units
- 40 ~ +85
With respect to GND
f= 10MHz
f= 1MHz
55030 155
-
With respect to GND
With respect to GND
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Active supply current
( AC,MOS level )
( AC,TTL level )
Active supply current
Stand by supply current
( AC,MOS level )
( AC,TTL level )
Stand by supply current Other inputs= 0 ~ Vcc
Note 1: Direction for current flowing into IC is indicated as positive (no mark).
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
CAPACITANCE
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Symbol Parameter Conditions Limits Max
Typ
Min Units
Input capacitance
Output capacitance
* -3.0V in case of AC (Pulse width < 30ns)
BC1# and BC2# < 0.2V, S# < 0.2V
other inputs < 0.2V or > Vcc-0.2V
Output - open (duty 100%)
BC1# and BC2#=VIL , S#=VIL
other pins =VIH or VIL
Output - open (duty 100%)
BC1# and BC2# = VIH or S# = VIH
* -1.0V in case of AC (Pulse width < 30ns)
10
°C
°C
µA
20
~ +70°C
~ +40°C
0.5
-
-
-
~ +85°C
~ +25°C -
1.0
5
8
-
-
40
(1)
S# > Vcc - 0.2V,
other inputs = 0 ~ Vcc
BC1# and BC2# > Vcc - 0.2V
S# < 0.2V
(2)
other inputs = 0 ~ Vcc
CAPACITANCE
DC ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
3
temperature
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
Input rise time and fall time
Reference level
Output loads
2.7~3.6V
VIH=2.4V, VIL=0.4V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
5ns
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
AC ELECTRICAL CHARACTERISTICS
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
Supply voltage
Input pulse
1TTL
CL
DQ
Fig.1 Output load
Including scope and
jig capacitance
tCR ns
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
ta(A)
10
35
ns
ns
ns
ns
ns
ns
ns
ns
ta(BC1)
ta(BC2)
tdis(BC1)
tdis(BC2)
ten
(BC1,2)
ns
ns
ns
ns
ns
70
70
70
70
25
25
25
25
5
5
10
70
4
tsu(A-WH)
tCW
tw(W)
tsu(A)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(BC1)
tsu(BC2)
25
25
70
55
0
65
5
5
65
65
65
35
0
0
Symbol Parameter
Read cycle time
Limits
Address access time
Chip select 1 access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S# high
Output disable time after BC1# high
MaxMin MaxMin Units
(2) READ CYCLE
Output disable time after BC2# high
Output disable time after OE# high
Output enable time after S# low
Output enable time after BC1#,BC2# low
Output enable time after OE# low
Data valid time after address
(3) WRITE CYCLE
MaxMin MaxMin
Limits
Units
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W#
Byte control 1 setup time
Byte control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W# low
Output disable time from OE# high
Output enable time from W# high
Output enable time from OE# low
Symbol Parameter
VOH=VOL=1.50V
10
45
85
85
85
85
30
30
30
30
5
5
10
85
85HI
70HI
85HI70HI
30
30
85
60
0
70
5
5
70
70
70
45
0
0
10
30
55
55
55
55
20
20
20
20
5
5
10
55 MaxMin55HI
20
20
55
45
0
50
5
5
50
50
50
30
0
0
MaxMin55HI
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
ten (W)
5
ta(A)
t
a(BC1)
tv (A)
tdis (BC1) or tdis (BC2)
ta (OE)
t
en (OE) tdis (OE)
tCR
th (D)tsu (D)
DQ1~16
tsu (BC1) or tsu(BC2)
ten
(OE)
tdis(OE)
tw
(W)
trec (W)
tsu
(A)
tdis (W)
tCW
ten (S)
W# = "H" level
A
0~18
DQ1~16
A0~18
OE#
OE#
W#
(4)TIMING DIAGRAMS
Read cycle
(Note3)
(Note3)
(Note3)
(Note3)
VALID DATA
Write cycle ( W# control mode )
DATA IN
STABLE
(Note3) (Note3)
ta(S)
tdis (S)
S#
(Note3) (Note3)
BC1#,BC2#
t
a(BC2)
or
ten (BC2)
ten (BC1)
t
su (A-WH)
S#
(Note3) (Note3)
tsu (S)
BC1#,BC2#
Read cycle
Write cycle
5
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
6
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S# low overlaps BC1# and/or BC2# low and W# low.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
Note 5: When the falling edge of W# is simultaneously or prior to the falling edge of BC1# and/or BC2# or the falling edge of
th (D)tsu (D)
DQ1~16
tsu (BC1) or
tsu (BC2) trec (W)
tsu
(A)
tCW
A
0~18
W#
Write cycle (BC# control mode)
DATA IN
STABLE
(Note3)(Note3)
(Note4)
(Note5)
(Note3)(Note3)
S#
S#, the outputs are maintained in the high impedance state.
BC1#,BC2#
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
th (D)tsu (D)
DQ1~16
tsu (S) trec (W)
tsu
(A)
tCW
A
0~18
W#
S#
Write cycle (S# control mode)
DATA IN
STABLE
(Note3)
(Note3)
(Note4)
(Note5)
(Note3)
(Note3)
BC1#, BC2#
7
M5M5W816TP - 55HI, 70HI, 85HI
2002.08.30 Ver. 6.1
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
8
tsu (PD)
trec (PD)
ns
ms
2.2V
tsu (PD) 2.7V2.7V trec (PD)
BC1# , BC2# > Vcc-0.2V
Vcc
V
2.0Vcc (PD)
VI (S)
Icc (PD)
2.2
BC1#
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Symbol Parameter Test conditions Limits
Min
Typ
Max Units
Power down supply voltage
Chip select input S#
Power down
supply current
(2) TIMING REQUIREMENTS
Symbol Parameter Test conditions Limits
Min
Typ
Max Units
Power down set up time
Power down recovery time
(3) TIMING DIAGRAM
BC# control mode
VI (BC)
Byte control input BC1# & BC2#
V
BC2#
tsu (PD) 2.7V2.7V trec (PD)
Vcc
S#
S# control mode
S# > Vcc-0.2V
0
5
µA
15
~ +70°C
~ +40°C0.1
-
-
-
~ +85°C
~ +25°C-0.2 1.5
3
-
-
30
(1)
S# > Vcc - 0.2V,
other inputs = 0 ~ Vcc
BC1# and BC2# >
Vcc - 0.2V
S# < 0.2V
(2)
other inputs = 0 ~ Vcc
Vcc=2.0V
2.2V
2.2V 2.2V
V
Note 7: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 2.0V, and not 100% tested.
On the BC# control mode, the level of S# must be fixed at S# > Vcc-0.2V or S# < 0.2V.
2.2V < Vcc(PD)
2.0V < Vcc(PD) < 2.2V Vcc(PD)
2.2
2.2V < Vcc(PD)
2.0V < Vcc(PD) < 2.2V Vcc(PD)
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric
Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs,
algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs
and algorithms represents information on products at the time of publication of these materials, and
are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or
an authorized Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various
means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data,
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the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake. Please
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
