© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 2
1Publication Order Number:
NIS5232/D
NIS5232 Series
+12 Volt Electronic Fuse
The NIS5232 is a cost effective, resettable fuse which can greatly
enhance the reliability of a hard drive or other circuit from both
catastrophic and shutdown failures.
It is designed to buffer the load device from excessive input voltage
which can damage sensitive circuits. It also includes an overvoltage
clamp circuit that limits the output voltage during transients but does
not shut the unit down, thereby allowing the load circuit to continue
operation.
Features
•Integrated Power Device
•Power Device Thermally Protected
•No External Current Shunt Required
•9 V to 18 V Input Range
•44 mW Typical
•Internal Charge Pump
•Internal Undervoltage Lockout Circuit
•Internal Overvoltage Clamp
•ESD Ratings: Human Body Model (HBM); 1500 V
Machine Model (MM); 200 V
•UL2367 Approved (UL File #E466553)
•These Devices are Pb−Free and are RoHS Compliant
Typical Applications
•Hard Drives
•Mother Board Power Management
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MARKING DIAGRAM
DFN10
CASE 485C
232
AYWG
G
1
232 = Latching Version
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
4.2 AMP, 12 VOLT
ELECTRONIC FUSE
Pin Function
1 GND
2 dv/dt
3 Enable/Fault
4 ILIMIT
5NC
6−10 SOURCE
11 (flag) VCC
See detailed ordering and shipping information in the ordering
information section on page 10 of this data sheet.
ORDERING INFORMATION
NIS5232 Series
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2
Figure 1. Block Diagram
ENABLE/
FAULT
SOURCE
ILIMIT
dv/dt
GND
VCC
Enable
Charge
Pump
Thermal
Shutdown
UVLO
Current
Limit
Voltage
Clamp
dv/dt
Control
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin Function Description
1 Ground Negative input voltage to the device. This is used as the internal reference for the IC.
2 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal
capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to this
pin to increase the ramp time. If an additional time delay is not required, this pin should be left open.
3 Enable/Fault The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the output
of the device by pulling it to ground using an open drain or open collector device. If a thermal fault
occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the
device is in thermal shutdown. It can also be connected to another device in this family to cause a
simultaneous shutdown during thermal events.
4 ILimit A resistor between this pin and the source pin sets the overload and short circuit current limit levels.
6−10 Source This pin is the source of the internal power FET and the output terminal of the fuse.
11 (belly pad) VCC Positive input voltage to the device.
MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage, operating, steady−state (VCC to GND, Note 1)
Transient (100 ms)
VIN −0.6 to 18
−0.6 to 25
V
Thermal Resistance, Junction−to−Air
0.1 in2 copper (Note 2)
0.5 in2 copper (Note 2)
4−layer board (Note 4)
qJA 160
95
50
°C/W
Thermal Resistance, Junction−to−Lead (Pin 1) qJL 27 °C/W
Thermal Resistance, Junction−to−Case qJC 20 °C/W
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Pmax 1.3
10.4
W
mW/°C
Operating Temperature Range (Note 3) TJ−40 to 150 °C
Nonoperating Temperature Range TJ−55 to 155 °C
Lead Temperature, Soldering (10 Sec) TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package.
2. 1 oz. copper, double−sided FR4.
3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the
maximum ratings for extended periods of time.
4. JESD51−7 4−layer board.
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ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 12 V, CL = 100 mF, dv/dt pin open, RLIMIT = 10 W, Tj = 25°C
unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
POWER FET
Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load) Tdly 220 ms
Kelvin ON Resistance (Note 5)
TJ = 140°C (Note 6)
RDSon 35 44
62
55 mW
Off State Output Voltage
(VCC = 18 Vdc, VGS = 0 Vdc, RL = R)
Voff 190 300 mV
Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 1 MHz) 250 pF
Continuous Current (TA = 25°C, 0.5 in2 copper) (Note 6)
(TA = 80°C, minimum copper)
ID
ID
4.2
2.5
A
THERMAL LATCH
Shutdown Temperature (Note 6) TSD 150 175 200 °C
UNDER/OVERVOLTAGE PROTECTION
Output Clamping Voltage (Overvoltage Protection) (VCC = 18 V) VClamp 14 15 16.2 V
Undervoltage Lockout (Turn on, voltage going high) VUVLO 7.7 8.5 9.3 V
UVLO Hysteresis VHyst −0.80 −V
CURRENT LIMIT
Kelvin Short Circuit Current Limit (RLimit = 15.4 W, Note 7) ILim−SS 2.75 3.44 4.25 A
Kelvin Overload Current Limit (RLimit = 15.4 W, Note 7) ILim−OL 4.6 A
dv/dt CIRCUIT
Output Voltage Ramp Time (Enable to VOUT = 11.7 V) tslew 0.5 0.9 1.8 ms
Maximum Capacitor Voltage Vmax VCC V
ENABLE/FAULT
Logic Level Low (Output Disabled) Vin−low 0.35 0.58 0.81 V
Logic Level Mid (Thermal Fault, Output Disabled) Vin−mid 0.82 1.4 1.95 V
Logic Level High (Output Enabled) Vin−high 1.96 2.64 3.30 V
High State Maximum Voltage Vin−max 3.40 4.30 5.2 V
Logic Low Sink Current (Venable = 0 V) Iin−low −17 −25 mA
Logic High Leakage Current for External Switch (Venable = 3.3 V) Iin−leak 1.0 mA
Maximum Fanout for Fault Signal (Total number of chips that can be
connected to this pin for simultaneous shutdown)
Fan 3.0 Units
TOTAL DEVICE
Bias Current (Operational) IBias 1. 8 2.5 mA
Bias Current (Shutdown) IBias 1.0 mA
Minimum Operating Voltage (Notes 6 and 8) Vmin 7.6 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse test: Pulse width 300 ms, duty cycle 2%.
6. Verified by design.
7. Refer to explanation of short circuit and overload conditions in application note AND8140.
8. Device will shut down prior to reaching this level based on actual UVLO trip point.
NIS5232 Series
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4
10
0
30
20
50
40
60
0.1 1 10 100 1000 10000 100000
POWER (W)
TIME (ms)
25_C
80_C
50_C
Figure 2. Power Dissipation vs. Thermal Trip Time
Figure 3. Application Circuit with Direct Current Sensing
LOAD
GND
ENABLE
+12 V
RS
NIS5232
SOURCE
VCC
ENABLE/
FAULT
ILIMIT
dv/dtGND
10
9
8
7
6
4
11
3
12
Figure 4. Application Circuit with Kelvin Current Sensing
LOAD
GND
ENABLE
+12 V
RS
NIS5232
SOURCE
VCC
ENABLE/
FAULT
ILIMIT
dv/dtGND
10
9
8
7
6
4
11
3
12
NIS5232 Series
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Figure 5. Common Thermal Shutdown
SOURCE
VCC
ENABLE/
FAULT
ILIMIT
dv/dt
GND
LOAD
ENABLE
RS
LOAD
SOURCE
VCC
ILIMIT
ENABLE/
FAULT
dv/dt GND
NIS5135 NIS5232
NIS5232 Series
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7.4
7.6
7.8
8
8.2
8.4
8.6
8.8
9
−50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C)
UVLO (V)
Figure 6. UVLO Turn−On
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
−50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 7. UVLO Hysteresis
HYST (V)
14.5
14.6
14.7
14.8
14.9
15
15.1
15.2
15.3
−50 −25 0 25 50 75 100 125 150
VOLTAGE (V)
TEMPERATURE (°C)
Figure 8. Output Clamping Voltage
0.85
0.9
0.95
1
1.05
−50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 9. Output Voltage dv/dt Rate
RAMP TIME (ms)
Figure 10. Input Transient Response
0
400
800
1200
1600
0.5 0.6 0.7 0.8
CURRENT (mA)
Figure 11. Body Diode Forward
Characteristics
FORWARD VOLTAGE (V)
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7
4
5
6
7
8
9
0 0.5 1 1.5 2
CURRENT (A)
Figure 12. Thermal Limit vs. Copper Area and
Ambient Temperature
COPPER AREA (in2)
−40°C
0°C
25°C
50°C
85°C
0.1
1
10
10 100 1000
CURRENT (A)
Rlimit (W)
Figure 13. Current Limit vs. Rsense for Direct
Current Sensing
OL
SC
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
−50 0 50 100 150
OL
SC
CURRENT (A)
TEMPERATURE (°C)
Figure 14. Direct Current Sensing Levels vs.
Temperature for 27 W Sense Resistor
0.1
1
10
1 10 100
CURRENT (A)
Rsense (W)
OL
SC
Figure 15. Current Limit vs. Rsense for Kelvin
Current Sensing
3
3.5
4
4.5
5
5.5
6
−40 −200 20406080100
CURRENT (A)
TEMPERATURE (°C)
OL
SC
Figure 16. Kelvin Current Sensing Levels vs.
Temperature for 15 W Sense Resistor
1
1.5
2
2.5
3
3.5
4
−40 −20 0 20 40 60 80 10
0
TEMPERATURE (°C)
OL
SC
Figure 17. Kelvin Current Sensing Levels vs.
Temperature for 33 W Sense Resistor
CURRENT (A)
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40
45
50
55
7.0 9.0 11 13 15
VCC (V)
Figure 18. On Resistance vs. VCC
ON RESISTANCE (mW)
APPLICATION INFORMATION
Basic Operation
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
voltage, output current and die temperature.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The dv/dt of the output voltage will be
controlled by the internal dv/dt circuit. The output voltage
will slew from 0 V to the rated output voltage in 2 ms, unless
additional capacitance is added to the dv/dt pin.
The device will remain on as long as the temperature does
not exceed the 175°C limit that is programmed into the chip.
The current limit circuit does not shut down the part but will
reduce the conductivity of the FET to maintain a constant
current at the internally set current limit level. The input
overvoltage clamp also does not shutdown the part, but will
limit the output voltage to 15 V in the event that the input
exceeds that level.
An internal charge pump provides bias for the gate voltage
of the internal n−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
between the input voltage (VCC) and ground.
Current Limit
The current limit circuit uses a SENSEFET along with a
reference and amplifier to control the peak current in the
device. The SENSEFET allows for a small fraction of the
load current to be measured, which has the advantage of
reducing the losses in the sense resistor as well as increasing
the value and decreasing the power rating of the sense
resistor. Sense resistors are typically in the tens of ohms
range with power ratings of several milliwatts making them
very inexpensive chip resistors.
The current limit circuit has two limiting values, one for
short circuit events which are defined as the mode of
operation in which the gate is high and the FET is fully
enhanced. The overload mode of operation occurs when the
device is actively limiting the current and the gate is at an
intermediate level. For a more detailed description of this
circuit please refer to application note AND8140.
There are two methods of biasing the current limit circuit
for this device. They are shown in the two application
figures. Direct current sensing connects the sense resistor
between the current limit pin and the load. This method
includes the bond wire resistance in the current limit circuit.
This resistance has an impact on the current limit levels for
a given resistor and may vary slightly depending on the
impedance between the sense resistor and the source pins.
The on resistance of the device will be slightly lower in this
configuration since all five source pins are connected in
parallel and therefore, the effective bond wire resistance is
one fifth of the resistance for any given pin.
The other method is Kelvin sensing. This method uses one
of the source pins as the connection for the current sense
resistor. This connection senses the voltage on the die and
therefore any bond wire resistance and external impedance
on the board have no effect on the current limit levels. In this
configuration the on resistance is slightly increased relative
to the direct sense method since only four of the source pins
are used for power.
Overvoltage Clamp
The overvoltage clamp consists of an amplifier and
reference. It monitors the output voltage and if the input
voltage exceeds 15 V, the gate drive of the main FET is
reduced to limit the output. This is intended to allow
operation through transients while protecting the load. If an
overvoltage condition exists for many seconds, the device
may overheat due to the voltage drop across the FET
combined with the load current. In this event, the thermal
protection circuit would shut down the device.
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Undervoltage Lockout
The undervoltage lockout circuit uses a comparator with
hysteresis to monitor the input voltage. If the input voltage
drops below the specified level, the output switch will be
switched to a high impedance state.
dv/dt Circuit
The dv/dt circuit brings the output voltage up under a
linear, controlled rate regardless of the load impedance
characteristics. An internal ramp generator creates a linear
ramp, and a control circuit forces the output voltage to
follow that ramp, scaled by a factor.
The default ramp time is approximately 2 ms. This can be
modified by adding an external capacitor at the dv/dt pin.
This pin includes an internal current source of
approximately 85 nA. Since the current level is very low, it
is important to use a ceramic cap or other low leakage
capacitor. Aluminum electrolytic capacitors are not
recommended for this circuit.
The ramp time from 0 to the nominal output voltage can
be determined by the following equation, where t is in
seconds:
t0*12 +24e6 @ǒ50 pF )CextǓ
Cext +
t0−12
24e6 *50 pF
Where:
C is in Farads
t is in seconds
Any time that the unit shuts down due to a fault, enable
shut−down, or recycling of input power, the timing capacitor
will be discharged and the output voltage will ramp from 0
at turn on.
Enable/Fault
The Enable/Fault pin is a multi−function, bidirectional pin
that can control the output of the chip as well as send
information to other devices regarding the state of the chip.
When this pin is low, the output of the fuse will be turned off.
When this pin is high the output of the fuse will be
turned−on. If a thermal fault occurs, this pin will be pulled
low to an intermediate level by an internal circuit.
To use as a simple enable pin, an open drain or open
collector device should be connected to this pin. Due to its
tri−state operation, it should not be connected to any type of
logic with an internal pullup device.
If the chip shuts down due to the die temperature reaching
its thermal limit, this pin will be pulled down to an
intermediate level. This signal can be monitored by an
external circuit to communicate that a thermal shutdown has
occurred. If this pin is tied to another device in this family
(NIS5232 or NIS5135), a thermal shutdown of one device
will cause both devices to disable their outputs. Both devices
will turn on once the fault is removed for the auto−retry
devices.
For the latching thermal device, the outputs will be
enabled after the enable pin has been pulled to ground with
an external switch and then allowed to go high or after the
input power has been recycled. For the auto retry devices,
both devices will restart as soon as the die temperature of the
device in shutdown has been reduced to the lower thermal
limit.
Thermal Protection
The NIS5232 includes an internal temperature sensing
circuit that senses the temperature on the die of the power
FET. If the temperature reaches 175°C, the device will shut
down, and remove power from the load. Output power can
be restored by either recycling the input power or toggling
the enable pin.
The thermal limit has been set high intentionally, to
increase the trip time during high power transient events. It
is not recommended to operate this device above 150°C for
extended periods of time.
Figure 19. Fault/Enable Signal Levels
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Figure 20. Enable/Fault Simplified Circuit
−
+
−
+
Startup
Blanking
Thermal
Shutdown
SD
1.4 V
Thermal Reset
Enable SD
2.64 V
Enable/Fault
4.3 V
Thermal SD
12 mA
0.58 V
ORDERING INFORMATION
Device Features Package Shipping†
NIS5232MN1TXG Thermal Latching DFN10
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE C
10X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
15
10 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
7. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
ÇÇÇ
ÇÇÇ
ÇÇÇ
B
A
0.15 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
REFERENCE
0.10 C
0.08 C
(A3)
C
10X
10X
0.10 C
0.05 C
A B
NOTE 3
K
10X
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 2.40 2.60
E3.00 BSC
E2 1.70 1.90
e0.50 BSC
L0.35 0.45
L1 0.00 0.03
DETAIL A K0.19 TYP
2X
2X
L1
DETAIL A
Bottom View
(Optional)
ÉÉÉ
ÉÉÉ
A1
A3
DETAIL B
Side View
(Optional)
EDGE OF PACKAGE
MOLD CMPD
EXPOSED Cu
DETAIL B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.1746
2.6016
1.8508
0.5000 PITCH
0.5651
10X
3.3048
0.3008
10X
DIMENSIONS: MILLIMETERS
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NIS5232/D
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