NCP1631DR2G - ON Semiconductor

April, 2010 − Rev. 2

1Publication Order Number:

NCP1631/D

NCP1631

Interleaved, 2-Phase Power

Factor Controller

The NCP1631 integrates a dual MOSFET driver for interleaved

PFC applications. Interleaving consists of paralleling two small

stages in lieu of a bigger one, more difficult to design. This approach

has several merits like the ease of implementation, the use of smaller

components or a better distribution of the heating.

Also, Interleaving extends the power range of Critical Conduction

Mode that is an efficient and cost−effective technique (no need for

low trr diodes). In addition, the NCP1631 drivers are 180° phase shift

for a significantly reduced current ripple.

Housed in a SOIC16 package, the circuit incorporates all the

features necessary for building robust and compact interleaved PFC

stages, with a minimum of external components.

General Features

•Near−Unity Power Factor

•Substantial 180° Phase Shift in All Conditions Including Transient

Phases

•Frequency Clamped Critical Conduction Mode (FCCrM) i.e.,

Fixed Frequency, Discontinuous Conduction Mode Operation with

Critical Conduction Achievable in Most Stressful Conditions

•FCCrM Operation Optimizes the PFC Stage Efficiency Over the

Load Range

•Out−of−phase Control for Low EMI and a Reduced rms Current in

the Bulk Capacitor

•Frequency Fold−back at Low Power to Further Improve the Light

Load Efficiency

•Accurate Zero Current Detection by Auxiliary Winding for Valley

Turn On

•Fast Line / Load Transient Compensation

•High Drive Capability: −500 mA / +800 mA

•Signal to Indicate that the PFC is Ready for Operation (“pfcOK”

Pin)

•VCC Range: from 10 V to 20 V

Safety Features

•Output Over and Under Voltage Protection

•Brown−Out Detection with a 50−ms Delay to Help

Meet Hold−up Time Specifications

•Soft−Start for Smooth Start−up Operation

•Programmable Adjustment of the Maximum Power

•Over Current Limitation

•Detection of Inrush Currents

Typical Applications

•Computer Power Supplies

•LCD / Plasma Flat Panels

•All Off Line Appliances Requiring Power Factor

Correction

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference

Manual, SOLDERRM/D.

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SOIC−16

D SUFFIX

CASE 751B

Device Package Shipping†

ORDERING INFORMATION

NCP1631DR2G SOIC−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

PIN ASSIGNMENT

(Top View)

ZCD1

REF5V/pfcOK

DRV1

GND

Vcc

DRV2

Latch

ZCD2

OSC

Vcontrol

FFOLD

OVP / UVP

MARKING DIAGRAM

NCP1631G

AWLYWWG

A = Assembly Location

WL = Wafer Lot

Y = Year

WW = Work Week

G = Pb−Free Package

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EMI

Filter

Ac lin e

Vin

LOAD

Vout

Cin

413

11 Vcc

pfcOK

Vout

Figure 1. Typical Application Schematic

Icoil2

Cbulk

Icoil1

L1Vaux2

Rzcd1

RCS

Rocp

OVPin

Iin

Rzcd2

Vaux2

Ccomp1

Cbo2

Rcomp1

Ccomp2

Cosc

RFF

Rbo2

Rbo1 Rovp1

Rovp2

OVPin

Rout1

Rout2

Table 1. MAXIMUM RATINGS TABLE

Symbol Rating Pin Value Unit

VCC(MAX) Maximum Power Supply Voltage Continuous 11 −0.3, +20 V

VMAX Maximum Input Voltage on Low Power Pins 1, 2, 3, 4, 6, 7,

8, 9, 10, 15,

and 16

−0.3, +9.0 V

VControl(MAX) VControl Pin Maximum Input Voltage 5 −0.3, VControl(clamp) (Note 1) V

RqJ−A

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation @ TA = 70°C

Thermal Resistance Junction−to−Air

550

145

°C/W

TJOperating Junction Temperature Range −40 to +125 °C

TJ(MAX) Maximum Junction Temperature 150 °C

TS(MAX) Storage Temperature Range −65 to +150 °C

TL(MAX) Lead Temperature (Soldering, 10s) 300 °C

ESD Capability, HBM model (Note 2) 3 kV

ESD Capability, Machine Model (Note 2) 250 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. “VControl(clamp)” is the pin5 clamp voltage.

2. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Machine Model Method 200 V per JEDEC Standard JESD22−A115−A

3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

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Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE

(Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V, TJ = −40°C to +125°C, unless otherwise specified)

Characteristics Test Conditions Symbol Min Typ Max Unit

STARTUP AND SUPPLY CIRCUITS

Supply Voltage

Startup Threshold

Minimum Operating Voltage

Hysteresis VCC(on) – VCC(off)

Internal Logic Reset

VCC increasing

VCC decreasing

VCC(on)

VCC(off)

VCC(hyst)

VCC(reset)

9.5

1.5

4.0

11.85

1.85

5.75

12.7

10.5

−

7.5

Startup current VCC = 9.4 V ICC(start) −35 100 mA

Supply Current

Device Enabled/No output load on pin6

Current that discharges VCC in latch mode

Current that discharges VCC in OFF

mode

Fsw = 130 kHz (Note 4)

VCC = 15 V, Vpin10 = 5 V

VCC = 15 V, pin 7 grounded

ICC1

ICC(latch)

ICC(off)

−

–

−

5.0

0.4

7.0

0.8

OSCILLATOR AND FREQUENCY FOLDBACK

Clamping Charging Current Pin 6 open IOSC(clamp) 31.5 35 38.5 mA

Charge Current with no frequency foldback Pin 6 grounded IOSC(CH1) 126 140 154 mA

Charge Current @ Ipin6 = 50 mA Ipin6 = 50 mA IOSC(CH2) 76.5 85 93.5 mA

Maximum Discharge Current

with no frequency foldback

Pin 6 grounded IOSC(DISCH1) 94.5 105 115.5 mA

Discharge Current @ Ipin6 = 50 mA Ipin6 = 50 mA IOSC(DISCH2) 45 50 55 mA

Voltage on pin 6 Ipin6 = 50 mA, Vpin5 = 2.5 V VFF 0.9 1.0 1.3 V

Oscillator Upper Threshold VOSC(high) −5−V

Oscillator Lower Threshold VOSC(low) 3.6 4.0 4.4 V

Oscillator Swing (Note 5) VOSC(swing) 0.93 0.98 1.03 V

CURRENT SENSE

Current Sense Voltage Offset Ipin9 = 100 mA

Ipin9 = 10 mA

VCS(TH100)

VCS(TH10)

−20

−10

Current Sense Protection Threshold Tj = 25°C

Tj = −40°C to 125°C

IILIM1

IILIM2

202

194

210

226

Threshold for In−rush Current Detection

(Note 5)

Iin−rush 11 14 17 mA

GATE DRIVE

Drive Resistance

DRV1 Sink

DRV1 Source

DRV2 Sink

DRV2 Source

Ipin14 = 100 mA

Ipin14 = −100 mA

Ipin11 = 100 mA

Ipin11 = −100 mA

RSNK1

RSRC1

RSNK2

RSRC2

–

Drive Current Capability (Note 5)

DRV1 Sink

DRV1 Source

DRV2 Sink

DRV2 Source

VDRV1 = 10 V

VDRV1 = 0 V

VDRV2 = 10 V

VDRV2 = 0 V

ISNK1

ISRC1

ISNK1

ISRC1

−

800

500

800

500

−

Rise Time

DRV1

DRV2

CDRV1 = 1 nF, VDRV1 = 1 to 10 V

CDRV2 = 1 nF, VDRV2 = 1 to 10 V

tr1

tr2

−

4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.

5. Not tested. Guaranteed by design and characterization.

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Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE

(Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V, TJ = −40°C to +125°C, unless otherwise specified)

Characteristics UnitMaxTypMinSymbolTest Conditions

GATE DRIVE

Fall Time

DRV1

DRV2

CDRV1 = 1 nF, VDRV1 = 10 to 1 V

CDRV2 = 1 nF, VDRV2 = 10 to 1 V

tf1

tf2

–

REGULATION BLOCK

Feedback Voltage Reference VREF 2.44 2.500 2.56 V

Error Amplifier Source Current Capability @ Vpin2 = 2.4 V IEA(SRC) −20 mA

Error Amplifier Sink Current Capability @ Vpin2 = 2.6 V IEA(SNK) +20

Error Amplifier Gain GEA 110 200 290 mS

Pin 5 Source Current when (Vout(low)

Detect) is activated

IControl(boost) 184 230 276 mA

Pin2 Bias Current Vpin2 = 2.5 V IFB(bias) −500 500 nA

Pin 5 Voltage: @ Vpin2 = 2.4 V

@ Vpin2 = 2.6 V

VControl(clamp)

VControl(MIN)

VControl(range)

−

2.7

3.6

0.6

−

3.3

Internal VREGUL Voltage

(measured on pin 6):

@ Vpin2 = 2.6 V, Ipin6 = 90 mA

@ Vpin2 = 2.4 V, Ipin6 = 90 mA

VREGUL(MIN)

VREGUL(Clamp)

−

1.66

0.1

−

Ratio (Vout(low) Detect Threshold / VREF)

(Note 5)

FB falling Vout(low)/VREF 95.0 95.5 96.0 %

Ratio (Vout(low) Detect Hysteresis /

VREF) (Note 5)

FB rising Hout(low)/VREF − − 0.5 %

SKIP MODE

Duty Cycle Vpin2 = 3 V DMIN − − 0 %

RAMP CONTROL (valid for the two phases)

Maximum DRV1 and DRV2 On−Time

(FB pin grounded)

TJ = −25°C to +125°C

Vpin7 = 1.1 V, Ipin3 = 50 mA

Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5)

Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5)

Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5)

ton1

ton2

ton3

ton4

14.5

1.10

4.00

0.35

19.5

1.35

5.00

0.41

22.5

1.60

6.00

0.48

Maximum DRV1 and DRV2 On−Time

(FB pin grounded)

TJ = −40°C to +125°C

Vpin7 = 1.1 V, Ipin3 = 50 mA

Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5)

Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5)

Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5)

ton1

ton2

ton3

ton4

14.0

1.05

3.84

0.33

19.5

1.35

5.00

0.41

22.5

1.60

6.00

0.48

Pin 3 voltage VBO = Vpin7 = 1.1 V, Ipin3 = 50 mA

VBO = Vpin7 = 1.1 V, Ipin3 = 200 mA

VBO = Vpin7 = 2.2 V, Ipin3 = 50 mA

VBO = Vpin7 = 2.2 V, Ipin3 = 200 mA

VRt1

VRt2

VRt3

VRt4

1.071

2.169

1.096

2.196

1.121

2.223

Maximum Vton Voltage Not tested Vton(MAX) 5 V

Pin 3 Current Capability IRt(MAX) 1− − mA

Pin 3 sourced current below which the

controller is OFF

IRt(off) 7mA

Pin 3 Current Range Not tested IRt(range) 20 1000 mA

ZERO VOLTAGE DETECTION CIRCUIT (valid for ZCD1 and ZCD2)

ZCD Threshold Voltage VZCD increasing

VZCD falling

VZCD(TH),H

VZCD(TH),L

0.40

0.20

0.50

0.25

0.60

0.30

ZCD Hysteresis VZCD decreasing VZCD(HYS) 0.25 V

4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.

5. Not tested. Guaranteed by design and characterization.

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Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE

(Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V, TJ = −40°C to +125°C, unless otherwise specified)

Characteristics UnitMaxTypMinSymbolTest Conditions

ZERO VOLTAGE DETECTION CIRCUIT (valid for ZCD1 and ZCD2)

Input Clamp Voltage

High State

Low State

Ipin1 = 5.0 mA

Ipin1 = −5.0 mA

VZCD(high)

VZCD(low)

−0.65

Internal Input Capacitance (Note 5) CZCD −10 −pF

ZCD Watchdog Delay tZCD 80 200 320 ms

BROWN−OUT DETECTION

Brown−Out Comparator Threshold VBO(TH) 0.97 1.00 1.03 V

Brown−Out Current Source IBO 6 7 8 mA

Brown−Out Blanking Time (Note 5) tBO(BLANK) 38 50 62 ms

Brown−Out Monitoring Window (Note 5) tBO(window) 38 50 62 ms

Pin 7 clamped voltage if VBO < VBO(TH)

during tBO(BLANK)

Ipin7 = −100 mA VBO(clamp) −965 −mV

Current Capability of the BO Clamp IBO(clamp) 100 − − mA

Hysteresis VBO(TH) – VBO(clamp) Ipin7 = − 100 mA VBO(HYS) 10 35 60 mV

Current Capability of the BO pin Clamp

PNP Transistor

IBO(PNP) 100 − − mA

Pin BO voltage when clamped by the PNP Ipin7 = − 100 mA VBO(PNP) 0.35 0.70 0.90 V

OVER AND UNDER VOLTAGE PROTECTIONS

Over−Voltage Protection Threshold VOVP 2.425 2.500 2.575 V

Ratio (VOVP / VREF) (Note 5) VOVP/VREF 99.2 99.7 100.2 %

Ratio UVP Threshold over VREF VUVP/VREF 8 12 16 %

Pin 8 Bias Current Vpin8 = 2.5 V

Vpin8 = 0.3 V

IOVP(bias) −500 −500 nA

LATCH INPUT

Pin Latch Threshold for Shutdown VLatch 2.375 2.500 2.625 V

Pin Latch Bias Current Vpin10 = 2.3 V ILatch(bias) −500 −500 nA

pfcOK / REF5V

Pin 15 Voltage Low State Vpin7 = 0 V, Ipin15 = 250 mA VREF5V(low) −60 120 mV

Pin 15 Voltage High State Vpin7 = 0 V, Ipin15 = 5 mA VREF5V(high) 4.7 4.85 5.3 V

Current Capability IREF5V 5 10 −mA

THERMAL SHUTDOWN

Thermal Shutdown Threshold TSHDN 130 140 150 °C

Thermal Shutdown Hysteresis TSHDN(HYS) −50 −°C

4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.

5. Not tested. Guaranteed by design and characterization.

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Table 3. DETAILED PIN DESCRIPTION

Pin Number Name Function

1 ZCD2 This is the zero current detection pin for phase 2 of the interleaved PFC stage. Apply the voltage

from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET

drain source voltage

2 FB This pin receives a portion of the pre−converter output voltage. This information is used for the reg-

ulation and the “output low” detection (VOUTL) that drastically speed−up the loop response when the

output voltage drops below 95.5% of the wished level.

3 RTThe resistor placed between pin 3 and ground adjusts the maximum on−time of our system for both

phases, and hence the maximum power that can be delivered by the PFC stage.

4 OSC Connect a capacitor to set the clamp frequency of the PFC stage. If wished, this frequency can be

reduced in light load as a function of the resistor placed between pin 6 and ground (frequency

fold−back). If the coil current cycle is longer than the selected switching period, the circuit delays

the next cycle until the core is reset. Hence, the PFC stage can operate in Critical Conduction Mode

in the most stressful conditions.

5 VControl The error amplifier output is available on this pin. The capacitor connected between this pin and

ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power

Factor ratios.

Pin5 is grounded when the circuit is off so that when it starts operation, the power increases slowly

(soft−start).

6Freq. Foldback Apply a resistor between pin 6 and ground to adjust the oscillator charge current. Clamped not to

exceed 100 mA, this charge current is made proportional to the power level for a reduced switching

frequency at light load and an optimum efficiency over the load range.

7 BO

(Brown−out

Protection)

Apply an averaged portion of the input voltage to detect brown−out conditions when Vpin2 drops

below 1 V. A 50−ms internal delay blanks short mains interruptions to help meet hold−up time re-

quirements. When it detects a brown−out condition, the circuit stops pulsing and grounds the

“pfcOK” pin to disable the downstream converter. Also an internal 7−mA current source is activated

to offer a programmable hysteresis.

The pin2 voltage is internally re−used for feed−forward.

Grounding pin 7 disables the part (after the 50−ms blanking time has elapsed).

8OVP / UVP The circuit turns off when Vpin9 goes below 480 mV (UVP) and disables the drive as long as the pin

voltage exceeds 2.5 V (OVP).

9 CS This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the

maximum coil current and protect the PFC stage in presence of in−rush currents.

10 Latch Apply a voltage higher than 2.5 V to latch−off the circuit. The device is reset by unplugging the PFC

stage (practically when the circuit detects a brown−out detection) or by forcing the circuit VCC below

VCCRST (4 V typically). Operation can then resume when the line is applied back.

11 DRV2 This is the gate drive pin for phase 2 of the interleaved PFC stage. The high current capability of the

totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power

MOSFETs.

12 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V and

turns off when VCC goes below 10 V (typical values). After start−up, the operating range is 9.5 V up

to 20 V.

13 GND Connect this pin to the pre−converter ground.

14 DRV1 This is the gate drive pin for phase 1 of the interleaved PFC stage. The high current capability of the

totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power

MOSFETs.

15 REF5V /

pfcOK

The pin15 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low

otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and

that hence, it can start operation.

16 ZCD1 This is the zero current detection pin for phase 1 of the interleaved PFC stage. Apply the voltage

from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET

drain source voltage.

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DRV1

VDD Regul Vcc

Outp ut

Buffer 1

Internal

TSD

OFF

UVLO

Vcontrol

Vton

processing

circuitry

Vton

ZCD2

GND

SHDN

OFF

OSC

Iref

−

Vovp = Vref

OVP

OFF

SHDN

−

Error Amplifier

Vref

−

0.955* Vref

Vout low

detect

FFOLD

Vcc

REF5V

OVP

OFF

OVLflag1

All the RS latches are

RESET dom inant

Stup

ZCD1

Latch

−

Vref

−

12% Vref

UVP

BO_NOK

Vcc_OK

pfcOK 230 mA

VDD

Vref

pfcOK

OVLflag1

Lstup

DRV1

Fault

management

OCP

In−rush

−

Ics

SKI P

( 0.6 V clamp vo ltage

is acti vated)

UVP

In−rush

Vcc < Vcc(reset)

Vcc(on)

Vcc(off)

OVP

DRV2

Outp ut

Buffer 2

Vcc

BO_NOK

Brown−out

50−ms delay

DRV2

L SHDN

OFF

SKIP

OCP STOP

Vpwm2

STOP

Vpwm1

STOP

CLK1

CLK2

CLK1

CLK2

Vpwm1

Vpwm2

DRV1 DRV2

DRV1

DRV2

pfcOK

IRt_low

In−rush

BO_NOK

Vcc_OK

pfcOK

Figure 2. Functional Block Diagram

pfcOK/

REF5V

VZCD1

VDMG1

VZCD2

VDMG2

VBO

Zero current

detection for

phase 1

Zero current

detection for

phase 2

VBOcomp

detection with

VBO

QZCD1

QZCD2

ICS > 210 mA

ICS > 14 mA

Current Sense Block

(Building of ICS

proportional to ICOIL)

IFF

VZCD1 VZCD2

ICH

Oscillator block

with interleaving and

frequency foldback

Lpwm1

Lpwm2

Thermal

Shutdown

±20 mA

IFF

VREGUL

IRt < 7 mA

VBOcomp

Generation of the oscillator

charge current IFF as a

function of VREGUL

(frequency fold−back)

Generation of the charge

current for the internal

timing capacitors (max

on−time setting for the

two phases)

On−time control

for the two

phases

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Detailed Operating Description

The NCP1631 integrates a dual MOSFET driver for

interleaved, 2−phase PFC applications. It drives the two

branches in so−called Frequency Clamped Critical

conduction Mode (FCCrM) where each phase operates in

Critical conduction Mode (CrM) in the most stressful

conditions and in Discontinuous Conduction Mode (DCM)

otherwise, acting as a CrM controller with a frequency

clamp (given by the oscillator). According to the

conditions, the PFC stage actually jumps from DCM to

CrM (and vice versa) with no discontinuity in operation and

without degradation of the current shape.

Furthermore, the circuit incorporates protection features

for a rugged operation together with some special circuitry

to lower the power consumed by the PFC stage in no−load

conditions. More generally, the NCP1631 is ideal in

systems where cost−effectiveness, reliability, low stand−by

power and high power factor are the key parameters:

Fully Stable FCCrM and Out−Of−Phase Operation.

Unlike master/slave controllers, the NCP1631 utilizes an

interactive−phase approach where the two branches

operate independently. Hence, the two phases necessarily

operate in FCCrM, preventing risks of undesired

dead−times or continuous conduction mode sequences. In

addition, the circuit makes them interact so that they run

out−of−phase. The NCP1631 unique interleaving

technique substantially maintains the wished 180° phase

shift between the 2 branches, in all conditions including

start−up, fault or transient sequences.

Optimized Efficiency Over The Full Power Range.

The NCP1631 optimizes the efficiency of your PFC

stage in the whole line/load range. Its clamp frequency is

a major contributor at nominal load. For medium and light

load, the clamp frequency linearly decays as a function of

the power to maintain high efficiency levels even in very

light load. The power threshold under which frequency

reduces is programmed by the resistor placed between pin

6 and ground. To prevent any risk of regulation loss at no

load, the circuit further skips cycles when the error

amplifier reaches its low clamp level.

Fast Line / Load Transient Compensation.

Characterized by the low bandwidth of their regulation

loop, PFC stages exhibit large over and under−shoots when

abrupt load or line transients occur (e.g. at start−up). The

NCP1631 dramatically narrows the output voltage range.

First, the controller dedicates one pin to set an accurate

Over−Voltage Protection level and interrupts the power

delivery as long as the output voltage exceeds this

threshold. Also, the NCP1631 dynamic response enhancer

drastically speeds−up the regulation loop when the output

voltage is 4.5% below its desired level. As a matter of fact,

a PFC stage provides the downstream converter with a very

narrow voltage range.

A “pfcOK” signal.

The circuit detects when the PFC stage is in steady state

or if on the contrary, it is in a start−up or fault condition. In

the first case, the “pfcOK” pin (pin15) is in high state and

low otherwise. This signal is to disable the downstream

converter unless the bulk capacitor is charged and no fault

is detected. Finally, the downstream converter can be

optimally designed for the narrow voltage provided by the

PFC stage in normal operation.

Safety Protections.

The NCP1631 permanently monitors the input and

output voltages, the input current and the die temperature

to protect the system from possible over−stresses and make

the PFC stage extremely robust and reliable. In addition to

the aforementioned OVP protection, one can list:

Maximum Current Limit: the circuit permanently

senses the total input current and prevents it

from exceeding the preset current limit, still

maintaining the out−of−phase operation.

In−rush Detection: the NCP1631 prevents the

power switches turn on for the large in−rush

currents sequence that occurs during the

start−up phase.

Under−Voltage Protection: this feature is mainly to

prevent operation in case of a failure in the

OVP monitoring network (e.g., bad

connection).

Brown−Out Detection: the circuit stops operating if

the line magnitude is too low to protect the

PFC stage from the excessive stress that could

damage it in such conditions.

Thermal Shutdown: the circuit stops pulsing when

its junction temperature exceeds 150°C

typically and resumes operation once it drops

below about 100°C (50°C hysteresis).

NCP1631 Operating Modes

The NCP1631 drives the two branches of the interleaved

in FCCrM where each phase operates in Critical

conduction Mode (CrM) in the most stressful conditions

and in Discontinuous Conduction Mode (DCM) otherwise,

acting as a CrM controller with a frequency clamp (given

by the oscillator). According to the conditions, the PFC

stage actually jumps from DCM to CrM (and vice versa)

with no discontinuity in operation and without degradation

of the current shape.

The circuit can also transition within an ac line cycle so

that:

•CrM reduces the current stress around the sinusoid top.

•DCM limits the frequency around the line zero

crossing.

This capability offers the best of each mode without the

drawbacks. The way the circuit modulates the MOSFET

on−time allows this facility.

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Figure 3. DCM and CRM Operation Within a Sinusoid Cycle for One Branch

NCP1631 On−time Modulation

Let’s study the ac line current absorbed by one phase of

the interleaved PFC converter.

The current waveform of the inductor (L) during one

switching period (Tsw) is portrayed by Figure 5.

The ac line current is the averaged value of the coil

current as the result of the EMI filter “polishing” action.

Hence, the line current produced by one of the phase is:

Iin +1

2ǒt1

LǓǒt1)t2

Tsw ǓVin (eq. 1)

Where (Tsw = t1 + t2 + t3) is the switching period and Vin

is the ac line rectified voltage.

Equation 1 shows that Iin is proportional to Vin if

ǒt1(t1)t2)

Tsw Ǔis a constant.

ǒt1(t1)t2)

Tsw Ǔ

Forcing

constant is what the NCP1631 does to perform FCCrM

operation that is, to operate in discontinuous or critical

conduction mode according to the conditions, without

degradation of the power factor.

Figure 4. Boost Converter

Figure 5. Inductor Current in DCM

The NCP1631 operates in voltage mode. As portrayed by

Figure 6, the MOSFET on time t1 is controlled by the signal

Vton generated by the regulation block as follows:

t1+CtVTON

(eq. 2)

Where:

•Ct is the internal timing capacitor

•It is the internal current source for the timing capacitor.

The It charge current is constant for a given resistor

placed on the Rt pin. Ct is also a constant. Hence, the

condition

ǒt1(t1)t2)

Tsw Ǔ

to be a constant for proper power factor correction can be

changed into:

ǒVTON(t1)t2)

Tsw Ǔis constant.

The output of the regulation block (VCONTROL) is

linearly changed into a signal (VREGUL) varying between

0 and 1.66 V. (VREGUL) is the voltage that is injected into

the PWM section to modulate the MOSFET duty−cycle.

However, the NCP1631 inserts some circuitry that

processes (VREGUL) to form the signal (VTON) that is used

in the PWM section instead of (VREGUL) (see Figure 7).

(VTON) is modulated in response to the dead−time sensed

during the precedent current cycles, that is, for a proper

shaping of the ac line current. This modulation leads to:

VTON +TswVREGUL

t1)t2

(eq. 3)

VTON

t1)t2

Tsw +VREGUL

or:

Substitution of Equation 3 into Equation 2 leads to the

following on−time expression:

t1+

CtǒTswVREGUL

t1)t2Ǔ

(eq. 4)

Replacing “t1” by its expression of Equation 4,

Equation 1 simplifies as follows:

Iin(phase1) +Iin(phase2) +Vin

CtVREGUL

(eq. 5)

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Given the regulation low bandwidth of the PFC systems,

(VCONTROL) and then (VREGUL) are slow varying signals.

Hence, the line current absorbed by each phase is:

Iin(phase1) +Iin(phase2) +kV

in (eq. 6)

k+constant +ƪCtVREGUL

2LI

tƫwhere:

Hence, the input current is then proportional to the input

voltage and the ac line current is properly shaped.

One can note that this analysis is also valid for CrM

operation that is just a particular case of this functioning

where (t3=0), which leads to (t1+t2=Tsw) and

(VTON=VREGUL). That is why the NCP1631 automatically

adapts to the conditions and jumps from DCM and CrM

(and vice versa) without power factor degradation and

without discontinuity in the power delivery.

The charging current It is internally processed to be

proportional to the square of the line magnitude. Its value

is however programmed by the pin 3 resistor to adjust the

available on−time as defined by the Ton1 to Ton4 parameters

of the data sheet.

From these data, we can deduce:

t1+Ton(ms) +50 n Rt2

Vpin7 2(eq. 7)

From this equation, we can check that if Vpin7 (BO

voltage) is 1 V and Rt is 20 kW (Ipin3 = 50 mA) that the

on−time is 20 ms as given by parameter Ton1.

Since:

Ton +CtVREGUL

VREGUL(max) +1.66 V

Vpin7 +22

ǸVin(rms)

pkBO

where kBO is the scale down factor of the BO sensing

network

ǒkBO +Rbo2

Rbo1 )Rbo2Ǔ

(see Brown−out section)

We can deduce the total input current value and the

average input power:

Iin(rms) ^(Rt)2VREGUL

26.9 @1012 Lk

BO 2Vin,rms

(eq. 8)

Pin,avg ^(Rt)2VREGUL

26.9 @1012 Lk

BO 2(eq. 9)

Figure 6. PWM Circuit and Timing Diagram Figure 7. VTON Processing Circuit

−

−> Vton d uring (t1+t2)

−> 0 V during t3 (dead−time)

−> Vton *(t1+t2)/T in average

Vton

−

timing capacitor

saw−too th

to PWM latch

PWM

comparator

IN1

R1 SKIP

OA1

OFF

S3 OVP

pfcOK

In−rus h

0.5*

(Ise nse

− 210 m)

OCP

The integrator OA1 amplifies the error between VREGUL and

IN1 so that in average, (VTON*(t1+t2)/Tsw) equates VREGUL.

VREGUL

VBOcomp

(from BO block)

(high during dead−time)

The “VTON processing circuit” is “informed” when there

is an OVP condition or a skip sequence, not to

over−dimension VTON in that conditions. Otherwise, an

OVP sequence or a skipped cycle would be viewed as a

“normal” dead−time phase by the circuit and VTON would

inappropriately increase to compensate it. (Refer to

Figure 7).

The output of the “VTON processing circuit” is also

grounded when the circuit is in OFF state to discharge the

capacitor C1 and initialize it for the next active phase.

Finally, the “VTON” is not allowed to be further increased

compared to VREGUL when the circuit has not completed

the start−up phase (pfcOK low) and if VBOcomp from the

brown−out block is high (refer to brown−out section for

more information).

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0,00

50,00

100,00

150,00

200,00

250,00

300,00

350,00

0 2 4 6 8 101214161820

time (ms)

Vin (V)

0,00

0,50

1,00

1,50

2,00

2,50

3,00

3,50

To n ( ms)

Vin

ton

Figure 8. Input Voltage and On−time vs. Time (example with FSW = 100 kHz, Pin = 150 W, VAC = 230 V, L = 200 mH)

Regulation Block and Low Output Voltage Detection

A trans−conductance error amplifier with access to the

inverting input and output is provided. It features a typical

trans−conductance gain of 200 mS and a typical capability

of ±20 mA. The output voltage of the PFC stage is typically

scaled down by a resistors divider and monitored by the

inverting input (feed−back pin – pin2). The bias current is

minimized (less than 500 nA) to allow the use of a high

impedance feed−back network. The output of the error

amplifier is pinned out for external loop compensation

(pin5). Typically a type−2 compensator is applied between

pin5 and ground, to set the regulation bandwidth below

20 Hz, as need in PFC applications (refer to application

note AND8407).

The swing of the error amplifier output is limited within

an accurate range:

•It is forced above a voltage drop (VF) by the “low

clamp” circuitry. When this circuitry is activated, the

power demand is minimum and the NCP1631 enters

skip mode (the controller stops pulsating) until the

clamp is no more active.

•It is clamped not to exceed 3.0 V + the same VF

voltage drop.

Hence, Vpin5 features a 3 V voltage swing. Vpin5 is then

offset down by (VF) and further divided before it connects

to the “Vton processing block” and the PWM section.

Finally, the output of the regulation is a signal (“VREGUL”

of the block diagram) that varies between 0 and 1.66 V.

Figure 9. Regulation Block

Vcontrol

OFF

−

Error Amp lifier

Vref

−

0.955*Vref

Vout low

detect

±20 mA

pfcOK 230 mA

VDD

OVLflag1

SKIP

Figure 10. Correspondence Between

VCONTROL and VREGUL

VREGUL

(0.6 V c lamp

voltage is activated)

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Provided the low bandwidth of the regulation loop, sharp

variations of the load, may result in excessive over and

under−shoots. Over−shoots are limited by the Over−

Voltage Protection (see OVP section). To contain the

under−shoots, an internal comparator monitors the

feed−back signal (Vpin2) and when Vpin2 is lower than

95.5% of its nominal value, it connects a 230 mA current

source to speed−up the charge of the compensation

capacitor (Cpin5). Finally, it is like if the comparator

multiplied the error amplifier gain by 10.

One must note that this circuitry for under−shoots

limitation, is not enabled during the start−up sequence of

the PFC stage but only once the converter has stabilized

(that is when the “pfcOK” signal of the block diagram, is

high). This is because, at the beginning of operation, the

pin5 capacitor must charge slowly and gradually for a soft

start−up.

Zero Current Detection

While the on time is constant, the core reset time varies

with the instantaneous input voltage. The NCP1631

determines the demagnetization completion by sensing the

inductor voltage, more specifically, by detecting when the

inductor voltage drops to zero.

Practically, an auxiliary winding in flyback

configuration is taken off of the boost inductor and gives a

scaled down version of the inductor voltage that is usable

by the controller (Figure 12). In that way, the ZCD voltage

(“VAUX”) falls and starts to ring around zero volts when the

inductor current drops to zero. The NCP1631 detects this

falling edge and allows the next driver on time.

Figure 1 shows how it is implemented.

For each phase, a comparator detects when the voltage

of the ZCD winding exceeds 0.5 V. When this is the case,

the coil is in demagnetization phase and the latch LZCD is

set. This latch is reset when the next driver pulse occurs.

Cbulk

DRV1

−

0.5 V

ZCD1

Vcc

output

buffer 1

200−ms

delay

Vin

ZCD2

D2 Vout

Cbulk

DRV2

Vcc

Vin

Vzcd2

−

0.5 V

Qzcd2

AND1

Vzcd1

SET1

SET2

In−rush

Figure 11. Zero Current Detection

Rzcd2

Rzcd1

Negative

and

positive

clamp

VDMG1

LZCD

Qzcd1

QZCD

VDMG2

OFF

(from Fault

management

block)

CLK2

(from phase

management

block)

CLK1

(from phase

management

block)

PWM

latch

PH1

PWM

latch PH2

reset signal

(from PH2 PWM comparator)

reset signal

(from PH1 PWM

comparator)

output

buffer 2

Negative

and

positive

clamp

To prevent negative voltages on the ZCD pins (ZCD1 for

phase 1 and ZCD2 for phase 2), these pins are internally

clamped to about 0 V when the voltage applied by the

corresponding ZCD winding is negative. Similarly, the

ZCD pins are clamped to VZCD(high) (10 V typical), when

the ZCD voltage rises too high. Because of these clamps,

a resistor (RZCD of Figure 11) is necessary to limit the

current from the ZCD winding to the ZCD pin. The clamps

are designed to respectively source and sink 5 mA

minimum. It is recommended not to exceed this 5 mA level

within the ZCD clamps for a proper operation.

At startup or after an inactive period (because of a

protection that has tripped for instance), there is no energy

in the ZCD winding and therefore no voltage signal to

activate the ZCD comparator. This means that the driver

will never turn on. To avoid this, an internal watchdog

timer is integrated into the controller. If the driver remains

low for more than 200 ms (typical), the timer sets the LZCD

latch as the ZCD winding signal would do. Obviously, this

200−ms delay acts as a minimum off−time if there is no

demagnetization winding while it has no action if there is

a ZCD voltage provided by the auxiliary winding.

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Figure 12. Zero Current Detection Timing Diagram

(VAUX is the Voltage Provided by the ZCD Winding)

Current Sense

The NCP1631 is designed to monitor a negative voltage

proportional to total input current, i.e., the current drawn by

the two interleaved branches (Iin). As portrayed by

Figure 13, a current sense resistor (RCS) is practically

inserted within the return path to generate a negative

voltage (VCS) proportional to Iin. The circuit uses VCS to

detect when Iin exceeds its maximum permissible level. To

do so, the circuit incorporates an operational amplifier that

sources the current necessary to maintain the CS pin

voltage null (refer to Figure 13). By inserting a resistor

ROCP between the CS pin and RCS, we adjust the current

that is sourced by the CS pin (ICS) as follows:

*[RCSICOIL])[ROCPICS]+0(eq. 10)

Which leads to:

ICS +RCS

ROCP

ICOIL (eq. 11)

In other words, the pin 9 current (ICS) is proportional to

the coil current.

A negative clamp protects the circuit from the possible

negative voltage that can be applied to the pin. This

protection is permanently active (even if the circuit off).

The clamp is designed to sustain 5 mA. It is recommended

not to sink more than 5 mA from the CS pin for a proper

operation.

Two functions use ICS: the over current protection and

the in−rush current detection.

Over−Current Protection (OCP)

If ICS exceeds IILIM1 (210 mA typical), an over−current

is detected and the on−time is decreased proportionally to

the difference between the sensed current IIN and the

210 mA OCP threshold.

The on−time reduction is done by injecting a current Ineg

in the negative input of the “VTON processing circuit”

OPAMP. (See Figure 7)

Ineg +0.5(ICS *210 m)(eq. 12)

This current is injected each time the OCP signal is high.

The maximum coil current is:

ICOIL(max) +ROCP

RCS

IILIM1 (eq. 13)

In−rush Current Detection

When the PFC stage is plugged to the mains, the bulk

capacitor is abruptly charged to the line voltage. The

charge current (named in−rush current) can be very huge

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depending on the presence or absence of an effective

in−rush limiting circuitry. If the MOSFET turns on during

this severe transient, it may be over−stressed and finally

damaged. That is why, the NCP1631 permanently monitors

the input current and delays the MOSFET turn on until the

in−rush current has vanished. This is the function of the ICS

comparison to the Iin−rush threshold (14 mA typical). When

ICS exceeds Iin−rush, the comparator output (“In−rush”) is

high and prevents the PWM latches from setting (see block

diagram). Hence, the two drivers cannot turn high and the

MOSFETs cannot switch on. This is to guarantee that the

MOSFETs remain off as long as if the input current exceeds

10% of its maximum value. This feature protects the

MOSFETs from the possible excessive stress it could suffer

from if it was allowed to turn on while a huge current

flowed through the coil as it can be the case at start−up or

during an over−load transient.

The propagation delay (ICS < Iin−rush) to (drive outputs

high) is in the range of few ms.

However when the circuit starts to operate, the NCP1631

disables this protection to avoid that the current produced

by one phase and sensed by the circuit prevents the other

branch from operating. Practically, some logic grounds the

In−rush protection output when it detects the presence of

current cycles with a zero current detection signal provided

by the auxiliary winding (Figure 13).

The CS block performs the over−current protection and the in−rush current detection.

Ac line

LOAD

OCP

In−rush

DRV2

Negative clamp

Curr ent

DRV1

DRV2

Figure 13. Current Sense Block

VIN IIN

CIN

EMI

Filter

ICS

RCS

The pin voltage

is maintained

to 0 V

ICS

ROCP

IIN

Mirror

ICS

(ICS is proportional to the coil current)

Vaux2

Vaux1

VOUT

CBULK

QZCD1

QZCD2

(from ZCD

block)

IILIM1 = 210 mA

Iin−rush = 14 mA

Over−Voltage Protection

While PFC circuits often use one single pin for both the

Over−Voltage Protection (OVP) and the feed−back, the

NCP1631 dedicates one specific pin for the under−voltage

and over−voltage protections. The NCP1631 configuration

allows the implementation of two separate feed−back

networks (see Figure 15):

1. One for regulation applied to pin 2.

2. Another one for the OVP function (pin 8).

Figure 14. Configuration with One Feed−back

Network for Both OVP and Regulation

413

OVP

Vout (bulk voltage)

Rout2

Rout1

Rout3

Figure 15. Configuration with Two

Separate Feed−back Networks

413

OVP

Vout (bulk voltage)

Rovp2

Rout1

Rout2

Rovp1

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The double feed−back configuration offers some

up−graded safety level as it protects the PFC stage even if

there is a failure of one of the two feed−back arrangements.

However, if wished, one single feed−back arrangement

is possible as portrayed by Figure 14. The regulation and

OVP blocks having the same reference voltage, the

resistance ratio Rout2 over Rout3 adjusts the OVP threshold.

More specifically,

The bulk regulation voltage (“Vout(nom)”) is:

Vout(nom) +Rout1 )Rout2 )Rout3

Rout2 )Rout3 @Vref (eq. 14)

The OVP level (“Vout(ovp)”) is:

Vout(ovp) +Rout1 )Rout2 )Rout3

Rout2 @Vref (eq. 15)

The ratio OVP level over regulation level is:

Vout(ovp)

Vout(nom) +1)Rout3

Rout2

(eq. 16)

For instance, (Vout(nom) = 105% x Vout(nom)) leads to:

(Rout3 = 5% x Rout2).

When the circuit detects that the output voltage exceeds

the OVP level, it maintains the power switch open to stop

the power delivery.

As mentioned previously, the “VTON processing circuit”

is “informed” when there is an OVP condition, not to

over−dimension VTON in that conditions. Otherwise, an

OVP sequence would be viewed as a dead−time phase by

the circuit and VTON would inappropriately increase to

compensate it (refer to Figure 7).

PfcOK / REF5V Signal

The NCP1631 can communicate with the downstream

converter. The signal “pfcOK/REF5V” is high (5 V) when

the PFC stage is in normal operation (its output voltage is

stabilized at the nominal level) and low otherwise.

More specifically, “pfcOK/REF5V” is low:

− During the PFC stage start−up, that is, as long as

the output voltage has not yet stabilized at the

right level. The start−up phase is detected by

the latch “LSTUP” of the block diagram in

Figure 2. “LSTUP” is set during each “off”

phase so that its output (“STUP“) is high when

the circuit enters an active phase. The latch is

reset when the error amplifier stops charging

its output capacitor, that is, when the output

voltage of the PFC stage has reached its

desired regulation level. At that moment,

“STUP” falls down to indicate the end of the

start−up phase.

− Any time, the circuit is off or a fault condition is

detected as described by the “Fault

management and OFF mode” section

Finally, “pfcOK/REF5V” is high when the PFC output

voltage is properly and safely regulated. “pfcOK/REF5V”

should be used to allow operation of the downstream

converter.

Oscillator Section – Phase Management

The oscillator generates the clock signal that dictates the

maximum switching frequency for the global system (fosc).

In other words, each of the two interleaved branches cannot

operate above the clamp frequency that is half the oscillator

frequency (fosc/2). The oscillator frequency (fosc) is

adjusted by the capacitor applied to pin 4. Typically, a

440 pF capacitor approximately leads to a 120−kHz

operating frequency, meaning a 60−kHz clamp frequency

for each branch. The oscillator frequency should be kept

below 500 kHz (which corresponds to a pin4 capacitor in

the range of 100 pF).

As shown by Figure 16, two current sources IOSC(clamp)

(35 mA typical) and IOSC(CH) (105 mA typical) charge the

pin 4 capacitor until its voltage exceeds VOSC(high) (5 V

typically). At that moment, the output of the COMP_OSC

comparator (“SYNC” of Figure 16) turns high and changes

the COMP_OSC reference threshold that drops from

VOSC(high) down to VOSC(low) (hysteresis). The system

enters a discharge phase where the ICH current source is

disabled and instead a sink current IOSC(DISCH) (105 mA

typ.) discharges the pin 4 capacitor. This sequence lasts

until Vpin4 goes below VOSC(low) when the “SYNC” signal

turns low and a new charging phase starts. A divider by two

uses the “SYNC” information to manage the phases of the

interleaved PFC: the first SYNC pulse sets “phase 1”, the

second one, “phase 2”, the third one phase 1 again... etc...

According to the selected phase, the “SYNC” signal sets

the relevant “Clock generator latch” that will generate the

clock signal (“CLK1” for phase 1, “CLK2” for phase 2)

when SYNC drops to zero (falling edge detector). So, the

drivers are synchronized to SYNC falling edge.

Actually, the drivers cannot turn on at this very moment

if the demagnetization of the coil is not yet complete (CrM

operation). In this case, the clock signal is maintained high

until the driver turns high (the clock generator latches are

reset by the corresponding driver is high − reset on rising

edge detector). Also, the discharge time can be prolonged

if when Vpin4 drops below VOSC(low), the driver of the

phase cannot turn on because the core is not reset yet (CrM

operation). In this case, Vpin4 decreases until the driver

turns high. The further discharge of Vpin4 below VOSC(low)

helps maintain a substantial 180° phase shift in CrM that is

in essence, guaranteed in DCM. In the two conditions (CrM

or DCM), operation is stable and robust.

Figure 17 portrays the clock signal waveforms in

different cases:

− In fixed frequency operation (DCM), the cycle

time of the coil current is shorter than an

oscillator period. Hence, as soon as the clock

signal goes high, the driver can turn on and

reset the clock generator latch. The clock

signal is then a short pulse.

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− However, the coil current can possibly be non

zero when the clock signal turns high. The

circuit would enter Continuous Conduction

Mode (CCM) if the MOSFET turned on in that

moment. In order to avoid CCM operation, the

clock is prevented from setting the PWM latch

until the core is reset (that is as low as “VZCD”

of Figure 8 is low). The clock signal remains

high during this waiting phase (refer to

Figure 12). Hence the next MOSFET

conduction time occurs as soon as the coil

current has totally vanished. In other words,

critical conduction mode (CrM) operation is

obtained.

The clamp frequency can be computed using the

following equation:

fosc ^60 m

COSC )10 p (eq. 17)

where COSC is the pin 4 external capacitor and Cpin the pin

4 parasitic capacitance (about 10 pF).

OSC

CLK1

Generation

latch

CLK1

DRV1

Comp_OSC

Current

CLK2

Generation

latch

CLK2

DRV2

divider

by two

Phase1

Phase2

SYNC

SYNCbar

Q_ph1

Q_ph2

Q_ph1

SYNCbar

pfcOK

FFOLD

Figure 16. Oscillator Block

RFF

IFF

VREGUL

IFF

Mirror

105 mA

VREGUL

Circuitry for

Frequency Foldback

COSC

IOSC(DISCH) = IFF

IOSC(CH) = IFF IOSC(clamp)

VOSC(high)/

VOSC(low)

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Figure 17. Typical Waveforms (Tdelay not shown here for the sake of simplicity)

Frequency Foldback

In addition, the circuit features the frequency fold−back

function to improve the light load efficiency. Practically,

the oscillator charge and discharge currents (IOSC(CH) and

IOSC(DISCH) of Figure 16) are not constant but dependent on

the power level. More specifically, IOSC(CH) and

IOSC(DISCH) linearly vary as a function of Vcontrol output of

the regulation block that thanks to the feed−forward

featured by the NCP1631, is representative of the load.

The practical implementation is portrayed by Figure 16.

“VREGUL” is the signal derived from Vcontrol that is

effectively used to modulate the MOSFET on−time.

VREGUL is buffered and applied to pin 6 (“Frequency

fold−back” pin). A resistor RFF is to be connected to pin 6

to sink a current proportional to VREGUL

ǒIpin6 +IFF +VREGUL

RFF Ǔ.

This current is clamped not to exceed 105 mA and copied

by a current mirror to form IOSC(CH) and IOSC(DISCH).

As a matter of fact, the oscillator charge current is:

IOSC(CH) +IOSC(clamp) )VREGUL

RFF (eq. 18)

if ǒVREGUL

RFF v105 mAǓ

IOSC(CH) +IOSC(clamp) )IOSC(CH1) +IOSC(CHT1) +140 mA otherwise

The oscillator charge current is then an increasing function of VREGUL and is clamped to 140 mA.

The oscillator discharge current is:

IOSC(DISCH) +VREGUL

RFF (eq. 19)

if ǒVREGUL

RFF v105 mAǓ

IOSC(DISCH) +IOSC(DISCH1) +105 mA otherwise

The oscillator discharge current is also an increasing

function of VREGUL and is clamped to105 mA.

As a consequence, the clamp frequency is also an

increasing function of VREGUL until it reaches a maximum

value for (IFF = 105 mA). If we consider the clamp

frequency fOSC computed by Equation 17 as the nominal

value obtained at full load and if we name it “fOSC(nom)”:

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fOSC +fOSC(nom)

(eq. 20)

if ǒVREGUL wRFF @105 mAǓ

fOSC +VREGUL(RFFIOSC(clamp) )VREGUL)

60 mRFF(RFFIOSC(clamp) )2VREGUL)@fOSC(nom) if ǒVREGUL vRFF @105 mAǓ

Let’s illustrate this operation on an example.

VREGUL is the control signal that varies between 0 and

1.66 V, (VREGUL = 1.66 V) corresponding to the maximum

power (Pin)HL that can virtually be delivered by the PFC

stage as selected by the timing resistor (for more details,

you can refer to the application note AND8407).

If one decides to start to reduce the clamp frequency

when the power goes below (Pin)HL/2, the oscillator charge

current should start to decrease when VREGUL is 0.83 V.

Hence, the pin 6 resistor (“RFF”) must be selected so that

pin 6 sources 105 mA when VREGUL equates 0.83 V:

RFF +0.83 V

105 mA+7.9 kW(eq. 21)

Let’s take (RFF = 8.2 kW) which is a normalized value.

This selection leads to:

fOSC +fOSC(nom)

(eq. 22)

if ǒVREGUL w8.2 k @105 m+860 mVǓ

fOSC +VREGUL(RFFIOSC(clamp) )VREGUL)

492 m(RFFIOSC(clamp) )2VREGUL)@fOSC(nom) if ǒVREGUL v860 mVǓ

For instance, if the nominal frequency (fOSC(nom)) is 120 kHz, the following characteristic is obtained.

Figure 18. Fold−back Characteristic of the Clamp Frequency with RFF = 8.2 kW and fOSC(nom) = 120 kHz

0 0.5 1 1.5

100

150

VREGUL (V)

Fosc (kHz)

fOSC(nom) = 120 kHz

If pin6 is grounded (accidently or not), the circuit operates

properly with a constant 140 mA oscillator charge current and

a 105 mA discharge current. The clamp frequency equates its

nominal value over the whole load range.

If pin6 is open, the oscillator charge current is equal to

IOSC(clamp) but the oscillator discharge current is null and

hence the PFC stage cannot operate.

A minimum discharge current and hence a minimum

clamp frequency can be forced by placing a resistor

between pin 4 and ground. For instance, a 1.5−MW resistor

forces a 3.3−mA discharge current when the oscillator

capacitor is fully charged and about 2.6 mA when it is near

the oscillator low threshold (4 V).

A transistor pulls the pin 6 down during startup to disable

the frequency fold−back function.

Skip Mode

The circuit features the frequency fold−back that leads to

a very efficient stand−by mode. In order to ensure a proper

regulation in no load conditions even if this feature is not

used (pin 6 grounded), the circuit skips cycles when the

error amplifier output is at its minimum level. The error

amplifier output is maintained between about 0.6 V and

3.6 V thanks to active clamps. A skip sequence occurs as

long as the 0.6 V clamp circuitry is triggered and switching

operation is recovered when the clamp is inactive.

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Brown−Out Protection

The brown−out pin receives a portion of the input voltage (VIN). As VIN is a rectified sinusoid, a capacitor must integrate

the ac line ripple so that a voltage proportional to the average value of (VIN) is applied to the brown−out pin.

Figure 19. Brown−out Block

EM I

Filter

Ac line

Cir c uitry for

brown−out detection

reset res et

BO_NO K

1 V

7 mA

Vdd 980 mV

Clamp

Current M irror

IRt_ low

This PNP transistor

maintains the BO pin

below the BO threshold

when the circuit is not fed

stateof the BO block

enough to control the

RCS Cbo

Cin

Vin

RRt

Rbo1

Rbo2

VBO

Feed−forward

circuitry

IRt

IRt < 7 mA

VBOcomp

Tdelay

50-ms

delay

50-ms

delay

LBO

This voltage

(“VBOcomp”) is

high when Vpin7

is below 1 V

The main function of the BO block is to detect too low

input voltage conditions. A 7−mA current source lowers the

BO pin voltage when a brown−out condition is detected.

This is for hysteresis purpose as required by this function.

In nominal operation, the voltage applied to pin7 must be

higher than the 1 V internal voltage reference. In this case,

the output of the comparator BO_Comp (VBOcomp) is low

(see Figure 19).

Conversely, if Vpin7 goes below 1 V, the BO_Comp

output turns high and a 965 mV voltage source is connected

to the BO pin to maintain the pin level near 1 V. Then, a

50−ms blanking delay is activated during which no fault is

detected. The main goal of the 50−ms lag is to help meet

the hold−up requirements. In case of a short mains

interruption, no fault is detected and hence, the “pfcOK”

signal remains high and does not disable the downstream

converter. In addition, pin7 being kept at 965 mV, there is

almost no extra delay between the line recovery and the

occurrence of a proper voltage applied to pin2, that

otherwise would exist because of the large capacitor

typically placed between pin7 and ground to filter the input

voltage ripple. As a result, the NCP1631 effectively

“blanks” any mains interruption that is shorter than 25 ms

(minimum guaranteed value of the 50−ms timer).

At the end of this 50−ms blanking delay, another timer is

activated that sets a 50−ms window during which a fault

can be detected. This is the role of the second 50−ms timer

of Figure 19:

•if the output of OPAMP is high at the end of the first

delay (50−ms blanking time) and before the second

50−ms delay time is elapsed, a brownout condition is

detected

•if the output of OPAMP remains low for the duration

of the second delay, no fault is detected.

When the “BO_NOK” signal is high:

− The drivers are disabled, the “Vcontrol” pin is

grounded to recover operation with a soft−start

when the fault has gone and the “pfcOK”

voltage turns low to disable the downstream

converter.

− The OPAMP output is separated from pin7

(Figure 19) to prevent the operational

amplifier from maintaining 1 V on pin7 (as

done by the switches s1 and s2 in the

representation of Figure 19). Instead, Vpin2

drops to the value that is externally forced (by

Vin, Rbo1, Rbo2 and Cbo2 in Figure 19). As a

consequence, the OPAMP output remains high

and the “BO_NOK” signal stays high until the

line recovers.

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− The 7−mA current source is enabled that lowers

the pin7 voltage for hysteresis purpose.

A short delay (Tdelay) is added to get sure that these three

actions are properly done before the PFC driver is disabled

and the “Vcontrol” and “pfcOK” pins are grounded.

At startup (and in UVLO situations that is when the Vcc

voltage is not sufficient for operation), a pnp transistor

ensures that the BO pin voltage remains below the 1 V

threshold until VCC reaches VCC(on). This is to guarantee

that the circuit starts operation in the right state, that is,

“BONOK” high. When VCC exceeds VCC(on), the pnp

transistor turns off and the circuit enables the 7−mA current

source (IBO).

Also, (IBO) is enabled whenever the part is in off−mode,

but at startup, IBO is disabled until VCC reaches VCC(on).

Brown−out Resistors Calculation

The BO resistors can be calculated with the following

equations (for more details, refer to the application note

AND8407)

Rbo1 +

(Vin,avg)boH *ȧ

Ȣ(Vin,avg)boL

Ȣ1*

fline

3fline

IHYST

(eq. 23)

Rbo2 +Rbo1

ǒ(Vin,avg)boL

VBO(th) ǒ1*fBO

3flineǓǓ*1

(eq. 24)

Feed−forward

As shown by Figure 19, The BO circuit also generates an

internal current proportional to the input voltage average

value (IRt). The pin7 voltage is buffered and made available

on pin 3. Placing a resistor between pin 3 and ground,

enables to adjust a current proportional to the average input

voltage. This current (IRt) is internally copied and squared

to form the charge current for the timing capacitor of each

phase. Since this current is proportional to the square of the

line magnitude, the conduction time is made inversely

proportional to the line magnitude. This feed−forward

feature makes the transfer function and the power delivery

independent of the ac line level. Only the regulation output

(VREGUL) controls the power amount. If the IRt current is

too low ( below 7 mA), the controller goes in OFF mode to

avoid damaging the MOSFETs with too long conduction

time.

Thermal Shutdown (TSD)

An internal thermal circuitry disables the circuit gate

drive and then keeps the power switch off when the junction

temperature exceeds 140°C typically. The output stage is

then enabled once the temperature drops below about 80°C

(60°C hysteresis).

The temperature shutdown keeps active as long as the

circuit is not reset, that is, as long as VCC keeps higher than

VCCRESET. The reset action forces the TSD threshold to

be the upper one (140°C). This ensures that any cold

start−up will be done with the right TSD level.

Under−Voltage Lockout Section

The NCP1631 incorporates an Under−Voltage Lockout

block to prevent the circuit from operating when the power

supply is not high enough to ensure a proper operation. An

UVLO comparator monitors the pin 12 voltage (VCC) to

allow the NCP1631 operation when VCC exceeds 12 V

typically. The comparator incorporates some hysteresis

(2.0 V typically) to prevent erratic operation as the VCC

crosses the threshold. When VCC goes below the UVLO

comparator lower threshold, the circuit turns off.

The circuit off state consumption is very low: < 50 mA.

This low consumption enables to use resistors to charge

the VCC capacitor during the start−up without the penalty

of a too high dissipation.

Output Drive Section

The circuit embeds two drivers to control the two

interleaved branches. Each output stage contains a totem

pole optimized to minimize the cross conduction current

during high frequency operation. The gate drive is kept in

a sinking mode whenever the Under−Voltage Lockout

(UVLO) is active or more generally whenever the circuit

is off. Its high current capability (−500 mA/+800 mA)

allows it to effectively drive high gate charge power

MOSFET.

Reference Section

The circuit features an accurate internal reference

voltage (VREF). VREF is optimized to be ±2.4% accurate

over the temperature range (the typical value is 2.5 V).

VREF is the voltage reference used for the regulation and

the over−voltage protection. The circuit also incorporates

a precise current reference (IREF) that allows the

Over−Current Limitation to feature a ±6% accuracy over

the temperature range.

Fault Management and OFF Mode

The circuit detects a fault if the Rt pin is open (Figure 20).

Practically, if the pin sources less than 7 mA, the “IRt_Low”

signal sets a latch that turns off the circuit if its output

(Rt(open)) is high. A 30−ms blanking time avoids parasitic

fault detections. The latch is reset when the circuit is in

UVLO state (too low VCC levels for proper operation).

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VDD

Regul

Vcc

Internal

Thermal

Shutdown

TSD

OFF

UVLO

Stdwn Iref

Vcc_OK

Vref

Fault

management

UVP

12 V / 10 V

BO_NOK

Rt(open)

Figure 20. Fault Management Block

IRt_Low

(Ipin3 < 7 mA)

30−ms

blanking

time

When any of the following faults is detected:

−brown−out (“BO_NOK”)

−Under−Voltage Protection (“UVP”)

−Latch−off condition (“Stdwn”)

−Die over−temperature (“TSD”)

−Too low current sourced by the Rt pin (“Rt(open)”)

−“UVLO” (improper Vcc level for operation)

The circuit turns off. In this mode, the controller stops

operating. The major part of the circuit sleeps and its

consumption is minimized (< 500 mA). More specifically,

when the circuit is in OFF state:

−The two drive outputs are kept low

−The 7−mA current source of the brown−out block is

enabled to set the proper start−up BO threshold if Vcc

is high enough for proper operation. If not, the

brown-out pin is pulled down by a pnp transistor for a

proper input voltage sensing when the circuit recovers

operation (see brown-out section).

−The pin5 capacitor (Vcontrol) is discharged and kept

grounded along the OFF time, to initialize it for the

next operating sequence, where it must be slowly and

gradually charged to offer some soft−start.

−The “pfcOK” pin is grounded.

−The output of the “VTON processing block” is

grounded

When the circuit recovers after a fault, the first watchdog

time is around 20 ms instead of 200 ms to allow a faster

re−start.

In OFF mode at startup, the consumption is very low (<

50 mA). The brown−out block is initialized not to allow

operation (“BO_NOK” high) by default. The PNP clamp is

active and maintains the BO pin level below 1 V. The 7−mA

current source is enabled only when VCC reaches VCC(on)

threshold.

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Figure 21. Start−up and Brown Out Conditions

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PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

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NCP1631/D

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