FTLF8536P4BCV Product Specification
Finisar Corporation - Apr 2017 Rev B3 Finisar Confidential Page 7
VIII. Digital Diagnostic Functions
Finisar FTLF8536P4BCV SFP+ transceivers support the 2-wire serial communication protocol as
defined in the SFP MSA
f
. It is very closely related to the E
2
PROM defined in the GBIC standard, with
the same electrical specifications.
The standard SFP serial ID provides access to identification information that describes the
transceiver’s capabilities, standard interfaces, manufacturer, and other information.
Additionally, Finisar SFP transceivers provide a enhanced digital diagnostic monitoring interface,
which allows real-time access to device operating parameters such as transceiver temperature, laser
bias current, transmitted optica l power, received optical power and transc eiver supply voltage. It also
defines a sophisticated system of alarm and warning flags, which alerts end-users when particular
operating parameters are outside of a factory set normal range.
The SFP MSA defines a 256-byte memory map in E
2
PROM that is accessible over a
2-wire serial interface at the 8 bit address 1010000X (A0h). The digital diagnostic monitoring interface
makes use of the 8 bit address 1010001X (A2h), so the originally defined serial ID memory map
remains unchanged. The interface is identical to, and is thus fully backward compatible with both the
GBIC Specification and the SFP Multi Source Agreement. The complete interface is described in
Finisar Application Note AN-2030: “Digital Diagnostics Monitoring Interface for SFP Optical
Transceivers”.
The operating and diagnostics information is monitored and reported by a Digital Diagnostics
Transceiver Controller (DDTC) inside the transceiver, which is accessed through a 2-wire serial
interface. When the serial protocol is activated, the serial clock si gnal (SCL, Mod Def 1) is generated
by the host. The positive edge clocks data into the SFP transceiver into those segments of the E
2
PROM
that are not write-protected. The negative edge clocks data from the SFP transceiver. The serial data
signal (SDA, Mod Def 2) is bi-directional for serial data transfer. The host uses SDA in conjunction
with SCL to mark the start and end of serial protocol activation. The memories are organized as a
series of 8-bit data words that can be addressed individually or sequentially.
For more information, please see the SFP MSA documentation
c,f
and Finisar Application Note AN-
2030.
TX Equalization Control @ 25G
Tx input equalization control can be accessed through 2-wire serial interface at by te address
114 (A2h). Tx input equalization control for 25GE is located at the upper 4 bits of byte 114
(A2h) while the lower 4 bits are reserved for rate low in the case of dual rate application.
RX Emphasis Control @ 25G
Rx output emphasis control can be accessed through 2-wire serial interface at byte address 115
(A2h). Rx output emphasis control for 25GE is located at the upper 4 bits of byte 115 (A2h)
while the lower 4 bits are reserved for rate low in the case of dual rate application.