IRF3710ZS - International Rectifier

08/29/03

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HEXFET® is a registered trademark of International Rectifier.

IRF3710Z

IRF3710ZS

IRF3710ZL

HEXFET® Power MOSFET

VDSS = 100V

RDS(on) = 18mΩ

ID = 59A

Features

OAdvanced Process Technology

OUltra Low On-Resistance

ODynamic dv/dt Rating

O175°C Operating Temperature

OFast Switching

ORepetitive Avalanche Allowed up to Tjmax

AUTOMOTIVE MOSFET

Description

Specifically designed for Automotive applications,

this HEXFET® Power MOSFET utilizes the latest

processing techniques to achieve extremely low

on-resistance per silicon area. Additional fea-

tures of this design are a 175°C junction operating

temperature, fast switching speed and improved

repetitive avalanche rating . These features com-

bine to make this design an extremely efficient

and reliable device for use in Automotive applica-

tions and a wide variety of other applications. D2Pak

IRF3710ZS

TO-220AB

IRF3710Z TO-262

IRF3710ZL

Absolute Maximum RatingsParameter Units

ID @ TC = 25 °C Co ntin uo us D r ai n C ur rent , V GS @ 10V ( Sili c on L i m i t e d) A

ID @ TC = 10 0°C Co ntin uo us D r ai n C ur rent , V GS @ 10V ( Se e Fig. 9)

IDM Pulsed Dr ain Current

PD @TC = 25°C Maximum Power D issi pation W

Linear D er ating Factor W/°C

VGS Gat e- to-S ource Vo ltage V

EAS Single Pul se Avalanche Ener gy (Thermally Limit ed)

EAS (tested) Sin

le Pul se Avalanche Ener

Tes ted Valu e

IAR Avalanche Current

EAR Re peti tive A v a l a nc he En er

TJ Operating Junc ti on and °C

TSTG Stor ag e Tempe r ature Range

Soldering Temperature, for 10 seconds

Mo unti ng t or que, 6-32 or M3 scr ew

Thermal Resistance Parameter Typ. Max. Units

RθJC Junction-to-Case ––– 0.92 °C/W

RθCS Ca s e- to-S ink, Flat , G r ea s ed Surf ac e 0.50 –––

RθJA Junction-to-Ambient ––– 62

RθJA Junction-to-Ambient (PCB Mount, steady state)

––– 40

Max.

240

10 lbf• in (1.1 N•m)

160

1.1

± 20

170

200

See Fig.12a,12b,15,16

300 ( 1.6mm f rom ca s e )

-5 5 to + 175

PD - 94632A

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Notes:

Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by TJmax, starting TJ = 25°C, L = 0.27mH,

RG = 25Ω, IAS = 35A, VGS =10V. Part not

recommended for use above this value.

ISD ≤ 35A, di/dt ≤ 380A/µs, VDD ≤ V(BR)DSS,

TJ ≤ 175°C.

Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

Coss eff. is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS .

Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

This value determined from sample failure population. 100%

tested to this value in production.

This is applied to D2Pak, when mounted on 1" square PCB

( FR-4 or G-10 Material ). For recommended footprint and

soldering techniques refer to application note #AN-994.

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. T

p. Max. Units

V(BR)DSS D r ai n- to-Sour c e Br e akdow n V ol t a

e 100 ––– ––– V

∆ΒVDSS

∆TJ Br eakdo wn Volta

e Temp. Coefficient ––– 0.10 ––– V/°C

RDS(on) Static Dr ain-t o- Sour c e O n- Resistance ––– 14 18 mΩ

VGS(th) G at e Threshold V o lta

e 2.0 ––– 4.0 V

fs For war d Tr ansconductance 35 ––– ––– S

IDSS Dr ai n- to-S ourc e Le aka

e Cur r ent ––– –– – 20 µ A

––– ––– 250

IGSS Gate-to-Source Forward Leaka

e ––– ––– 200 nA

Gate-t o- Sour c e R ev ers e Le ak a

e ––– ––– -200

QgTotal Gate Char

e ––– 82 120 nC

Qgs Gate-to-Source Char

e ––– 19 28

Qgd Gate-to-D r ain ("M iller " ) C har

e ––– 27 40

td(on) Turn-On Dela

Time ––– 17 ––– ns

trRise Time ––– 77 –– –

td(off) Turn-Off Del a

Ti m e ––– 41 –––

tfFall Time ––– 56 –––

LDInternal Drain Inductance ––– 4.5 ––– nH Between lead,

6mm (0.25in.)

LSInt er nal Sou rce Indu ctance ––– 7.5 ––– fr om packa

and center of die contact

Ciss Input Capacitance ––– 2900 ––– pF

Coss Output Capacitance ––– 290 –––

Crss Reve rse Tra ns fer Cap acit a nc e ––– 150 –––

Coss Output Capacitance ––– 1130 –––

Coss Output Capacitance ––– 170 –––

Coss eff. Ef f e c t ive O utput Capacita nc e – –– 280 –––

Diode Charac teristics

Par a meter Min. T

p. Max. Units

ISContin uous Source Cu r rent ––– ––– 59

(Body Diode) A

ISM Pulsed Source Current ––– ––– 240

(Body Diode)

c

VSD Diode Forward Vol tage ––– ––– 1.3 V

trr Reverse Recovery Time –––5075ns

Qrr Reverse Recover

Char

e ––– 100 160 nC

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Conditions

VGS = 0V, ID = 250µA

Refere nc e to 25 °C , ID = 1m A

VGS = 10V, ID = 35A

VDS = VGS, ID = 250µ A

VDS = 100V, VGS = 0V

VDS = 100V, VGS = 0V, TJ = 125°C

RG = 6.8Ω

ID = 35A

VDS = 50V , I D = 35A

VDD = 50V

ID = 35A

VGS = 20V

VGS = -20V

TJ = 25°C, IF = 35 A , V DD = 25V

di/d t = 100A /µ s

TJ = 25°C, IS = 35A, VGS = 0V

showing the

integra l revers e

p-n junct ion diode.

MOSFET symbol

VGS = 0V

VDS = 25V

VGS = 0 V, VDS = 80V , ƒ = 1.0MHz

Conditions

VGS = 0V, VDS = 0V to 80V

VDS = 80V

VGS = 10V

ƒ = 1. 0M Hz, See F ig . 5

VGS = 0 V, VDS = 1.0V, ƒ = 1.0MHz

VGS = 10V

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Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

vs. Drain Current

0.1 110 100

VDS, D rain- to-S ource Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

4.5V

20µs PU LSE WIDTH

Tj = 175°C

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

0.1 110 100

VDS, D rain- to-S ource Voltage (V)

0.01

0.1

100

1000

ID, Drain-to-Source Current (A)

4.5V

20µs PU LSE WIDTH

Tj = 25°C

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

2 4 6 8 10

VGS, Gate-to- Source V oltage ( V)

100

1000

ID, Drain-to-Source Current (Α)

TJ = 25°C

TJ = 175°C

VDS = 25V

20µs PU LSE WIDTH

010 20 30 40 50 60 70

ID, Drai n-to- Source Current (A)

100

120

GFS, Forward Transconductance (S)

TJ = 25°C

TJ = 175°C

VDS = 15V

20µs PU LSE WIDTH

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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100

VDS, Drain-t o-Source Voltage (V )

100

1000

10000

100000

C, Capacitance(pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, Cds SHORTED

Crss = Cgd

Coss = Cds + Cgd

0 20406080100

QG Total Gate Charge (nC)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

VGS, Gate-to-Source Voltage (V)

VDS= 80V

VDS= 50V

VDS= 20V

ID= 35A

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

VSD, Source-to-D rain V oltage (V)

0.10

1.00

10.00

100.00

1000.00

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

1 10 100 1000

VDS , Dr ain-t oSource V oltage (V)

0.1

100

1000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMI TED BY R

DS(on)

100µsec

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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current vs.

Case Temperature Fig 10. Normalized On-Resistance

vs. Temperature

25 50 75 100 125 150 175

T C , C ase Temperature (°C)

ID, Drain Current (A)

1E-006 1E-005 0.0001 0.001 0.01 0.1 1

t1 , Rectangular P ulse Durati on (sec)

0.001

0.01

0.1

Thermal Response ( Z thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Tem peratur e (°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 59A

VGS = 10V

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QGS QGD

Charge

D.U.T. V

3mA

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 14. Threshold Voltage vs. Temperature

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

100

150

200

250

300

EAS , Single Pulse Avalanche Energy (mJ)

TOP 1 5 A

25A

BOTTOM35A

-75 -50 -25 025 50 75 100 125 150 175 200

TJ , T em peratur e ( °C )

1.0

2.0

3.0

4.0

5.0

VGS(th) Gate threshold Voltage (V)

ID = 250µA

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Fig 15. Typical Avalanche Current vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T jmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current .

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV· Zth]

EAS (AR) = PD (ave)·tav

1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

0.1

100

1000

Avalanche Current (A)

0.05

Dut y Cycle = Single P ulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses

0.01

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

100

150

200

EAR , Avalanche Energy (mJ)

TOP Sin g le Pulse

BOTTOM 10% Duty Cycle

ID = 35A

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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P.W.

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



VDS

90%

10%

VGS t

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

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L EAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

- B -

1.32 ( .052)

1.22 ( .048)

3X 0.55 ( .022)

0.46 ( .018)

2.92 ( .115)

2.64 ( .104)

4.69 (.185)

4.20 (.165)

3X 0.93 (.037)

0.69 (.027)

4.06 (.160)

3.55 (.140)

1.15 ( .045)

MIN

6.47 (.255)

6.10 (.240)

3.78 (.149)

3.54 (.139)

- A -

10.54 (.415)

10.29 (.405)

2.87 (.113)

2.62 (.103)

15.24 (.600)

14.84 (.584)

14.0 9 (.555)

13.4 7 (.530)

3X 1.40 (.055)

1.15 (.045)

2.54 ( .100)

0.36 (.014) M B A M

1 2 3

NOTES:

1 DIM ENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.

2 CONTROLLING DI MEN SION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

TO-220AB Part Marking Information

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

PART NUMBER

INTERNATIONAL

RECTIFIER

LOGO

EXAMPLE : THIS IS AN IRF1010

WITH ASSEMBLY

LOT CODE 9B1M

ASSEMBLY

LOT CODE

DATE CODE

(YYWW)

YY = YEAR

WW = WEEK

9246

IRF1010

9B 1M

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D2Pak Part Marking Information

F530S

T HIS IS AN IRF 530S WIT H

LOT CODE 8024

AS S E MBLED ON WW 02, 2000

IN THE ASS EMBLY LINE "L"

AS S E MB L Y

LOT CODE

INT ERNAT IONAL

RECTIFIER

LOGO

PART NUMB ER

DAT E CODE

YEAR 0 = 2000

WE E K 02

LINE L

D2Pak Package Outline

Dimensions are shown in millimeters (inches)

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TO-262 Package Outline

Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information

EXA

PLE:THIS IS A

N IRL3103L

LOT C

DE 1789

SSEM

BLY

RT NUMBER

TE C

ODE

EEK 19

LINE C

T C

ODE

YEA

R 7 = 1997

SSEM

BLED O

N WW

19, 1997

IN THE A

SSEM

BLY LINE "C

"LOG

REC

TIFIER

INTERNA

TIONA

IGBT

1- GATE

2- COLLECTOR

3- EMITTER

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Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101] market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 08/03

TO-220AB package is not recommended for Surface Mount Application.

D2Pak Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRR

F E E D DIRE CT I O N

1.85 (.073)

1.65 (.065)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

TRL

F E E D DIRE CT I O N

10.90 (.429)

10.70 (.421) 16.10 (.6 34)

15. 90 ( . 6 26)

1.75 (.069)

1.25 (.049)

11.60 (.457)

11.40 (.449) 15. 42 (.6 09 )

15. 22 (.601 )

4.72 (.136)

4.52 (.178)

24.30 (.957)

23.90 (.941)

0.368 (.0145)

0.342 (.0135)

1.60 (.063)

1.50 (.059)

13.50 (.532)

12.80 (.504)

330.00

(14.173)

MAX.

27.40 (1.079)

23.90 (.941)

60.00 (2.362)

MIN.

30.40 (1.197)

MAX.

26.40 (1.039)

24.40 (.961)

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUD ES FLANGE DISTORTION @ OUTER EDGE.

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Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/

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