X28C512DI-15 - Xicor, Inc. - Product.Network

X28C512/X28C513

512K X28C512/X28C513 64K x 8 Bit

5 Volt, Byte Alterable E2PROM

3856-3.2 8/5/97 T1/C0/D0 EW

FEATURES

•Access Time: 90ns

•Simple Byte and Page Write

—Single 5V Supply

— No External High Voltages or VPP Control

Circuits

—Self-Timed

—No Erase Before Write

—No Complex Programming Algorithms

—No Overerase Problem

•Low Power CMOS:

—Active: 50mA

—Standby: 500µA

•Software Data Protection

—Protects Data Against System Level

Inadvertant Writes

•High Speed Page Write Capability

•Highly Reliable Direct Write™ Cell

—Endurance: 100,000 Write Cycles

—Data Retention: 100 Years

•Early End of Write Detection

—DATA Polling

—Toggle Bit Polling

•Two PLCC and LCC Pinouts

—X28C512

—X28C010 E2PROM Pin Compatible

—X28C513

—Compatible with Lower Density E2PROMs

DESCRIPTION

The X28C512/513 is an 64K x 8 E2PROM, fabricated

with Xicor’s proprietary, high performance, floating gate

CMOS technology. Like all Xicor programmable non-

volatile memories the X28C512/513 is a 5V only device.

The X28C512/513 features the JEDEC approved pinout

for bytewide memories, compatible with industry stan-

dard EPROMS.

The X28C512/513 supports a 128-byte page write op-

eration, effectively providing a 39µs/byte write cycle and

enabling the entire memory to be written in less than 2.5

seconds. The X28C512/513 also features DATA Polling

and Toggle Bit Polling, system software support schemes

used to indicate the early completion of a write cycle. In

addition, the X28C512/513 supports the Software Data

Protection option.

PIN CONFIGURATIONS

3856 FHD F01

A15

A12

I/O0

I/O1

I/O2

VSS

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/04

I/O3

X28C512

PLASTIC DIP

CERDIP

FLAT PACK

SOIC (R)

X28C512

3856 ILL F22

A10

I/O7

I/O6

I/O5

I/O4

I/O3

VSS

I/O2

I/O1

I/O0

A11

A13

A14

VCC

A15

A12

TSOP

X28C512

(TOP VIEW)

I/O0

A13

A11

A10

I/O7

A14

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

A12

A15

VCC

3856 FHD F03

232

13 15 1716 18 19 20

14 21

PLCC / LCC

X28C513

(TOP VIEW)

I/O0

A11

A10

I/O7

I/O6

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

A12

A14

A15

VCC

A13

3856 FHD F04

232

13 15 1716 18 19 20

PGA

3856 FHD F02

BOTTOM

VIEW

A016

I/O118

VSS

11A3

9A5

7A7

I/O017

I/O219

I/O3

5A15 2NC 36

VCC

I/O4

I/O5

I/O7

A10

A11

I/O6

A13

8A6

4NC 3NC 1NC 35

WE 33

A14

6A12

X28C512/X28C513

PIN DESCRIPTIONS

Addresses (A0–A15)

The Address inputs select an 8-bit memory location

during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/

write operations. When CE is HIGH, power consumption

is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers

and is used to initiate read operations.

Data In/Data Out (I/O0–I/O7)

Data is written to or read from the X28C512/513 through

the I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the

X28C512/513.

FUNCTIONAL DIAGRAM

PIN NAMES

Symbol Description

A0–A15 Address Inputs

I/O0–I/O7Data Input/Output

WE Write Enable

CE Chip Enable

OE Output Enable

VCC +5V

VSS Ground

NC No Connect 3856 PGM T01

X BUFFERS

LA TCHES AND

DECODER

I/O BUFFERS

AND LATCHES

3856 FHD F05

Y BUFFERS

LA TCHES AND

DECODER

CONTROL

LOGIC AND

TIMING

512K-BIT

E2PROM

ARRAY

I/O0–I/O7

DATA INPUTS/OUTPUTS

VCC

VSS

A7–A15

A0–A6

X28C512/X28C513

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE LOW.

The read operation is terminated by either CE or OE

returning HIGH. This two line control architecture elimi-

nates bus contention in a system environment. The data

bus will be in a high impedance state when either OE or

CE is HIGH.

Write

Write operations are initiated when both CE and WE are

LOW and OE is HIGH. The X28C512/513 supports both

a CE and WE controlled write cycle. That is, the address

is latched by the falling edge of either CE or WE,

whichever occurs last. Similarly, the data is latched

internally by the rising edge of either CE or WE, which-

ever occurs first. A byte write operation, once initiated,

will automatically continue to completion, typically within

5ms.

Page Write Operation

The page write feature of the X28C512/513 allows the

entire memory to be written in 2.5 seconds. Page write

allows two to one hundred twenty-eight bytes of data to

be consecutively written to the X28C512/513 prior to the

commencement of the internal programming cycle. The

host can fetch data from another device within the

system during a page write operation (change the source

address), but the page address (A7 through A15) for

each subsequent valid write cycle to the part during this

operation must be the same as the initial page address.

The page write mode can be initiated during any write

operation. Following the initial byte write cycle, the host

can write an additional one to one hundred twenty-

seven bytes in the same manner as the first byte was

written. Each successive byte load cycle, started by the

WE HIGH to LOW transition, must begin within 100µs of

the falling edge of the preceding WE. If a subsequent

WE HIGH to LOW transition is not detected within

100µs, the internal automatic programming cycle will

commence. There is no page write window limitation.

Effectively the page write window is infinitely wide, so

long as the host continues to access the device within

the byte load cycle time of 100µs.

Write Operation Status Bits

The X28C512/513 provides the user two write operation

status bits. These can be used to optimize a system

write cycle time. The status bits are mapped onto the

I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

DATA Polling (I/O7)

The X28C512/513 features DATA Polling as a method

to indicate to the host system that the byte write or page

write cycle has completed. DATA Polling allows a simple

bit test operation to determine the status of the X28C512/

513, eliminating additional interrupt inputs or external

hardware. During the internal programming cycle, any

attempt to read the last byte written will produce the

complement of that data on I/O7 (i.e. write data = 0xxx

xxxx, read data = 1xxx xxxx). Once the programming

cycle is complete, I/O7 will reflect true data.

Toggle Bit (I/O6)

The X28C512/513 also provides another method for

determining when the internal write cycle is complete.

During the internal programming cycle, I/O6 will toggle

from HIGH to LOW and LOW to HIGH on subsequent

attempts to read the device. When the internal cycle is

complete the toggling will cease and the device will be

accessible for additional read or write operations.

3856 FHD F06

TBDP 43210I/O

RESERVED

TOGGLE BIT

DATA POLLING

X28C512/X28C513

DATA Polling I/O7

Figure 2a. DATA Polling Bus Sequence

Figure 2b. DATA Polling Software Flow

DATA Polling can effectively halve the time for writing to

the X28C512/513. The timing diagram in Figure 2a

illustrates the sequence of events on the bus. The

software flow diagram in Figure 2b illustrates one method

of implementing the routine.

WRITE DATA

SAVE LAST DATA

AND ADDRESS

READ LAST

ADDRESS

IO7

COMPARE?

X28C512

READY

YES

WRITES

COMPLETE? NO

YES

3856 FHD F08

I/O7X28C512/513

READY

LAST

WRITE

HIGH Z VOL

VIH

A0–A15 An An An An An An

VOH

3856 FHD F07.1

X28C512/X28C513

The Toggle Bit I/O6

Figure 3a. Toggle Bit Bus Sequence

Figure 3b. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping

chore of saving and fetching the last address and data

written to a device in order to implement DATA Polling.

This can be especially helpful in an array comprised of

multiple X28C512/513 memories that is frequently up-

dated. Toggle Bit Polling can also provide a method for

status checking in multiprocessor applications. The

timing diagram in Figure 3a illustrates the sequence of

events on the bus. The software flow diagram in Figure

3b illustrates a method for polling the Toggle Bit.

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

X28C512

READY

COMPARE

OK?

YES

3856 FHD F10

LAST WRITE

I/O6X28C512/513

READY

VOH

VOL

LAST

WRITE

HIGH Z

* Beginning and ending state of I/O6 will vary.

3856 FHD F09.1

X28C512/X28C513

HARDWARE DATA PROTECTION

The X28C512/513 provides three hardware features

that protect nonvolatile data from inadvertent writes.

• Noise Protection—A WE pulse typically less than

10ns will not initiate a write cycle.

• Default VCC Sense—All write functions are inhibited

when VCC is ≤3.6V.

• Write Inhibit—Holding either OE LOW, WE HIGH,

or CE HIGH will prevent an inadvertent write cycle

during power-up and power-down, maintaining data

integrity. Write cycle timing specifications must be

observed concurrently.

SOFTWARE DATA PROTECTION

The X28C512/513 offers a software controlled data

protection feature. The X28C512/513 is shipped from

Xicor with the software data protection NOT ENABLED;

that is, the device will be in the standard operating mode.

In this mode data should be protected during power-up/

-down operations through the use of external circuits.

The host would then have open read and write access

of the device once VCC was stable.

The X28C512/513 can be automatically protected dur-

ing power-up and power-down without the need for

external circuits by employing the software data protec-

tion feature. The internal software data protection circuit

is enabled after the first write operation utilizing the

software algorithm. This circuit is nonvolatile and will

remain set for the life of the device unless the reset

command is issued.

Once the software protection is enabled, the X28C512/

513 is also protected from inadvertent and accidental

writes in the powered-up state. That is, the software

algorithm must be issued prior to writing additional data

to the device. Note: The data in the three-byte enable

sequence is not written to the memory array.

SOFTWARE ALGORITHM

Selecting the software data protection mode requires

the host system to precede data write operations by a

series of three write operations to three specific ad-

dresses. Refer to Figure 4a and 4b for the sequence.

The three byte sequence opens the page write window

enabling the host to write from one to one hundred

twenty-eight bytes of data. Once the page load cycle has

been completed, the device will automatically be re-

turned to the data protected state.

X28C512/X28C513

Software Data Protection

Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write

Figure 4b. Write Sequence for Software Data

Protection Regardless of whether the device has previously been

protected or not, once the software data protected

algorithm is used and data has been written, the

X28C512/513 will automatically disable further writes

unless another command is issued to cancel it. If no

further commands are issued the X28C512/513 will be

write protected during power-down and after any subse-

quent power-up. The state of A15 while executing the

algorithm is don’t care.

Note: Once initiated, the sequence of write operations

should not be interrupted.

NOTE: All other timings and control pins are per page write timing requirements.

3856 FHD F11

(VCC)

WRITE

PROTECTED

VCC

DATA

ADDR AA

5555 55

2AAA A0

5555

≤tBLC MAX

WRITES

BYTE

PAGE

tWC

WRITE LAST

BYTE TO

LAST ADDRESS

3856 FHD F12

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA A0

TO ADDRESS

5555

WRITE DATA XX

TO ANY

ADDRESS

AFTER tWC

RE-ENTERS DATA

PROTECTED STATE

WRITE DATA AA

TO ADDRESS

5555

OPTIONAL

BYTE/PAGE

LOAD OPERATION

X28C512/X28C513

Resetting Software Data Protection

Figure 5a. Reset Software Data Protection Timing Sequence

Figure 5b. Software Sequence to Deactivate

Software Data Protection In the event the user wants to deactivate the software

data protection feature for testing or reprogramming in

an E2PROM programmer, the following six step algo-

rithm will reset the internal protection circuit. After tWC,

the X28C512/513 will be in standard operating mode.

Note: Once initiated, the sequence of write operations

should not be interrupted.

3856 FHD F13

STANDARD

OPERATING

MODE

VCC

DATA

ADDR AA

5555 55

2AAA 80

5555

NOTE: All other timings and control pins are per page write timing requirements.

≥tWC

5555 55

2AAA 20

5555

WRITE DATA 55

TO ADDRESS

2AAA

3856 FHD F14

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA 80

TO ADDRESS

5555

WRITE DATA AA

TO ADDRESS

5555

WRITE DATA 20

TO ADDRESS

5555

WRITE DATA AA

TO ADDRESS

5555

X28C512/X28C513

SYSTEM CONSIDERATIONS

Because the X28C512/513 is frequently used in large

memory arrays it is provided with a two line control

architecture for both read and write operations. Proper

usage can provide the lowest possible power dissipation

and eliminate the possibility of contention where mul-

tiple I/O pins share the same bus.

To gain the most benefit it is recommended that CE be

decoded from the address bus and be used as the

primary device selection input. Both OE and WE would

then be common among all devices in the array. For a

read operation this assures that all deselected devices

are in their standby mode and that only the selected

device(s) is outputting data on the bus.

Because the X28C512/513 has two power modes,

standby and active, proper decoupling of the memory

array is of prime concern. Enabling CE will cause

transient current spikes. The magnitude of these spikes

is dependent on the output capacitive loading of the I/

Os. Therefore, the larger the array sharing a common

bus, the larger the transient spikes. The voltage peaks

associated with the current transients can be sup-

pressed by the proper selection and placement of

decoupling capacitors. As a minimum, it is recom-

mended that a 0.1µF high frequency ceramic capacitor

be used between VCC and VSS at each device. Depend-

ing on the size of the array, the value of the capacitor

may have to be larger.

In addition, it is recommended that a 4.7µF electrolytic

bulk capacitor be placed between VCC and VSS for each

eight devices employed in the array. This bulk capacitor

is employed to overcome the voltage droop caused by

the inductive effects of the PC board traces.

Active Supply Current vs. Ambient Temperature ICC (RD) by Temperature over Frequency

Standby Supply Current vs. Ambient Temperature

–55 –10 +125

0.14

0.16

0.18

0.2

0.24

AMBIENT TEMPERATURE (°C)

(mA)

3856 ILL F26

0.1 +35 +80

0.22 V

= 5V

0.12

–55 –10 +125

AMBIENT TEMPERATURE (°C)

(mA)

3856 ILL F24

8+35 +80

= 5V

0315

5.0 V

FREQUENCY (MHz)

RD (mA)

3856 ILL F25

10 69

–55°C

+25°C

+125°C

X28C512/X28C513

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)

Limits

Symbol Parameter Min. Max. Units Test Conditions

ICC VCC Current (Active) 50 mA CE = OE = VIL, WE = VIH,

(TTL Inputs) All I/O’s = Open, Address Inputs =

.4V/2.4V Levels @ f = 5MHz

ISB1 VCC Current (Standby) 3 mA CE = VIH, OE = VIL

(TTL Inputs) All I/O’s = Open, Other Inputs = VIH

ISB2 VCC Current (Standby) 500 µACE = VCC – 0.3V, OE = VIL

(CMOS Inputs) All I/O’s = Open, Other Inputs = VIH

ILI Input Leakage Current 10 µAV

IN = VSS to VCC

ILO Output Leakage Current 10 µAV

OUT = VSS to VCC, CE = VIH

VlL(1) Input LOW Voltage –1 0.8 V

VIH(1) Input HIGH Voltage 2 VCC + 1 V

VOL Output LOW Voltage 0.4 V IOL = 2.1mA

VOH Output HIGH Voltage 2.4 V IOH = –400µA3856 PGM T04.2

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias

X28C512/513............................... –10°C to +85°C

X28C512I/513I........................... –65°C to +135°C

X28C512M/513M....................... –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Respect to VSS .......................................–1V to +7V

D.C. Output Current .............................................5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and the functional operation of

the device at these or any other conditions above those

indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

RECOMMEND OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C +70°C

Industrial –40°C +85°C

Military –55°C +125°C

3856 PGM T02

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.

Supply Voltage Limits

X28C512/513 5V ±10%

3856 PGM T03.1

X28C512/X28C513

POWER-UP TIMING

Symbol Parameter Max. Units

tPUR(2) Power-up to Read Operation 100 µs

tPUW(2) Power-up to Write Operation 5 ms 3856 PGM T05

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

Symbol Parameter Max. Units Test Conditions

CI/O(2) Input/Output Capacitance 10 pF VI/O = 0V

CIN(2) Input Capacitance 10 pF VIN = 0V

3856 PGM T06.1

ENDURANCE AND DATA RETENTION

Parameter Min. Max. Units

Endurance 10,000 Cycles Per Byte

Endurance 100,000 Cycles Per Page

Data Retention 100 Years

3856 PGM T07.1

A.C. CONDITIONS OF TEST

Input Pulse Levels 0V to 3V

Input Rise and

Fall Times 10ns

Input and Output

Timing Levels 1.5V

3856 PGM T07.1

Note: (2) This parameter is periodically sampled and not 100%

tested.

EQUIVALENT A.C. LOAD CIRCUIT SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

Must be

steady Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

3856 FHD F15.3

1.92KΩ

100pF

OUTPUT

1.37KΩ

MODE SELECTION

CE OE WE Mode I/O Power

L L H Read DOUT Active

L H L Write DIN Active

H X X Standby and High Z Standby

Write Inhibit

X L X Write Inhibit — —

X X H Write Inhibit — —

3856 PGM T08

X28C512/X28C513

Read Cycle Limits

X28C512-90 X28C512-12 X28C512-15 X28C512-20 X28C512-25

X28C513-90 X28C513-12 X28C513-15 X28C513-20 X28C513-25

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

tRC Read Cycle Time 90 120 150 200 250 ns

tCE Chip Enable Access Time 90 120 150 200 250 ns

tAA Address Access Time 90 120 150 200 250 ns

tOE Output Enable Access Time 40 50 50 50 50 ns

tLZ(3) CE LOW to Active Output 0 0 0 0 0 ns

tOLZ(3) OE LOW to Active Output 0 0 0 0 0 ns

tHZ(3) CE HIGH to High Z Output 40 50 50 50 50 ns

tOHZ(3) OE HIGH to High Z Output 40 50 50 50 50 ns

tOH Output Hold from 0 0 0 0 0 ns

Address Change 3856 PGM T09.4

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

Read Cycle

Notes: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with

CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.

3856 FHD F16

tCE

tRC

ADDRESS

DATA VALID DATA VALID

tOE

tLZ

tOLZ

tOH

tAA

tHZ

tOHZ

DATA I/O

VIH

HIGH Z

X28C512/X28C513

WRITE CYCLE LIMITS

Symbol Parameter Min. Max. Units

tWC(4) Write Cycle Time 10 ms

tAS Address Setup Time 0 ns

tAH Address Hold Time 50 ns

tCS Write Setup Time 0 ns

tCH Write Hold Time 0 ns

tCW CE Pulse Width 100 ns

tOES OE HIGH Setup Time 10 ns

tOEH OE HIGH Hold Time 10 ns

tWP WE Pulse Width 100 ns

tWPH WE HIGH Recovery 100 ns

tDV Data Valid 1 µs

tDS Data Setup 50 ns

tDH Data Hold 0 ns

tDW Delay to Next Write 10 µs

tBLC Byte Load Cycle 0.2 100 µs

3856 PGM T10.2

WE Controlled Write Cycle

Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time

the device requires to complete the internal write operation.

3856 FHD F17

ADDRESS

tAS

tWC

tAH

tOES

tDV

tDS tDH

tOEH

DATA IN

DATA OUT HIGH Z

tCS tCH

tWP

DATA VALID

X28C512/X28C513

CE Controlled Write Cycle

Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH

to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing

a polling operation.

(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform

to either the CE or WE controlled write cycle timing.

Page Write Cycle

3856 FHD F18

ADDRESS

tAS

tOEH

tWC

tAH

tOES tWPH

tCS

tDV

tDS tDH

tCH

DATA IN

DATA OUT HIGH Z

tCW

DATA VALID

3856 FHD F19.1

OE(5)

BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2

tWP

tWPH

tBLC

tWC

*ADDRESS(6)

I/O

*For each successive write within the page write operation, A7–A15 should be the same or

writes to an unknown address could occur.

LAST BYTE

X28C512/X28C513

DATA Polling Timing Diagram(7)

Toggle Bit Timing Diagram

Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.

ADDRESS An

3856 FHD F20

DIN=X DOUT=X DOUT=X

tWC

tOEH tOES

AnAn

I/O7

tDW

3856 FHD F21

I/O6

tOES

tDW

tWC

tOEH

HIGH Z *

* Starting and ending state of I/O6 will vary, depending upon actual tWC.

X28C512/X28C513

NOTES

X28C512/X28C513

PACKAGING INFORMATION

0.620 (15.75)

0.590 (14.99)

TYP. 0.614 (15.60)

0.110 (2.79)

0.090 (2.29)

TYP. 0.018 (0.46)

1.690 (42.95)

MAX.

0.023 (0.58)

0.014 (0.36)

TYP. 0.018 (0.46)

0.232 (5.90) MAX.

0.060 (1.52)

0.015 (0.38)

3926 FHD F09

PIN 1

0.200 (5.08)

0.125 (3.18) 0.065 (1.65)

0.033 (0.84)

TYP. 0.055 (1.40)

0.610 (15.49)

0.500 (12.70)

0.100 (2.54) MAX.

0°

15°

32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.005 (0.13) MIN.

0.150 (3.81) MIN.

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

X28C512/X28C513

PACKAGING INFORMATION

0.150 (3.81) BSC

0.458 (11.63)

––

0.458 (11.63)

0.442 (11.22)

PIN 1

3926 FHD F14

0.020 (0.51) x 45° REF.

0.095 (2.41)

0.075 (1.91)

0.022 (0.56)

0.006 (0.15)

0.055 (1.39)

0.045 (1.14)

TYP. (4) PLCS.

0.040 (1.02) x 45° REF.

TYP. (3) PLCS.

0.050 (1.27) BSC

0.028 (0.71)

0.022 (0.56)

(32) PLCS.

0.200 (5.08)

BSC

0.558 (14.17)

––

0.088 (2.24)

0.050 (1.27)

0.120 (3.05)

0.060 (1.52)

PIN 1 INDEX CORNER

32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. TOLERANCE: ±1% NLT ±0.005 (0.127)

0.300 (7.62)

BSC

0.015 (0.38)

MIN.

0.400 (10.16)

BSC

0.560 (14.22)

0.540 (13.71)

DIA.

0.015 (0.38)

0.003 (0.08)

X28C512/X28C513

PACKAGING INFORMATION

32-LEAD CERAMIC FLAT PACK TYPE F

3926 FHD F20

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.019 (0.48)

0.015 (0.38)

0.045 (1.14) MAX.

PIN 1 INDEX

132

0.130 (3.30)

0.090 (2.29)

0.047 (1.19)

0.026 (0.66)

0.007 (0.18)

0.004 (0.10)

0.370 (9.40)

0.270 (6.86)

0.828 (21.04)

0.812 (20.64)

0.50 (1.27) BSC

0.488

0.430 (10.93)

0.347 (8.82)

0.330 (8.38)

0.005 (0.13) MIN.

0.030 (0.76)

MIN

X28C512/X28C513

PACKAGING INFORMATION

0.021 (0.53)

0.013 (0.33)

0.420 (10.67)

0.050 (1.27) TYP.

TYP. 0.017 (0.43)0.045 (1.14) x 45°

0.300 (7.62)

REF.

0.453 (11.51)

0.447 (11.35)

TYP. 0.450 (11.43)

0.495 (12.57)

0.485 (12.32)

TYP. 0.490 (12.45)

PIN 1

0.400

(10.16)REF.

0.553 (14.05)

0.547 (13.89)

TYP. 0.550 (13.97)

0.595 (15.11)

0.585 (14.86)

TYP. 0.590 (14.99)

3° TYP.

0.048 (1.22)

0.042 (1.07)

0.140 (3.56)

0.100 (2.45)

TYP. 0.136 (3.45)

0.095 (2.41)

0.060 (1.52)

—

0.015 (0.38)

SEATING PLANE

±0.004 LEAD

CO – PLANARITY

3926 FHD F13

32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J

NOTES:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY

X28C512/X28C513

3926 FHD F21

36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K

15 17 19 21 22

14 16 18 20 23

10 9 27 28

8 7 29 30

5 2 36 34 32

4 3 1 35 33

TYP. 0.100 (2.54)

ALL LEADS

PIN 1 INDEX

0.050 (1.27)

0.008 (0.20)

NOTE: LEADS 5, 14, 23, & 32

12 11 25 26

6 31

0.090 (2.29)

0.070 (1.78)

0.090 (2.29)

0.070 (1.78)

0.770 (19.56)

0.750 (19.05)

SQ.

0.185 (4.70)

0.175 (4.45)

0.020 (0.51)

0.016 (0.41)

0.072 (1.83)

0.062 (1.57)

0.120 (3.05)

0.100 (2.54)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

PACKAGING INFORMATION

X28C512/X28C513

PACKAGING INFORMATION

3926 FHD F25

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.022 (0.56)

0.014 (0.36)

0.160 (4.06)

0.125 (3.17)

0.625 (15.88)

0.590 (14.99)

0.110 (2.79)

0.090 (2.29)

1.665 (42.29)

1.644 (41.76)

1.500 (38.10)

REF.

PIN 1 INDEX

0.160 (4.06)

0.140 (3.56)

0.030 (0.76)

0.015 (0.38)

PIN 1

SEATING

PLANE

0.070 (17.78)

0.030 (7.62)

0.557 (14.15)

0.510 (12.95)

0.085 (2.16)

0.040 (1.02)

0°

15°

32-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

TYP. 0.010 (0.25)

X28C512/X28C513

PACKAGING INFORMATION

32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R

3926 FHD F27

NOTES:

1. ALL DIMENSIONS IN INCHES

2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES

0.340

±0.007

SEE DETAIL “A”

FOR LEAD

INFORMATION

0.440 MAX.

0.560 NOM.

0.0192

0.0138

0.050

0.750

±0.005

0.840

MAX.

0.060 NOM.

0.020 MIN.

0.015 R TYP.

0.035 MIN.

0.015 R

TYP.

0.035 TYP.

0.165 TYP.

DETAIL “A”

0.560"

TYPICAL

0.050"

TYPICAL

0.050"

TYPICAL

FOOTPRINT 0.030" TYPICAL

32 PLACES

X28C512/X28C513

PACKAGING INFORMATION

3926 ILL F39.2

NOTE:

1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).

0.50 ± 0.04

(0.0197 ± 0.0016)

0.30 ± 0.05

(0.012 ± 0.002)

14.80 ± 0.05

(0.583 ± 0.002)

1.30 ± 0.05

(0.051 ± 0.002)

0.17 (0.007)

0.03 (0.001)

TYPICAL

40 PLACES 15 EQ. SPC. @ 0.50 ± 0.04

0.0197 ± 0.016 = 9.50 ± 0.06

(0.374 ± 0.0024) OVERALL

TOL. NON-CUMULATIVE

SOLDER PADS

FOOTPRINT

10.058 (0.396)

9.957 (0.392)

12.522 (0.493)

12.268 (0.483)

PIN #1 IDENT.

O 1.016 (0.040)

O 0.762 (0.030)

0.965

(0.038)

1.143 (0.045)

0.889 (0.035) 0.127 (0.005) DP.

0.076 (0.003) DP.

0.065 (0.0025)

14.148 (0.557)

13.894 (0.547)

SEATING

PLANE

0.178 (0.007)

1.016 (0.040)

SEATING

PLANE

15° TYP.

0.500 (0.0197)

1.219 (0.048)

0.254 (0.010)

0.152 (0.006)

0.432 (0.017)

0.813 (0.032) TYP.

0.432 (0.017)

0.508 (0.020) TYP.

0.152 (0.006)

TYP.

4° TYP.

DETAIL A

40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T

X28C512/X28C513

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes

no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described

devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to

discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,

licenses are implied.

US. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;

4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976.

Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with

appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use as critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,

and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected

to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure

of the life support device or system, or to affect its satety or effectiveness.

ORDERING INFORMATION

Access Time

–90 = 90ns

–12 = 120ns

–15 = 150ns

–20 = 200ns

–25 = 250ns

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = –40°C to +85°C

M = Military = –55°C to +125°C

MB = Mil-STD-883

Package

D = 32-Lead CerDip

E = 32-Pad LCC

F = 32-Lead Flat Pack

J = 32-Lead PLCC

K = 36-Lead Pin Grid Array

P = 32-Lead Plastic Dip

R = 32-Lead Ceramic SOIC

T = 40-Lead TSOP

X28C512 X X -X

Device

Access Time

–90 = 90ns

–12 = 120ns

–15 = 150ns

–20 = 200ns

–25 = 250ns

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = –40°C to +85°C

M = Military = –55°C to +125°C

MB = Mil-STD-883

Package

E = 32-Pad LCC

J = 32-Lead PLCC

X28C513 X X -X

Device