INTEGRATED CIRCUITS DATA SHEET PCF8583 Clock/calendar with 240 x 8-bit RAM Product specification Supersedes data of 1997 Mar 28 File under Integrated Circuits, IC12 1997 Jul 15 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 Counter function modes Alarm function modes Control/status register Counter registers Alarm control register Alarm registers Timer Event counter mode Interrupt output Oscillator and divider Initialization 8 CHARACTERISTICS OF THE I2C-BUS 8.1 8.2 8.3 8.4 Bit transfer Start and stop conditions System configuration Acknowledge 9 I2C-BUS PROTOCOL 9.1 9.2 Addressing Clock/calendar READ/WRITE cycles 1997 Jul 15 2 PCF8583 10 LIMITING VALUES 11 HANDLING 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 14 APPLICATION INFORMATION 14.1 14.1.1 14.1.2 14.1.3 Quartz frequency adjustment Method 1: fixed osci capacitor Method 2: OSCI Trimmer Method 3: 15 PACKAGE OUTLINES 16 SOLDERING 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.3.3 Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints 17 DEFINITIONS 18 LIFE SUPPORT APPLICATIONS 19 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM 1 * PCF8583 2 FEATURES I2C-bus GENERAL DESCRIPTION The PCF8583 is a clock/calendar circuit based on a 2048-bit static CMOS RAM organized as 256 words by 8 bits. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. Address pin A0 is used for programming the hardware address, allowing the connection of two devices to the bus without additional hardware. interface operating supply voltage: 2.5 V to 6 V * Clock operating supply voltage (0 to +70 C): 1.0 V to 6.0 V * 240 x 8-bit low-voltage RAM * Data retention voltage: 1.0 V to 6 V * Operating current (at fSCL = 0 Hz): max. 50 A * Clock function with four year calendar The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the clock/calendar and counter functions. The next 8 bytes may be programmed as alarm registers or used as free RAM space. The remaining 240 bytes are free RAM locations. * Universal timer with alarm and overflow indication * 24 or 12 hour format * 32.768 kHz or 50 Hz time base * Serial input/output bus (I2C) * Automatic word address incrementing * Programmable alarm, timer and interrupt function * Slave address: - READ: A1 or A3 - WRITE: A0 or A2. 3 QUICK REFERENCE DATA SYMBOL VDD PARAMETER supply voltage operating mode IDD supply current operating mode IDDO supply current clock mode CONDITION MIN. TYP. MAX. UNIT 2.5 - 6.0 V I2C-bus inactive 1.0 - 6.0 V fSCL = 100 kHz - - 200 A fSCL = 0 Hz; VDD = 5 V - 10 50 A fSCL = 0 Hz; VDD = 1 V - 2 10 A I2C-bus active Tamb operating ambient temperature range -40 - +85 C Tstg storage temperature range -65 - +150 C 4 ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION PCF8583P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8583T SO8 plastic small outline package; 8 leads; body width 7.5 mm SOT176-1 1997 Jul 15 3 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM 5 PCF8583 BLOCK DIAGRAM handbook, full pagewidth OSCI OSCO INT VDD VSS A0 SCL SDA 1 2 PCF8583 OSCILLATOR 32.768 kHz DIVIDER 1 : 256 OR 100 : 128 POWER-ON RESET CONTROL LOGIC 100 Hz 7 8 4 control/status hundredth of a second seconds minutes hours year/date weekdays/months timer alarm control 00 01 07 08 alarm registers or RAM 3 I2C-BUS INTERFACE 6 5 ADDRESS REGISTER 0F RAM (240 x 8) FF MRB001 Fig.1 Block diagram. 6 PINNING SYMBOL OSCI PIN DESCRIPTION 1 oscillator input, 50 Hz or event-pulse input OSCO 2 oscillator output A0 3 address input VSS 4 negative supply SDA 5 serial data line SCL 6 serial clock line INT 7 open drain interrupt output (active LOW) VDD 8 positive supply 1997 Jul 15 handbook, halfpage OSCI 1 OSCO 2 A0 3 V SS 4 PCF8583P PCF8583T 8 V DD 7 INT 6 SCL 5 SDA MRB014 Fig.2 Pinning diagram. 4 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM 7 PCF8583 Whenever an alarm event occurs the alarm flag of the control/status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open drain interrupt output is switched on (active LOW) when the alarm or timer flag is set (enabled). The flags remain set until directly reset by a write operation. FUNCTIONAL DESCRIPTION The PCF8583 contains a 256 by 8-bit RAM with an 8-bit auto-increment address register, an on-chip 32.768 kHz oscillator circuit, a frequency divider, a serial two-line bidirectional I2C-bus interface and a power-on reset circuit. The first 16 bytes of the RAM (memory addresses 00 to 0F) are designed as addressable 8-bit parallel special function registers. The first register (memory address 00) is used as a control/status register. The memory addresses 01 to 07 are used as counters for the clock function. The memory addresses 08 to 0F may be programmed as alarm registers or used as free RAM locations, when the alarm is disabled. 7.1 When the alarm is disabled (Bit 2 of control/status register = 0) the alarm registers at addresses 08 to 0F may be used as free RAM. 7.3 The control/status register is defined as the memory location 00 with free access for reading and writing via the I2C-bus. All functions and options are controlled by the contents of the control/status register (see Fig.3). Counter function modes When the control/status register is programmed, a 32.768 kHz clock mode, a 50 Hz clock mode or an event-counter mode can be selected. 7.4 The year and date are packed into memory location 05 (see Fig.6). The weekdays and months are packed into memory location 06 (see Fig.7). When reading these memory locations the year and weekdays are masked out when the mask flag of the control/status register is set. This allows the user to read the date and month count directly. When one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore, faulty reading of the count during a carry condition is prevented. In the event-counter mode events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed. When a counter is written, other counters are not affected. In the different modes the counter registers are programmed and arranged as shown in Fig.4. Counter cycles are listed in Table 1. Alarm function modes By setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated. By setting the alarm control register a dated alarm, a daily alarm, a weekday alarm or a timer alarm may be programmed. In the clock modes, the timer register (address 07) may be programmed to count hundredths of a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed. 1997 Jul 15 Counter registers In the clock modes 24 h or 12 h format can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Fig.5. In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are stored in a BCD format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data. 7.2 Control/status register 5 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth PCF8583 MSB 7 LSB 6 5 4 3 2 1 0 memory location 00 reset state: 0000 0000 timer flag (50% duty factor seconds flag if alarm enable bit is 0) alarm flag (50% duty factor minutes flag if alarm enable bit is 0) alarm enable bit: 0 alarm disabled: flags toggle alarm control register disabled (memory locations 08 to 0F are free RAM space) 1 enable alarm control register (memory location 08 is the alarm control register) mask flag: 0 read locations 05 to 06 unmasked 1 read date and month count directly function mode : 00 clock mode 32.768 kHz 01 clock mode 50 Hz 10 event-counter mode 11 test modes hold last count flag : 0 count 1 store and hold last count in capture latches stop counting flag : 0 count pulses 1 stop counting, reset divider MRB017 Fig.3 Control/status register. 1997 Jul 15 6 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth PCF8583 control/status control/status hundredth of a second 1/10 s 1/100 s seconds 10 s 1s minutes 10 min 1 min hours 10 h 1h year/date 10 day 1 day weekday/month 10 month 1 month timer 10 day 1 day 00 D1 D0 D3 D2 02 D4 03 D5 01 free 04 free 05 free 06 timer T1 T0 07 alarm control alarm control 08 hundredth of a second 1/10 s 1/100 s alarm seconds alarm minutes alarm D1 alarm D0 D3 D2 D5 D4 09 0A 0B alarm hours free alarm date 0C free alarm month free alarm timer alarm timer free RAM free RAM CLOCK MODES 0D 0E 0F EVENT COUNTER MRB015 Fig.4 Register arrangement. 1997 Jul 15 7 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth MSB 7 PCF8583 LSB 6 5 4 3 2 1 0 memory location 04 (hours counter) reset state: 0000 0000 unit hours BCD ten hours (0 to 2 binary) AM/PM flag: 0 AM 1 PM format: 0 24 h format, AM/PM flag remains unchanged 1 12 h format, AM/PM flag will be updated MRB002 Fig.5 Format of the hours counter. handbook, full pagewidth MSB 7 LSB 6 5 4 3 2 1 0 memory location 05 (year/date) reset state: 0000 0001 unit days BCD ten days (0 to 3 binary) year (0 to 3 binary, read as 0 if the mask flag is set) MRB003 Fig.6 Format of the year/date counter. handbook, full pagewidth MSB 7 LSB 6 5 4 3 2 1 0 memory location 06 (weekdays/months) reset state: 0000 0001 unit months BCD ten months weekdays (0 to 6 binary, read as 0 if the mask flag is set) MRB004 Fig.7 Format of the weekdays/month counter. 1997 Jul 15 8 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM Table 1 PCF8583 Cycle length of the time counters, clock modes UNIT COUNTING CYCLE CONTENTS OF THE MONTH COUNTER CARRY TO NEXT UNIT Hundredths of a second 00 to 99 99 to 00 - Seconds 00 to 59 59 to 00 - Minutes 00 to 59 59 to 00 - Hours (24 h) 00 to 23 23 to 00 - Hours (12 h) 12 AM - - 01 AM to 11 AM - - 12 PM - - 01 PM to 11 PM 11 PM to 12 AM - 01 to 31 31 to 01 1, 3, 5, 7, 8, 10 and 12 01 to 30 30 to 01 4, 6, 9 and 11 01 to 29 29 to 01 2, year = 0 01 to 28 28 to 01 2, year = 1, 2 and 3 Months 01 to 12 12 to 01 - Year 0 to 3 - - Weekdays 0 to 6 6 to 0 - Timer 00 to 99 no carry - Date 7.5 An alarm signal is generated when the contents of the alarm registers matches bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday/month register will select the weekdays on which an alarm is activated (see Fig.9). Alarm control register When the alarm enable bit of the control/status register is set (address 00, bit 2) the alarm control register (address 08) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Fig.8). 7.6 Remark: In the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter. Alarm registers All alarm registers are allocated with a constant address offset of hexadecimal 08 to the corresponding counter registers (see Fig.4, Register arrangement). 1997 Jul 15 9 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth PCF8583 MSB 7 LSB 6 5 4 3 2 1 0 memory location 08 reset state: 0000 0000 timer function : 000 001 010 011 100 101 110 111 no timer hundredths of a second seconds minutes hours days not used test mode, all counters in parallel (factory use only) timer interrupt enable : 0 1 timer flag, no interrupt timer flag, interrupt clock alarm function : 00 01 10 11 no clock alarm daily alarm weekday alarm dated alarm timer alarm enable : 0 1 no timer alarm timer alarm alarm interrupt enable : MRB005 (valid only when 'alarm enable' in control / status register is set 0 1 alarm flag, no interrupt alarm flag, interrupt Fig.8 Alarm control register; clock mode. 1997 Jul 15 10 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth MSB 7 PCF8583 LSB 6 5 4 3 2 1 0 memory location 0E (alarm weekday / month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used MRB006 Fig.9 Selection of alarm weekdays. 7.7 The event counter stores up to 6 digits of data, which are stored as 6 hexadecimal values located in locations 1, 2, and 3. Thus, up to 1 million events may be recorded. Timer The timer (location 07) is enabled by setting the control/status register = XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the timer resets to 0. The timer flag (LSB of control/status register) is set on overflow of the timer. This flag must be reset by software. The inverted value of this flag can be transferred to the external interrupt by setting bit 3 of the alarm control register. An event counter alarm occurs when the event counter registers match the value programmed in locations 9, A, and B, and the event alarm is enabled (bits 4 and 5 which are logic 0, 1 in the alarm control register). In this event, the alarm flag (bit 1 of the control/status register) is set. The inverted value of this flag can be transferred to the interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. In this mode, the timer (location 07) increments once for every one, one-hundred, ten thousand, or 1 million events, depending on the value programmed in bits 0, 1 and 2 of the alarm control register. In all other events, the timer functions are as in the clock mode. Additionally, a timer alarm can be programmed by setting the timer alarm enable (bit 6 of the alarm control register). When the value of the timer equals a pre-programmed value in the alarm timer register (location 0F), the alarm flag is set (bit 1 of the control/status register). The inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit 6 of the alarm control register). 7.9 Resolution of the timer is programmed via the 3 LSBs of the alarm control register (see Fig.11, Alarm and timer Interrupt logic diagram). 7.8 The conditions for activating the open-drain n-channel interrupt output INT (active LOW) are determined by appropriate programming of the alarm control register. These conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrupt is enabled. In all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt. Event counter mode Event counter mode is selected by bits 4 and 5 which are logic 1, 0 in the control/status register. The event counter mode is used to count pulses externally applied to the oscillator input (OSCO left open-circuit). 1997 Jul 15 Interrupt output 11 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth PCF8583 MSB 7 LSB 6 5 4 3 2 1 0 memory location 08 reset state: 0000 0000 timer function : 000 001 010 011 100 101 110 111 no timer units 100 10 000 1 000 000 not allowed not allowed test mode, all counters in parallel timer interrupt enable : 0 1 timer flag, no interrupt timer flag, interrupt clock alarm function : 00 01 10 11 no event alarm event alarm not allowed not allowed timer alarm enable : 0 1 no timer alarm timer alarm alarm interrupt enable : MRB007 0 1 alarm flag, no interrupt alarm flag, interrupt Fig.10 Alarm control register, event-counter mode. In the clock mode, if the alarm enable is not activated (alarm enable bit of control/status register is logic 0), the interrupt output toggles at 1 Hz with a 50% duty cycle (may be used for calibration). This is the default power-on state of the device. The OFF voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic diagram of the interrupt output is shown in Fig.11. 7.10 This allows the user to feed the 50 Hz reference frequency or an external high speed event signal into the input OSCI. 7.11 When power-up occurs the I2C-bus interface, the control/status register and all clock counters are reset. The device starts time-keeping in the 32.768 kHz clock mode with the 24 h format on the first of January at 0.00.00: 00. A 1 Hz square wave with 50% duty cycle appears at the interrupt output pin (starts HIGH). Oscillator and divider A 32.768 kHz quartz crystal has to be connected to OSCI (pin 1) and OSCO (pin 2). A trimmer capacitor between OSCI and VDD is used for tuning the oscillator (see quartz frequency adjustment). A 100 Hz clock signal is derived from the quartz oscillator for the clock counters. It is recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction. In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high impedance state. 1997 Jul 15 Initialization 12 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 handbook, full pagewidth MUX oscillator mode select counter CLOCK/CALENDAR control TIMER ALARM clock alarm 7 6 alarm control 5 4 3 2 1 timer alarm 0 timer control overflow 7 6 5 4 CONTROL/STATUS 3 2 1 0 ALARM CONTROL REGISTER REGISTER (1) alarm interrupt timer overflow interrupt INT MBD818 (1) If the alarm enable bit of the control/status register is reset (logic 0), a 1 Hz signal can be observed on the interrupt pin INT. Fig.11 Alarm and timer interrupt logic diagram. 1997 Jul 15 13 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM 8 PCF8583 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer (see Fig.12) One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. SDA SCL change of data allowed data line stable; data valid MBC621 Fig.12 Bit transfer. 8.2 Start and stop conditions (see Fig.13) Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). SDA SDA SCL SCL S P START condition STOP condition Fig.13 Definition of start and stop conditions. 1997 Jul 15 14 MBC622 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM 8.3 PCF8583 System configuration (see Fig.14) A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER SLAVE RECEIVER MASTER TRANSMITTER / RECEIVER MASTER TRANSMITTER MBA605 Fig.14 System configuration. 8.4 The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Acknowledge (see Fig.15) The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S START CONDITION MBC602 Fig.15 Acknowledgment on the I2C-bus. 1997 Jul 15 15 clock pulse for acknowledgement Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM 9 9.1 PCF8583 I2C-BUS PROTOCOL Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.16. Bit A0 corresponds to hardware address pin A0. Connecting this pin to VDD or VSS allows the device to have one of two different addresses. handbook, halfpage 1 0 1 0 0 0 A0 R/W MRB016 group 2 group 1 Fig.16 Slave address. 9.2 Clock/calendar READ/WRITE cycles The I2C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in Figs 17, 18 and 19. acknowledgement from slave acknowledgement from slave handbook, full pagewidth S SLAVE ADDRESS 0 A WORD ADDRESS R/W A acknowledgement from slave DATA A P n bytes auto increment memory word address MBD822 Fig.17 Master transmits to slave receiver (WRITE) mode. 1997 Jul 15 16 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth S acknowledgement from slave acknowledgement from slave SLAVE ADDRESS 0 A PCF8583 WORD ADDRESS R/W A S acknowledgement from slave SLAVE ADDRESS at this moment master transmitter becomes master - receiver and PCF8593 slave - receiver becomes slave - transmitter 1 A R/W acknowledgement from master DATA A n bytes auto increment memory word address no acknowledgement from master DATA 1 P last byte auto increment memory word address MBD823 Fig.18 Master reads after setting word address (write word address; READ data). acknowledgement from slave acknowledgement from slave handbook, full pagewidth S SLAVE ADDRESS 1 A R/W DATA A n bytes acknowledgement from slave DATA 1 P last bytes auto increment word address auto increment word address MBD824 Fig.19 Master reads slave immediately after first byte (READ mode). 1997 Jul 15 17 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage (pin 8) -0.8 +7.0 V IDD supply current (pin 8) - 50 mA ISS supply current (pin 4) - 50 mA VI input voltage -0.8 VDD + 0.8 V II DC input current - 10 mA IO DC output current - 10 mA Ptot total power dissipation per package - 300 mW PO power dissipation per output - 50 mW Tamb operating ambient temperature -40 +85 C Tstg storage temperature -65 +150 C 11 HANDLING Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under "Handling MOS Devices". 12 DC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = -40 to +85 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT supply voltage (operating mode) I2C-bus 2.5 - 6.0 V I2C-bus inactive 1.0 - 6.0 V VDDosc supply voltage (quartz oscillator) Tamb = 0 to 70 C; note 2 1.0 - 6.0 V IDD supply current (operating mode) fSCL = 100 kHz; clock mode; note 3 - - 200 A IDDO supply current (clock mode) see Fig.20 fSCL = 0 Hz; VDD = 5 V - 10 50 A fSCL = 0 Hz; VDD = 1 V - 2 10 A data retention fOSCI = 0 Hz; VDD = 1 V Tamb = -40 to + 85 C - - 5 A Tamb = -25 to + 70 C - - 2 A note 4 1.5 1.9 2.3 V V VDD IDDR VEN I2C-bus enable level active SDA VIL LOW level input voltage note 5 -0.8 - 0.3VDD VIH HIGH level input voltage note 5 0.7VDD - VDD +0.8 V IOL LOW level output current VOL = 0.4 V 3 - - mA ILI input leakage current VI = VDD or VSS -1 - +1 A Ci input capacitance note 6 - - 7 pF 1997 Jul 15 18 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM SYMBOL PARAMETER PCF8583 CONDITIONS MIN. TYP.(1) MAX. UNIT A0; OSCI input leakage current Vl = VDD or VSS -250 - +250 nA IOL LOW level output current VOL = 0.4 V 3 - - mA ILI input leakage current Vl = VDD or VSS -1 - +1 A Ci input capacitance note 6 - - 7 pF ILI input leakage current VI = VDD or VSS -1 - +1 A ILI INT SCL Notes 1. Typical values measured at Tamb = 25 C. 2. When powering-up the device, VDD must exceed 1.5 V until stable operation of the oscillator is established. 3. Event counter mode: supply current dependant upon input frequency. 4. The I2C-bus logic is disabled if VDD < VEN. 5. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must not exceed 0.5 mA. 6. Tested on sample basis. MRB012 12 handbook, halfpage I DDO (A) 8 4 0 0 2 4 V DD (V) 6 fSCL = 32 kHz; Tamb = 25 C. Fig.20 Typical supply current in clock mode as a function of supply voltage. 1997 Jul 15 19 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 13 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Oscillator Cosc integrated oscillator capacitance fosc oscillator stability fi input frequency - 40 - for VDD = 100 mV; Tamb = 25 C; VDD = 1.5 V - 2 x 10-7 - note 1 - - 1 MHz pF Quartz crystal parameters (f = 32.768 kHz) Rs series resistance - - 40 k CL parallel load capacitance - 10 - pF CT trimmer capacitance 5 - 25 pF - 100 kHz I2C-bus timing (see Fig.21; notes 2 and 3) fSCL SCL clock frequency - tSP tolerable spike width on bus - - 100 ns tBUF bus free time 4.7 - - s tSU;STA START condition set-up time 4.7 - - s tHD;STA START condition hold time 4.0 - - s tLOW SCL LOW time 4.7 - - s tHIGH SCL HIGH time 4.0 - - s tr SCL and SDA rise time - - 1.0 s tf SCL and SDA fall time - - 0.3 s tSU;DAT data set-up time 250 - - ns tHD;DAT data hold time 0 - - ns tVD;DAT SCL LOW to data out valid - - 3.4 s tSU;STO STOP condition set-up time 4.0 - - s Notes 1. Event counter mode only. 2. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and VIH with an input voltage swing of VSS to VDD. 3. A detailed description of the I2C-bus specification, with applications, is given in brochure "The I2C-bus and how to use it". This brochure may be ordered using the code 9398 393 40011. 1997 Jul 15 20 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM handbook, full pagewidth t t SU;STA BIT 6 (A6) BIT 7 MSB (A7) START CONDITION (S) PROTOCOL LOW PCF8583 t HIGH BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / f SCL SCL t tr BUF tf SDA t HD;STA t SU;DAT t t VD;DAT HD;DAT MBD820 t SU;STO Fig.21 I2C-bus timing diagram; rise and fall times refer to VIL and VIH. 14 APPLICATION INFORMATION Procedure: 14.1 * Power-on 14.1.1 Quartz frequency adjustment * Initialization (alarm functions). METHOD 1: FIXED OSCI CAPACITOR Routine: By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 1 Hz signal available after power-on at the interrupt output (pin 7). The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 x 10-6). Average deviations of 5 minutes per year can be achieved. 14.1.2 * Set clock to time T and set alarm to time T + dT * At time T + dT (interrupt) repeat routine. 14.1.3 Direct measurement of OSC out (accounting for test probe capacitance). The PCF8583 slave address has a fixed combination 1010 as group 1. METHOD 2: OSCI TRIMMER Using the alarm function (via the I2C-bus) a signal faster than 1 Hz can be generated at the interrupt output for fast setting of a trimmer. 1997 Jul 15 METHOD 3: 21 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 V DD handbook, full pagewidth SDA V DD SCL MASTER TRANSMITTER A0 CLOCK CALENDAR OSCI PCF8583 '1010' OSCO SCL SDA V SS VDD VDD 1 A0 OSCI EVENT COUNTER PCF8583 '1010' OSCO SCL SDA V SS V DD R SDA Fig.22 Application diagram. 22 R: pull-up resistor R = trise / C-bus SCL (I 2C-bus) 1997 Jul 15 R MRB018 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 15 PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 1.15 inches 0.17 0.020 0.13 0.068 0.045 0.021 0.015 0.042 0.035 0.014 0.009 0.39 0.36 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT97-1 050G01 MO-001AN 1997 Jul 15 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 23 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 SO8: plastic small outline package; 8 leads; body width 7.5 mm SOT176-1 D E A X c y HE v M A Z 8 5 Q A2 A (A 3) A1 pin 1 index Lp L 1 4 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 7.65 7.45 7.6 7.4 1.27 10.65 10.00 1.45 1.1 0.45 1.1 1.0 0.25 0.25 0.1 2.0 1.8 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.30 0.29 0.30 0.29 0.050 0.419 0.057 0.394 0.043 0.018 0.043 0.039 0.01 0.01 0.004 0.079 0.071 inches 0.10 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-25 97-05-22 SOT176-1 1997 Jul 15 EUROPEAN PROJECTION 24 o 8 0o Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. 16 SOLDERING 16.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 16.3.2 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 16.2 16.2.1 Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE * The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 16.3 16.3.1 16.3.3 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Jul 15 WAVE SOLDERING 25 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 17 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jul 15 26 Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 NOTES 1997 Jul 15 27 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com (c) Philips Electronics N.V. 1997 SCA55 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417067/00/05/pp28 Date of release: 1997 Jul 15 Document order number: 9397 750 02588