DATA SH EET
Product specification
Supersedes data of 1997 Mar 28
File under Integrated Circuits, IC12
1997 Jul 15
INTEGRATED CIRCUITS
PCF8583
Clock/calendar with 240 ×8-bit
RAM
1997 Jul 15 2
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 Counter function modes
7.2 Alarm function modes
7.3 Control/status register
7.4 Counter registers
7.5 Alarm control register
7.6 Alarm registers
7.7 Timer
7.8 Event counter mode
7.9 Interrupt output
7.10 Oscillator and divider
7.11 Initialization
8 CHARACTERISTICS OF THE I2C-BUS
8.1 Bit transfer
8.2 Start and stop conditions
8.3 System configuration
8.4 Acknowledge
9I
2
C-BUS PROTOCOL
9.1 Addressing
9.2 Clock/calendar READ/WRITE cycles
10 LIMITING VALUES
11 HANDLING
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 APPLICATION INFORMATION
14.1 Quartz frequency adjustment
14.1.1 Method 1: fixed osci capacitor
14.1.2 Method 2: OSCI Trimmer
14.1.3 Method 3:
15 PACKAGE OUTLINES
16 SOLDERING
16.1 Introduction
16.2 DIP
16.2.1 Soldering by dipping or by wave
16.2.2 Repairing soldered joints
16.3 SO
16.3.1 Reflow soldering
16.3.2 Wave soldering
16.3.3 Repairing soldered joints
17 DEFINITIONS
18 LIFE SUPPORT APPLICATIONS
19 PURCHASE OF PHILIPS I2C COMPONENTS
1997 Jul 15 3
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
1 FEATURES
•I2C-bus interface operating supply voltage: 2.5 V to 6 V
•Clock operating supply voltage (0 to +70 °C):
1.0 V to 6.0 V
•240 ×8-bit low-voltage RAM
•Data retention voltage: 1.0 V to 6 V
•Operating current (at fSCL = 0 Hz): max. 50 µA
•Clock function with four year calendar
•Universal timer with alarm and overflow indication
•24 or 12 hour format
•32.768 kHz or 50 Hz time base
•Serial input/output bus (I2C)
•Automatic word address incrementing
•Programmable alarm, timer and interrupt function
•Slave address:
– READ: A1 or A3
– WRITE: A0 or A2.
2 GENERAL DESCRIPTION
The PCF8583 is a clock/calendar circuit based on a
2048-bit static CMOS RAM organized as 256 words by
8 bits. Addresses and data are transferred serially via the
two-line bidirectional I2C-bus. The built-in word address
register is incremented automatically after each written or
read data byte. Address pin A0 is used for programming
the hardware address, allowing the connection of two
devices to the bus without additional hardware.
The built-in 32.768 kHz oscillator circuit and the first
8 bytes of the RAM are used for the clock/calendar and
counter functions. The next 8 bytes may be programmed
as alarm registers or used as free RAM space.
The remaining 240 bytes are free RAM locations.
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT
VDD supply voltage operating mode I2C-bus active 2.5 −6.0 V
I2C-bus inactive 1.0 −6.0 V
IDD supply current operating mode fSCL = 100 kHz −−200 µA
IDDO supply current clock mode fSCL = 0 Hz; VDD =5V −10 50 µA
fSCL = 0 Hz; VDD =1V −210µA
T
amb operating ambient temperature range −40 −+85 °C
Tstg storage temperature range −65 −+150 °C
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
PCF8583P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
PCF8583T SO8 plastic small outline package; 8 leads; body width 7.5 mm SOT176-1
1997 Jul 15 4
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
5 BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MRB001
control/status
hundredth of a second
seconds
minutes
hours
year/date
weekdays/months
timer
alarm control
alarm registers
or RAM
RAM
(240 × 8)
DIVIDER
1 : 256
OR
100 : 128
100 Hz
PCF8583
OSCILLATOR
32.768 kHz
CONTROL
LOGIC
POWER-ON
RESET
ADDRESS
REGISTER
OSCI
OSCO
INT
A0
SDA
FF
0F
08
07
01
00
I2C-BUS
INTERFACE
VDD
1
2
7
8
3
SCL 6
5
VSS 4
6 PINNING
SYMBOL PIN DESCRIPTION
OSCI 1 oscillator input, 50 Hz or event-pulse
input
OSCO 2 oscillator output
A0 3 address input
VSS 4 negative supply
SDA 5 serial data line
SCL 6 serial clock line
INT 7 open drain interrupt output (active
LOW)
VDD 8 positive supply
handbook, halfpage
1
2
3
4
8
7
6
5
PCF8583P
PCF8583T
VSS
OSCI
OSCO
SCL
SDA
VDD
MRB014
INT
A0
Fig.2 Pinning diagram.
1997 Jul 15 5
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
7 FUNCTIONAL DESCRIPTION
The PCF8583 contains a 256 by 8-bit RAM with an 8-bit
auto-increment address register, an on-chip 32.768 kHz
oscillator circuit, a frequency divider, a serial two-line
bidirectional I2C-bus interface and a power-on reset circuit.
The first 16 bytes of the RAM (memory addresses
00 to 0F) are designed as addressable 8-bit parallel
special function registers. The first register (memory
address 00) is used as a control/status register.
The memory addresses 01 to 07 are used as counters for
the clock function. The memory addresses 08 to 0F may
be programmed as alarm registers or used as free RAM
locations, when the alarm is disabled.
7.1 Counter function modes
When the control/status register is programmed, a
32.768 kHz clock mode, a 50 Hz clock mode or an
event-counter mode can be selected.
In the clock modes the hundredths of a second, seconds,
minutes, hours, date, month (four year calendar) and
weekday are stored in a BCD format. The timer register
stores up to 99 days. The event counter mode is used to
count pulses applied to the oscillator input (OSCO left
open-circuit). The event counter stores up to 6 digits of
data.
When one of the counters is read (memory locations
01 to 07), the contents of all counters are strobed into
capture latches at the beginning of a read cycle. Therefore,
faulty reading of the count during a carry condition is
prevented.
When a counter is written, other counters are not affected.
7.2 Alarm function modes
By setting the alarm enable bit of the control/status register
the alarm control register (address 08) is activated.
By setting the alarm control register a dated alarm, a daily
alarm, a weekday alarm or a timer alarm may be
programmed. In the clock modes, the timer register
(address 07) may be programmed to count hundredths of
a second, seconds, minutes, hours or days. Days are
counted when an alarm is not programmed.
Whenever an alarm event occurs the alarm flag of the
control/status register is set. A timer alarm event will set
the alarm flag and an overflow condition of the timer will set
the timer flag. The open drain interrupt output is switched
on (active LOW) when the alarm or timer flag is set
(enabled). The flags remain set until directly reset by a
write operation.
When the alarm is disabled (Bit 2 of control/status
register = 0) the alarm registers at addresses 08 to 0F
may be used as free RAM.
7.3 Control/status register
The control/status register is defined as the memory
location 00 with free access for reading and writing via the
I2C-bus. All functions and options are controlled by the
contents of the control/status register (see Fig.3).
7.4 Counter registers
In the clock modes 24 h or 12 h format can be selected by
setting the most significant bit of the hours counter
register. The format of the hours counter is shown in Fig.5.
The year and date are packed into memory location 05
(see Fig.6). The weekdays and months are packed into
memory location 06 (see Fig.7). When reading these
memory locations the year and weekdays are masked out
when the mask flag of the control/status register is set.
This allows the user to read the date and month count
directly.
In the event-counter mode events are stored in BCD
format. D5 is the most significant and D0 the least
significant digit. The divider is by-passed.
In the different modes the counter registers are
programmed and arranged as shown in Fig.4. Counter
cycles are listed in Table 1.
1997 Jul 15 6
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.3 Control/status register.
handbook, full pagewidth
memory location 00
reset state: 0000 0000
timer flag (50% duty factor
seconds flag if alarm
enable bit is 0)
alarm flag (50% duty factor
minutes flag if alarm
enable bit is 0)
alarm enable bit:
0 alarm disabled: flags toggle
alarm control register disabled
(memory locations 08 to 0F
are free RAM space)
1 enable alarm control register
(memory location 08 is the
alarm control register)
mask flag:
0 read locations 05 to 06
unmasked
1 read date and month count
directly
function mode :
00 clock mode 32.768 kHz
01 clock mode 50 Hz
10 event-counter mode
11 test modes
hold last count flag :
0 count
1 store and hold last count in
capture latches
stop counting flag :
0 count pulses
1 stop counting, reset divider
76543210
MSB LSB
MRB017
1997 Jul 15 7
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
handbook, full pagewidth
control/status
hundredth of a second
1/10 sseconds
minutes
hours
year/date
weekday/month
timer
10 s
10 min
10 h
10 day
10 month
10 day
1/100 s
1 s
1 min
1 h
1 day
1 month
1 day
alarm control
hundredth of a second
1/10 s 1/100 s
alarm seconds
alarm minutes
alarm hours
alarm month
alarm timer
alarm date
control/status
D1
D3
D5
free
free
free
timer
T1
alarm control
alarm alarm
D1
D3
D5
D0
D2
D4
T0
D0
D2
D4
free
free
free
alarm timer
free RAM free RAM
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
CLOCK MODES EVENT COUNTER
MRB015
Fig.4 Register arrangement.
1997 Jul 15 8
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.5 Format of the hours counter.
h
andbook, full pagewidth
76543210
MSB LSB
MRB002
memory location 04 (hours counter)
reset state: 0000 0000
unit hours BCD
ten hours (0 to 2 binary)
AM/PM flag:
0 AM
1 PM
format:
0 24 h format, AM/PM flag
remains unchanged
1 12 h format, AM/PM flag
will be updated
Fig.6 Format of the year/date counter.
handbook, full pagewidth
76543210
MSB LSB
MRB003
memory location 05 (year/date)
reset state: 0000 0001
unit days BCD
ten days (0 to 3 binary)
year (0 to 3 binary, read as 0 if
the mask flag is set)
Fig.7 Format of the weekdays/month counter.
handbook, full pagewidth
76543210
MSB LSB
MRB004
memory location 06 (weekdays/months)
reset state: 0000 0001
unit months BCD
ten months
weekdays (0 to 6 binary, read as 0 if
the mask flag is set)
1997 Jul 15 9
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Table 1 Cycle length of the time counters, clock modes
UNIT COUNTING CYCLE CARRY TO NEXT UNIT CONTENTS OF THE
MONTH COUNTER
Hundredths of a second 00 to 99 99 to 00 −
Seconds 00 to 59 59 to 00 −
Minutes 00 to 59 59 to 00 −
Hours (24 h) 00 to 23 23 to 00 −
Hours (12 h) 12 AM −−
01 AM to 11 AM −−
12 PM −−
01 PM to 11 PM 11 PM to 12 AM −
Date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10 and 12
01 to 30 30 to 01 4, 6, 9 and 11
01 to 29 29 to 01 2, year = 0
01 to 28 28 to 01 2, year = 1, 2 and 3
Months 01 to 12 12 to 01 −
Year 0 to 3 −−
Weekdays 0 to 6 6 to 0 −
Timer 00 to 99 no carry −
7.5 Alarm control register
When the alarm enable bit of the control/status register is
set (address 00, bit 2) the alarm control register (address
08) is activated. All alarm, timer, and interrupt output
functions are controlled by the contents of the alarm
control register (see Fig.8).
7.6 Alarm registers
All alarm registers are allocated with a constant address
offset of hexadecimal 08 to the corresponding counter
registers (see Fig.4, Register arrangement).
An alarm signal is generated when the contents of the
alarm registers matches bit-by-bit the contents of the
involved counter registers. The year and weekday bits are
ignored in a dated alarm. A daily alarm ignores the month
and date bits. When a weekday alarm is selected, the
contents of the alarm weekday/month register will select
the weekdays on which an alarm is activated (see Fig.9).
Remark: In the 12 h mode, bits 6 and 7 of the alarm hours
register must be the same as the hours counter.
1997 Jul 15 10
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.8 Alarm control register; clock mode.
handbook, full pagewidth
memory location 08
reset state: 0000 0000
timer function :
000 no timer
001 hundredths of a second
010 seconds
011 minutes
100 hours
101 days
110 not used
111 test mode, all counters
in parallel (factory use only)
timer interrupt enable :
0 timer flag, no interrupt
1 timer flag, interrupt
clock alarm function :
00 no clock alarm
01 daily alarm
10 weekday alarm
11 dated alarm
timer alarm enable :
0 no timer alarm
1 timer alarm
alarm interrupt enable :
(valid only when 'alarm enable' in
control / status register is set
0 alarm flag, no interrupt
1 alarm flag, interrupt
76543210
MSB LSB
MRB005
1997 Jul 15 11
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.9 Selection of alarm weekdays.
handbook, full pagewidth
76543210
MSB LSB
MRB006
memory location 0E (alarm weekday / month)
weekday 0 enabled when set
weekday 1 enabled when set
weekday 2 enabled when set
weekday 3 enabled when set
weekday 4 enabled when set
weekday 5 enabled when set
weekday 6 enabled when set
not used
7.7 Timer
The timer (location 07) is enabled by setting the
control/status register = XX0X X1XX. The timer counts up
from 0 (or a programmed value) to 99. On overflow, the
timer resets to 0. The timer flag (LSB of control/status
register) is set on overflow of the timer. This flag must be
reset by software. The inverted value of this flag can be
transferred to the external interrupt by setting bit 3 of the
alarm control register.
Additionally, a timer alarm can be programmed by setting
the timer alarm enable (bit 6 of the alarm control register).
When the value of the timer equals a pre-programmed
value in the alarm timer register (location 0F), the alarm
flag is set (bit 1 of the control/status register). The inverted
value of the alarm flag can be transferred to the external
interrupt by enabling the alarm interrupt (bit 6 of the alarm
control register).
Resolution of the timer is programmed via the 3 LSBs of
the alarm control register (see Fig.11, Alarm and timer
Interrupt logic diagram).
7.8 Event counter mode
Event counter mode is selected by bits 4 and 5 which are
logic 1, 0 in the control/status register. The event counter
mode is used to count pulses externally applied to the
oscillator input (OSCO left open-circuit).
The event counter stores up to 6 digits of data, which are
stored as 6 hexadecimal values located in locations 1, 2,
and 3. Thus, up to 1 million events may be recorded.
An event counter alarm occurs when the event counter
registers match the value programmed in locations 9, A,
and B, and the event alarm is enabled (bits 4 and 5 which
are logic 0, 1 in the alarm control register). In this event,
the alarm flag (bit 1 of the control/status register) is set.
The inverted value of this flag can be transferred to the
interrupt pin (pin 7) by setting the alarm interrupt enable in
the alarm control register. In this mode, the timer
(location 07) increments once for every one, one-hundred,
ten thousand, or 1 million events, depending on the value
programmed in bits 0, 1 and 2 of the alarm control register.
In all other events, the timer functions are as in the clock
mode.
7.9 Interrupt output
The conditions for activating the open-drain n-channel
interrupt output INT (active LOW) are determined by
appropriate programming of the alarm control register.
These conditions are clock alarm, timer alarm, timer
overflow, and event counter alarm. An interrupt occurs
when the alarm flag or the timer flag is set, and the
corresponding interrupt is enabled. In all events, the
interrupt is cleared only by software resetting of the flag
which initiated the interrupt.
1997 Jul 15 12
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.10 Alarm control register, event-counter mode.
handbook, full pagewidth
memory location 08
reset state: 0000 0000
timer function :
000 no timer
001 units
010 100
011 10 000
100 1 000 000
101 not allowed
110 not allowed
111 test mode, all counters
in parallel
timer interrupt enable :
0 timer flag, no interrupt
1 timer flag, interrupt
clock alarm function :
00 no event alarm
01 event alarm
10 not allowed
11 not allowed
timer alarm enable :
0 no timer alarm
1 timer alarm
alarm interrupt enable :
0 alarm flag, no interrupt
1 alarm flag, interrupt
76543210
MSB LSB
MRB007
In the clock mode, if the alarm enable is not activated
(alarm enable bit of control/status register is logic 0), the
interrupt output toggles at 1 Hz with a 50% duty cycle (may
be used for calibration). This is the default power-on state
of the device. The OFF voltage of the interrupt output may
exceed the supply voltage, up to a maximum of 6.0 V.
A logic diagram of the interrupt output is shown in Fig.11.
7.10 Oscillator and divider
A 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and VDD is used for tuning the oscillator (see quartz
frequency adjustment). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.
In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high impedance state.
This allows the user to feed the 50 Hz reference frequency
or an external high speed event signal into the input OSCI.
7.11 Initialization
When power-up occurs the I2C-bus interface, the
control/status register and all clock counters are reset.
The device starts time-keeping in the 32.768 kHz clock
mode with the 24 h format on the first of January at
0.00.00: 00. A 1 Hz square wave with 50% duty cycle
appears at the interrupt output pin (starts HIGH).
It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.
1997 Jul 15 13
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.11 Alarm and timer interrupt logic diagram.
(1) If the alarm enable bit of the control/status register is reset (logic 0), a 1 Hz signal can be observed on the interrupt pin INT.
handbook, full pagewidth
MBD818
76543210
CONTROL/STATUS
REGISTER (1)
alarm
interrupt timer overflow
interrupt INT
76543210
alarm
control timer
alarm overflow timer
control
clock
alarm
ALARM TIMER
CLOCK/CALENDAR
counter
control
mode
select
MUX oscillator
ALARM
CONTROL
REGISTER
1997 Jul 15 14
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
8 CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
8.1 Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
8.2 Start and stop conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
Fig.12 Bit transfer.
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.13 Definition of start and stop conditions.
MBC622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
1997 Jul 15 15
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
8.3 System configuration (see Fig.14)
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
Fig.14 System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER SLAVE
RECEIVER SLAVE
TRANSMITTER /
RECEIVER MASTER
TRANSMITTER MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
8.4 Acknowledge (see Fig.15)
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
Fig.15 Acknowledgment on the I2C-bus.
MBC602
S
START
CONDITION
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
1997 Jul 15 16
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
9I
2
C-BUS PROTOCOL
9.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the start procedure.
The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal,
but the data signal SDA is a bidirectional line.
The clock/calendar slave address is shown in Fig.16. Bit A0 corresponds to hardware address pin A0. Connecting this
pin to VDD or VSS allows the device to have one of two different addresses.
9.2 Clock/calendar READ/WRITE cycles
The I2C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in Figs 17, 18 and 19.
Fig.16 Slave address.
handbook, halfpage
MRB016
101000A0R/W
group 1 group 2
Fig.17 Master transmits to slave receiver (WRITE) mode.
handbook, full pagewidth
S0ASLAVE ADDRESS WORD ADDRESS A ADATA P
acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave
R/W
auto increment
memory word address
MBD822
n bytes
1997 Jul 15 17
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.18 Master reads after setting word address (write word address; READ data).
handbook, full pagewidth
S0ASLAVE ADDRESS WORD ADDRESS A A
SLAVE ADDRESS
acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave
R/W
acknowledgement
from master
A
DATA
auto increment
memory word address
MBD823
P
no acknowledgement
from master
1DATA
auto increment
memory word address
last byte
R/W
S1
n bytes
at this moment master -
transmitter becomes
master - receiver and
PCF8593 slave - receiver
becomes slave - transmitter
Fig.19 Master reads slave immediately after first byte (READ mode).
handbook, full pagewidth
S1A
SLAVE ADDRESS DATA A1DATA
acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave
R/W
auto increment
word address
MBD824
auto increment
word address
n bytes last bytes
P
1997 Jul 15 18
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
11 HANDLING
Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12
under
“Handling MOS Devices”.
12 DC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS =0V; T
amb =−40 to +85 °C unless otherwise specified.
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage (pin 8) −0.8 +7.0 V
IDD supply current (pin 8) −50 mA
ISS supply current (pin 4) −50 mA
VIinput voltage −0.8 VDD + 0.8 V
IIDC input current −10 mA
IODC output current −10 mA
Ptot total power dissipation per package −300 mW
POpower dissipation per output −50 mW
Tamb operating ambient temperature −40 +85 °C
Tstg storage temperature −65 +150 °C
SYMBOL PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT
VDD supply voltage
(operating mode) I2C-bus active 2.5 −6.0 V
I2C-bus inactive 1.0 −6.0 V
VDDosc supply voltage
(quartz oscillator) Tamb = 0 to 70 °C; note 2 1.0 −6.0 V
IDD supply current
(operating mode) fSCL = 100 kHz; clock mode;
note 3 −−200 µA
IDDO supply current
(clock mode) see Fig.20
fSCL = 0 Hz; VDD = 5 V −10 50 µA
fSCL = 0 Hz; VDD = 1 V −210µA
I
DDR data retention fOSCI = 0 Hz; VDD = 1 V
Tamb = −40 to + 85 °C−−5µA
T
amb = −25 to + 70 °C−−2µA
V
EN I2C-bus enable level note 4 1.5 1.9 2.3 V
SDA
VIL LOW level input voltage note 5 −0.8 −0.3VDD V
VIH HIGH level input voltage note 5 0.7VDD −VDD +0.8 V
IOL LOW level output current VOL = 0.4 V 3 −− mA
ILI input leakage current VI=V
DD or VSS −1−+1 µA
Ciinput capacitance note 6 −−7pF
1997 Jul 15 19
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Notes
1. Typical values measured at Tamb =25°C.
2. When powering-up the device, VDD must exceed 1.5 V until stable operation of the oscillator is established.
3. Event counter mode: supply current dependant upon input frequency.
4. The I2C-bus logic is disabled if VDD <V
EN.
5. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current
must not exceed ±0.5 mA.
6. Tested on sample basis.
A0; OSCI
ILI input leakage current Vl=V
DD or VSS −250 −+250 nA
INT
IOL LOW level output current VOL = 0.4 V 3 −− mA
ILI input leakage current Vl=V
DD or VSS −1−+1 µA
SCL
Ciinput capacitance note 6 −−7pF
I
LI input leakage current VI=V
DD or VSS −1−+1 µA
SYMBOL PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT
Fig.20 Typical supply current in clock mode as a function of supply voltage.
handbook, halfpage
0
12
8
4
0246
MRB012
IDDO
(µA)
V (V)
DD
fSCL = 32 kHz; Tamb =25°C.
1997 Jul 15 20
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
13 AC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb =−40 to +85 °C; unless otherwise specified.
Notes
1. Event counter mode only.
2. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL
and VIH with an input voltage swing of VSS to VDD.
3. A detailed description of the I2C-bus specification, with applications, is given in brochure
“The I
2
C-bus and how to
use it”
. This brochure may be ordered using the code 9398 393 40011.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Oscillator
Cosc integrated oscillator
capacitance −40 −pF
∆fosc oscillator stability for ∆VDD = 100 mV;
Tamb =25°C; VDD = 1.5 V −2×10−7−
fiinput frequency note 1 −−1 MHz
Quartz crystal parameters (f = 32.768 kHz)
Rsseries resistance −−40 kΩ
CLparallel load capacitance −10 −pF
CTtrimmer capacitance 5 −25 pF
I2C-bus timing (see Fig.21; notes 2 and 3)
fSCL SCL clock frequency −−100 kHz
tSP tolerable spike width on bus −−100 ns
tBUF bus free time 4.7 −−µs
t
SU;STA START condition set-up time 4.7 −−µs
t
HD;STA START condition hold time 4.0 −−µs
t
LOW SCL LOW time 4.7 −−µs
t
HIGH SCL HIGH time 4.0 −−µs
t
rSCL and SDA rise time −−1.0 µs
tfSCL and SDA fall time −−0.3 µs
tSU;DAT data set-up time 250 −−ns
tHD;DAT data hold time 0 −−ns
tVD;DAT SCL LOW to data out valid −−3.4 µs
tSU;STO STOP condition set-up time 4.0 −−µs
1997 Jul 15 21
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
Fig.21 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
handbook, full pagewidth
PROTOCOL
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO
tf
r
t
tBUF
tSU;STA tLOW tHIGH 1 / fSCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6) ACKNOWLEDGE
(A) STOP
CONDITION
(P)
14 APPLICATION INFORMATION
14.1 Quartz frequency adjustment
14.1.1 METHOD 1: FIXED OSCI CAPACITOR
By evaluating the average capacitance necessary for the
application layout a fixed capacitor can be used.
The frequency is best measured via the 1 Hz signal
available after power-on at the interrupt output (pin 7).
The frequency tolerance depends on the quartz crystal
tolerance, the capacitor tolerance and the
device-to-device tolerance (on average ±5×10−6).
Average deviations of ±5 minutes per year can be
achieved.
14.1.2 METHOD 2: OSCI TRIMMER
Using the alarm function (via the I2C-bus) a signal faster
than 1 Hz can be generated at the interrupt output for fast
setting of a trimmer.
Procedure:
•Power-on
•Initialization (alarm functions).
Routine:
•Set clock to time T and set alarm to time T +dT
•At time T +dT (interrupt) repeat routine.
14.1.3 METHOD 3:
Direct measurement of OSC out (accounting for test probe
capacitance).
The PCF8583 slave address has a fixed combination 1010
as group 1.
1997 Jul 15 22
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
handbook, full pagewidth
MRB018
SCL
A0
SDA
VSS
OSCI
OSCO
CLOCK
CALENDAR
PCF8583
'1010'
SDA
SCL
MASTER
TRANSMITTER
VDD
VDD
SCL
A0
1
SDA
VSS
OSCI
OSCO
EVENT
COUNTER
PCF8583
'1010'
VDD
VDD
SDA SCL
RR
V
DD
(I C-bus)
2
R: pull-up resistor
R = trise / C-bus
Fig.22 Application diagram.
1997 Jul 15 23
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
15 PACKAGE OUTLINES
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT97-1 92-11-17
95-02-04
UNIT A
max. 12 b
1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.14 0.53
0.38 0.36
0.23 9.8
9.2 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 1.154.2 0.51 3.2
inches 0.068
0.045 0.021
0.015 0.014
0.009
1.07
0.89
0.042
0.035 0.39
0.36 0.26
0.24 0.14
0.12 0.010.10 0.30 0.32
0.31 0.39
0.33 0.0450.17 0.020 0.13
b2
050G01 MO-001AN
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
8
1
5
4
b
E
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
pin 1 index
DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1
1997 Jul 15 24
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
UNIT A
max. A1A2A3bpcD
(1) E(1) Z(1)
eH
ELL
pQywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 7.65
7.45 7.6
7.4 1.27 10.65
10.00 1.1
1.0 2.0
1.8 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.45
SOT176-1 95-02-25
97-05-22
X
4
8
θ
A
A1
A2
wM
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
5
1
(A )
3
A
y
0.25
0.10 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.30
0.29 0.30
0.29 0.050
1.45
0.057
0.25
0.01
0.419
0.394 0.043
0.039 0.079
0.071
0.01 0.004
0.043
0.018
0.01
0 5 10 mm
scale
pin 1 index
SO8: plastic small outline package; 8 leads; body width 7.5 mm SOT176-1
1997 Jul 15 25
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
16 SOLDERING
16.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
16.2 DIP
16.2.1 SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
16.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
16.3 SO
16.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
16.3.2 WAVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
•The longitudinal axis of the package footprint must be
parallel to the solder flow.
•The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
16.3.3 REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Jul 15 26
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
17 DEFINITIONS
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jul 15 27
Philips Semiconductors Product specification
Clock/calendar with 240 ×8-bit RAM PCF8583
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
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Printed in The Netherlands 417067/00/05/pp28 Date of release: 1997 Jul 15 Document order number: 9397 750 02588
