LTC2000A
1
2000afb
For more information www.linear.com/LTC2000A
BLOCK DIAGRAM
FEATURES DESCRIPTION
16-/14-/11-Bit 2.7Gsps
DACs
The LTC
®
2000A is a family of 16-/14-/11-bit 2.7Gsps
current steering DACs with exceptional spectral purity.
The single (1.35Gsps mode) or dual (2.7Gsps mode) port
source synchronous LVDS interface supports data rates of
up to 1.35Gbps using a 675MHz DDR data clock, which
can be either in quadrature or in phase with the data. An
internal synchronizer automatically aligns the data with
the DAC sample clock.
Additional features such as pattern generation, LVDS
loopout and junction temperature sensing simplify system
development and testing.
A serial peripheral interface (SPI) port allows configura-
tion and read back of internal registers. Operating from
1.86V and 3.3V supplies, the LTC2000A consumes 2.41W
at 2.7Gsps and 1.43W at 1.35Gsps.
APPLICATIONS
n 80dBc SFDR at 50MHz fOUT
n >68dBc SFDR from DC to 1080MHz fOUT
n 40mA Nominal Full-Scale, ±1V Output Compliant
n 10mA to 60mA Adjustable Full-Scale Current Range
n Single or Dual Port DDR LVDS and DHSTL Interface
n Low Latency (7.5 Cycles for Single Port,
11 Cycles for Dual Port)
n >78dBc 2-Tone IMD from DC to 1000MHz fOUT
n –156dBc/Hz Additive Phase Noise at 1MHz Offset for
65MHz fOUT
n 170-Lead (9mm × 15mm) BGA Package
n Broadband Communication Systems
n DOCSIS CMTS
n Direct RF Synthesis
n Radar
n Instrumentation
n Automatic Test Equipment
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 8330633.
LVDS RECEIVERS
DDR DATA FLIP-FLOPS
4:1
TSTP/N PD CS SCK SDI SDO SVDD
50Ω
IOUTP
IOUTN
FSADJ
REFIO
50Ω
10k
2000A BD
CKP/NGNDDVDD33
DVDD18 AVDD33
AVDD18
GAIN
ADJUST
CLOCK
SYNC
CLK
RECEIVER
DELAY
ADJUST
DCKOP/N
DCKIP/N
DBP/N[15:0]
DAP/N[15:0]
CLK DIVIDER
÷2 OR ÷4
REF
SPI
PATTERN
GENERATOR
JUNCTION
TEMPERATURE
16-BIT DAC
fOUT (MHz)
0
50
SFDR (dBc)
60
70
80
90
100
200 400 600 800
2000A TA01b
1000 1200
DIGITAL AMPLITUDE = 0dBFS
IOUTFS = 40mA
SFDR vs fOUT, fDAC = 2.7Gsps
LTC2000A
2
2000afb
For more information www.linear.com/LTC2000A
TABLE OF CONTENTS
Features ..................................................... 1
Applications ................................................ 1
Block Diagram .............................................. 1
Description.................................................. 1
Absolute Maximum Ratings .............................. 3
Pin Configuration .......................................... 3
Order Information .......................................... 4
Electrical Characteristics ................................. 5
Timing Characteristics .................................... 8
Typical Performance Characteristics ................... 9
Pin Functions .............................................. 16
Block Diagram ............................................. 17
Timing Diagrams ......................................... 18
Operation................................................... 18
Introduction ............................................................ 18
Dual-Port Mode ...................................................... 19
Single-Port Mode .................................................... 19
Serial Peripheral Interface (SPI) .............................22
Power-On Reset ......................................................22
Power Down ...........................................................22
Reference Operation ...............................................22
Setting the Full-Scale Current .................................23
DAC Transfer Function ............................................ 24
Analog Outputs (IOUTP/N) ........................................24
DAC Sample Clock (CKP/N) ....................................25
Divided Clock Output (DCKOP/N) ............................25
LVDS Data Clock Input (DCKIP/N) ..........................25
LVDS Data Input Ports (DAP/N, DBP/N) .................26
Clock Synchronizer .................................................27
Minimizing Harmonic Distortion .............................29
Measuring LVDS Input Timing Skew .......................29
Measuring Internal Junction Temperature (TJ) .......32
Pattern Generator ...................................................32
SPI Register Summary ................................... 33
Applications Information ................................ 34
Sample Start-Up Sequence .....................................34
Output Configurations ...........................................35
Generating the DAC Sample Clock ..........................35
Synchronizing Multiple LTC2000As in Dual-Port
Mode ......................................................................36
Synchronizing Multiple LTC2000As in Single-Port
Mode ......................................................................38
PCB Layout Considerations ....................................40
Pin Locations (LTC2000A-16) ...........................45
Pin Locations (LTC2000A-14) ...........................47
Pin Locations (LTC2000A-11) ...........................49
Package Description ..................................... 51
Typical Application ....................................... 52
Related Parts .............................................. 52
LTC2000A
3
2000afb
For more information www.linear.com/LTC2000A
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
AVDD33, DVDD33, SVDD ................................. –0.3V to 4V
AVDD18, DVDD18............................................ –0.3V to 2V
IOUTP, IOUTN .................–1.2V to Min (AVDD33 + 0.3V, 4V)
FSADJ, REFIO ............ –0.3V to Min (AVDD33 + 0.3V, 4V)
DCKIP, DCKIN ............–0.3V to Min (DVDD33 + 0.3V, 4V)
DCKOP, DCKON ..........–0.3V to Min (DVDD33 + 0.3V, 4V)
DAP/N, DBP/N ............–0.3V to Min (DVDD33 + 0.3V, 4V)
TSTP, TSTN ................ –0.3V to Min (AVDD33 + 0.3V, 4V)
(Notes 1, 2)
LTC2000A-16 LTC2000A-14 LTC2000A-11
1
S
R
Q
P
N
M
L
K
J
H
GND
GND
DVDD33
AVDD33
GND
G
F
E
D
C
B
A
2345678910
BGA PACKAGE
170-LEAD (9mm × 15mm × 1.54mm)
TOP VIEW
AVDD18
DVDD18
TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W,
θJCtop = 9°C/W, θJCbottom = 3°C/W
1
S
R
Q
P
N
M
L
K
J
H
DVDD33
AVDD18
GND
GND
GND
G
F
E
D
C
B
A
2345678910
BGA PACKAGE
170-LEAD (9mm × 15mm × 1.54mm)
TOP VIEW
AVDD33
DVDD18
TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W,
θJCtop = 9°C/W, θJCbottom = 3°C/W
1
S
R
Q
P
N
M
L
K
J
H
GND
GND
DVDD33
AVDD18
GND
G
F
E
D
C
B
A
2345678910
BGA PACKAGE
170-LEAD (9mm × 15mm × 1.54mm)
TOP VIEW
AVDD33
DVDD18
TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W,
θJCtop = 9°C/W, θJCbottom = 3°C/W
CKP, CKN ................... –0.3V to Min (AVDD18 + 0.3V, 2V)
CS, PD, SCK, SDI, SDO ...–0.3V to Min (SVDD + 0.3V, 4V)
Operating Temperature Range
LTC2000AC .............................................. 0°C to 70°C
LTC2000AI ...........................................–40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range .................. –55°C to 125°C
Lead Temperature (Soldering, 10 sec) ...................260°C
LTC2000A
4
2000afb
For more information www.linear.com/LTC2000A
ORDER INFORMATION
LTC2000A C Y –16 #PBF
LEAD FREE DESIGNATOR
PBF = Lead Free
RESOLUTION
16 = 16-Bit Resolution
14 = 14-Bit Resolution
11 = 11-Bit Resolution
PACKAGE TYPE
170-Lead (15mm × 9mm × 1.54mm) BGA
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
PRODUCT PART NUMBER
PART NUMBER BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE
LTC2000ACY-16#PBF SAC305 (RoHS) LTC2000Y-16 BGA 3 0°C to 70°C
LTC2000ACY-14#PBF SAC305 (RoHS) LTC2000Y-14 BGA 3 0°C to 70°C
LTC2000ACY-11#PBF SAC305 (RoHS) LTC2000Y-11 BGA 3 0°C to 70°C
LTC2000AIY-16#PBF SAC305 (RoHS) LTC2000Y-16 BGA 3 –40°C to 85°C
LTC2000AIY-14#PBF SAC305 (RoHS) LTC2000Y-14 BGA 3 –40°C to 85°C
LTC2000AIY-11#PBF SAC305 (RoHS) LTC2000Y-11 BGA 3 –40°C to 85°C
LTC2000AIY-16 Sn/Pb LTC2000Y-16 BGA 3 –40°C to 85°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC2000A#orderinfo
LTC2000A
5
2000afb
For more information www.linear.com/LTC2000A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.8V to 1.92V, AVDD33, DVDD33 = 3.135V to 3.465V,
SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Performance
Resolution LTC2000A-16 l16 Bits
LTC2000A-14 l14 Bits
LTC2000A-11 l11 Bits
DNL Differential Nonlinearity LTC2000A-16 l±0.5 ±2.7 LSB
LTC2000A-14 l±0.2 ±1 LSB
LTC2000A-11 l±0.1 ±0.5 LSB
INL Integral Nonlinearity LTC2000A-16 l±1 ±4 LSB
LTC2000A-14 l±0.5 ±2 LSB
LTC2000A-11 l±0.2 ±1 LSB
Offset Error LTC2000A-16 l±0.05 % FSR
LTC2000A-14 l±0.06 % FSR
LTC2000A-11 l±0.09 % FSR
Offset Error Drift 1 ppm/°C
Gain Error ±0.5 % FSR
Gain Error Drift 5 ppm/°C
Power Supply Rejection Ratio Full-Scale; AVDD33 = 3.135V to 3.465V 69 dB
Analog Output
Full-Scale Output Current RFSADJ = 500Ω 40 mA
Output Compliance Range l–1 1 V
Output Resistance IOUTP/N to GND l42 50 58 Ω
Output Capacitance 6 pF
Output Bandwidth RIOUTP/N = 12.5Ω, –3dB Excluding sin(x)/x 2.1 GHz
AC Performance
Maximum Update Rate Dual-Port Mode
Single-Port Mode
l
l
2.7
1.35
Gsps
Gsps
SFDR Spurious Free Dynamic Range
fDAC = 1.25Gsps, 0dBFS
fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75%
82
82
74
74
dBc
dBc
dBc
dBc
Spurious Free Dynamic Range
fDAC = 2.7Gsps, 0dBFS
fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 200MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75%
l
67
75
72
75
72
dBc
dBc
dBc
dBc
fOUT = 500MHz, LIN_DIS = 1
fOUT = 1000MHz, LIN_DIS = 1
67
61
dBc
dBc
IMD 2-Tone Intermodulation Distortion
fOUT2 = fOUT1 + 1.25MHz
fDAC = 1.25Gsps, –6dBFS
fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75%
103
93
97
84
dBc
dBc
dBc
dBc
2-Tone Intermodulation Distortion
fOUT2 = fOUT1 + 1.25MHz
fDAC = 2.7Gsps, –6dBFS
fOUT = 100MHz, LIN_DIS = 1
fOUT = 200MHz, LIN_DIS = 1
fOUT = 500MHz, LIN_DIS = 1
fOUT = 1000MHz, LIN_DIS = 1
87
86
82
80
dBc
dBc
dBc
dBc
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75%
fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75%
79
68
dBc
dBc
LTC2000A
6
2000afb
For more information www.linear.com/LTC2000A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.8V to 1.92V, AVDD33, DVDD33 = 3.135V to 3.465V,
SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
NSD Noise Spectral Density
0dBFS Single Tone, fDAC = 2.7Gsps,
IOUTFS = 40mA
LTC2000A-16, fOUT = 100MHz
LTC2000A-16, fOUT = 350MHz
LTC2000A-16, fOUT = 550MHz
LTC2000A-16, fOUT = 950MHz
–164
–158
–155
–153
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
LTC2000A-14, fOUT = 100MHz
LTC2000A-14, fOUT = 350MHz
LTC2000A-14, fOUT = 550MHz
LTC2000A-14, fOUT = 950MHz
–163
–158
–155
–153
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
LTC2000A-11, fOUT = 100MHz
LTC2000A-11, fOUT = 350MHz
LTC2000A-11, fOUT = 550MHz
LTC2000A-11, fOUT = 950MHz
–156
–154
–153
–150
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
Phase Noise
fDAC = 2.7Gsps, fOUT = 65MHz
0dBFS Single Tone, IOUTFS = 40mA
10kHz Offset
1MHz Offset
–141
–156
dBc/Hz
dBc/Hz
WCDMA
ACLR
WCDMA ACLR (Single Carrier)
Adjacent/Alternate Adjacent Channel
fDAC = 2.7Gsps, fOUT = 350MHz
fDAC = 2.7Gsps, fOUT = 950MHz
78/79
72/75
dBc
dBc
Latency
Latency (Note 5) Single-Port Mode
Dual-Port Mode, DAP/N Data
Dual-Port Mode, DBP/N Data
7.5
10
11
Cycles
Cycles
Cycles
Aperture Delay CKP/N Rising to IOUTP/N Transition 3 ns
Settling Time ±0.1% FSR, Full-Scale Step 2.2 ns
Reference
Output Voltage l1.225 1.25 1.275 V
Input Voltage l1.1 1.4 V
Reference Temperature Coefficient ±25 ppm/°C
Output Impedance 10 kΩ
DAC Clock Inputs (CKP, CKN)
Differential Input Voltage Range l±0.3 ±1.8 V
Common-Mode Input Voltage Set Internally 1 V
Sampling Clock Frequency l50 2700 MHz
Input Impedance 5 kΩ
LVDS Inputs (DCKIP, DCKIN, DAP/N, DBP/N)
Differential Input Voltage Range l±0.2 ±0.6 V
Common-Mode Voltage Range l0.4 1.8 V
Differential Input Impedance l95 120 145 Ω
Maximum Data Rate l1350 Mbps
LVDS Clock Frequency l25 675 MHz
LTC2000A
7
2000afb
For more information www.linear.com/LTC2000A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.8V to 1.92V, AVDD33, DVDD33 = 3.135V to 3.465V,
SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LVDS Output (DCKOP, DCKON)
Differential Output Voltage 100Ω Differential Load, DCKO_ISEL = 0
50Ω Differential Load, DCKO_ISEL = 1
l
l
0.24
0.24
0.36
0.36
0.48
0.48
V
V
Common-Mode Output Voltage l1.075 1.2 1.325 V
Internal Termination Resistance DCKO_TRM = 1 100 Ω
CMOS Digital Inputs (CS, PD, SCK, SDI)
VIH Digital Input High Voltage l70 %VSVDD
VIL Digital Input Low Voltage l30 %VSVDD
ILK Digital Input Leakage VIN = GND or SVDD l±10 µA
CIN Digital Input Capacitance 8 pF
CMOS Digital Output (SDO)
VOH Digital Output High Voltage ISOURCE = 0.2mA l85 %VSVDD
VOL Digital Output Low Voltage ISINK = 1.6mA l15 %VSVDD
Hi-Z Output Leakage l±10 µA
Hi-Z Output Capacitance 8 pF
Power Supply
VVDD33 AVDD33, DVDD33 Supply Voltage l3.135 3.3 3.465 V
VVDD18 AVDD18, DVDD18 Supply Voltage l1.8 1.86 1.92 V
VSVDD SVDD SPI Supply Voltage l1.71 3.465 V
IAVDD33 AVDD33 Supply Current, AVDD33 = 3.3V PD = SVDD
PD = GND
l
l
68
0.1
78
10
mA
µA
IDVDD33 DVDD33 Supply Current, DVDD33 = 3.3V PD = SVDD
PD = GND
l
l
8
0.1
14
5
mA
µA
IAVDD18 AVDD18 Supply Current, AVDD18 = 1.86V fDAC = 2700MHz
fDAC = 1350MHz
fDAC = 0Hz, PD = SVDD
fDAC = 0Hz, PD = GND
l
l
l
l
780
425
23
3
870
480
27
180
mA
mA
mA
µA
IDVDD18 DVDD18 Supply Current, DVDD18 = 1.86V fDAC = 2700MHz
fDAC = 1350MHz
fDAC = 0Hz, PD = SVDD
fDAC = 0Hz, PD = GND
l
l
l
l
380
210
10
0.1
440
240
14
240
mA
mA
mA
µA
ISVDD SVDD Supply Current (Note 4),
SVDD = 3.3V
fSCK = 0Hz l0.1 5 µA
Total Power Dissipation fDAC = 2700MHz
fDAC = 1350MHz
fDAC = 0Hz, PD = SVDD
fDAC = 0Hz, PD = GND
2408
1432
312
6
mW
mW
mW
µW
LTC2000A
8
2000afb
For more information www.linear.com/LTC2000A
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.8V to 1.92V, AVDD33, DVDD33 = 3.135V to 3.465V, SVDD = 1.71V
to 3.465V, RFSADJ = 500Ω, output load 50Ω double terminated, unless otherwise specified.
TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t1SDI Valid to SCK Setup (Note 3) l4 ns
t2SDI Valid to SCK Hold (Note 3) l4 ns
t3SCK High Time (Note 3) l9 ns
t4SCK Low Time (Note 3) l9 ns
t5CS Pulse Width (Note 3) l10 ns
t6SCK High to CS High (Note 3) l7 ns
t7CS Low to SCK High (Note 3) l7 ns
t10 CS High to SCK High (Note 3) l7 ns
t13 SCK Low to SDO Valid Unloaded (Note 3) l10 ns
SCK Frequency 50% Duty Cycle (Note 3) l50 MHz
t11 LVDS DAP/N, DBP/N to DCKI Setup Time
(Note 3)
DCKI_Q = 1
DCKI_Q = 0, DCKI_TADJ = 000
l
l
200
570
ps
ps
t12 LVDS DAP/N, DBP/N to DCKI Hold Time
(Note 3)
DCKI_Q = 1
DCKI_Q = 0, DCKI_TADJ = 000
l
l
200
–170
ps
ps
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: Guaranteed by design and not production tested.
Note 4: Digital inputs at 0V or SVDD.
Note 5: Latency is the delay from a transition on DCKIP/N until the CKP/N
transition which causes the sample on DAP/N or DBP/N to appear at the
DAC output IOUTP/N, as measured in DAC sample clock (CKP/N) cycles.
LTC2000A
9
2000afb
For more information www.linear.com/LTC2000A
TYPICAL PERFORMANCE CHARACTERISTICS
DNL vs IOUTFS and Temperature Offset Error vs Temperature Gain Error vs Temperature
Reference Output Voltage
vs Temperature Supply Current vs fDAC
Shutdown Current
vs Temperature
LTC2000A-16 Integral
Nonlinearity (INL)
LTC2000A-16 Differential
Nonlinearity (DNL) INL vs IOUTFS and Temperature
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, unless otherwise noted.
CODE
–32768
INL (LSB)
0
2
32768
2000A G01
–2
–4 –16384 016384
4
CODE
–32768
DNL (LSB)
0
1
32768
2000A G02
–1
–2 –16384 016384
2
TEMPERATURE (°C)
–50
–6
INL (LSB)
–4
–2
0
2
6
–25 0 25 50
2000A G03
75 100
4
INL (POS)
INL (NEG)
10mA
20mA
40mA
60mA
TEMPERATURE (°C)
–50
–6
DNL (LSB)
–4
–2
0
2
6
–25 0 25 50
2000A G04
75 100
4
DNL (POS)
DNL (NEG)
10mA
20mA
40mA
60mA
TEMPERATURE (°C)
–50
–1.0
GAIN ERROR (% FSR)
–0.5
0
0.5
1.0
–25 0 25 50
2000A G06
75 100
TEMPERATURE (°C)
–50
1.240
VREF (V)
1.245
1.250
1.255
1.260
–25 0 25 50
2000A G07
75 100
fDAC (MHz)
0
I (mA)
300
400
500
1500 2500
2000A G08
200
100
0500 1000 2000
600
700
800
DVDD33
AVDD33
DVDD18
AVDD18
TEMPERATURE (°C)
–50
–0.06
OFFSET ERROR (%FSR)
–0.04
–0.02
0
0.02
0.06
–25 0 25 50
2000A G05
75 100
0.04
16 BIT
14 BIT
11 BIT
TEMPERATURE (°C)
–50
I (µA)
15
2000A G09
5
–5 0 50
–25 25 75
25
35
10
0
20
30
100
DVDD18
AVDD18
SVDD
AVDD33
DVDD33
LTC2000A
10
2000afb
For more information www.linear.com/LTC2000A
TYPICAL PERFORMANCE CHARACTERISTICS
SFDR vs fOUT and Temperature,
fDAC = 2.7Gsps
SFDR vs fOUT and Digital
Amplitude (dBFS), fDAC = 2.7Gsps
SFDR vs fOUT and IOUTFS,
fDAC = 2.7Gsps
HD2 vs fOUT and fDAC HD3 vs fOUT and fDAC
Single-Tone Spectrum at
fOUT = 70MHz, fDAC = 2.7Gsps
Single-Tone Spectrum at
fOUT = 990MHz, fDAC = 2.7Gsps SFDR vs fOUT and fDAC
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.
FREQUENCY (MHz)
20
–90
10dB/DIV
–80
–60
–50
–40
1092 2164 2700
0
2000A G10
–70
556 1628
–30
–20
–10
RBW = 2kHz, VBW = 5kHz
REF = 5dBm, ATTEN = 25dB
SWEEP = 620s (1001 PTS)
fDAC-fOUT
IMAGE
FREQUENCY (MHz)
20
–90
10dB/DIV
–80
–60
–50
–40
1092 2164 2700
0
2000A G11
–70
556 1628
–30
–20
–10 RBW = 2kHz
VBW = 5kHz
REF = 5dBm
ATTEN = 25dB
SWEEP = 620s
(1001 PTS)
HD3
fDAC-fOUT
IMAGE
HD2 AND HD3
IN 2ND
NYQUIST BAND
fOUT (MHz)
0
50
SFDR (dBc)
60
70
80
90
100
200 400 600 800
2000A G12
1000 1200
2.7Gsps
2.0Gsps
1.6Gsps
1.25Gsps
DIGITAL AMPLITUDE = 0dBFS
fOUT (MHz)
0
50
SFDR (dBc)
60
70
80
90
100
200 400 600 800
2000A G13
1000 1200
85°C
25°C
–40°C
DIGITAL AMPLITUDE = 0dBFS
fOUT (MHz)
0
50
SFDR (dBc)
60
70
80
90
100
200 400 600 800
2000A G14
1000 1200
0dBFS
–3dBFS
–6dBFS
–12dBFS
–16dBFS
fOUT (MHz)
0
50
SFDR (dBc)
60
70
80
90
100
200 400 600 800
2000A G15
1000 1200
60mA
40mA
20mA
10mA
fOUT (MHz)
0
50
HD2 (dBc)
60
70
80
90
100
200 400 600 800
2000A G16
1000 1200
2.7Gsps
2.0Gsps
1.6Gsps
1.25Gsps
DIGITAL AMPLITUDE = 0dBFS
fOUT (MHz)
0
50
HD3 (dBc)
60
70
80
90
100
200 400 600 800
2000A G17
1000 1200
2.7Gsps
2.0Gsps
1.6Gsps
1.25Gsps
DIGITAL AMPLITUDE = 0dBFS
HD2 vs fOUT and Digital Amplitude
(dBFS), fDAC = 2.7Gsps
fOUT (MHz)
0
50
HD2 (dBc)
60
70
80
90
100
200 400 600 800
2000A G18
1000 1200
0dBFS
–3dBFS
–6dBFS
–12dBFS
–16dBFS
LTC2000A
11
2000afb
For more information www.linear.com/LTC2000A
TYPICAL PERFORMANCE CHARACTERISTICS
2-Tone IMD vs fOUT and fDAC
2-Tone IMD vs fOUT and Digital
Amplitude, fDAC = 2.7Gsps
SFDR vs fOUT and Linearization
Setting, fDAC = 2.7Gsps
LTC2000A-16 Single-Tone NSD
vs fOUT and fDAC
LTC2000A-16 Single-Tone NSD
vs fOUT and IOUTFS
HD3 vs fOUT and Linearization
Setting, fDAC = 2.7Gsps
2-Tone IMD vs fOUT and
Linearization Setting,
fDAC = 2.7Gsps
HD3 vs fOUT and Digital Amplitude
(dBFS), fDAC = 2.7Gsps
2-Tone IMD vs fOUT and fDAC with
Default Linearization
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.
fOUT (MHz)
0
50
HD3 (dBc)
60
70
80
90
100
200 400 600 800
2000A G19
1000 1200
0dBFS
–3dBFS
–6dBFS
–12dBFS
–16dBFS
fOUT (MHz)
0
60
IMD (dBc)
70
80
90
100
110
200 400 600 800
2000A G22
1000 1200
2.7Gsps
2.0Gsps
1.6Gsps
1.25Gsps
DIGITAL AMPLITUDE = –6dBFS
F2 = F1 + 1.25MHz
LIN_DIS = 0
LIN_GN = 75%
fOUT (MHz)
0
50
HD3 (dBc)
60
70
80
90
100
200 400 600 800
2000A G25
1000 1200
LIN_GN = 100%
LIN_GN = 75%
LIN_GN = 50%
LIN_DIS = 1
DIGITAL AMPLITUDE = 0dBFS
fOUT (MHz)
0
60
IMD (dBC)
70
80
90
100
110
200 400 600 800
2000A G20
1000 1200
2.7Gsps
2.0Gsps
1.6Gsps
1.25Gsps
DIGITAL AMPLITUDE = –6dBFS
F2 = F1 + 1.25MHz
LIN_DIS = 1
fOUT (MHz)
0
60
IMD (dBC)
70
80
90
100
110
200 400 600 800
2000A G21
1000 1200
0dBFS
–6dBFS
–12dBFS
–16dBFS
F2 = F1 + 1.25MHz
LIN_DIS = 1
fOUT (MHz)
0
–170
NSD (dBm/Hz)
–165
–160
–155
–150
–145
200 400 600 800
2000A G26
1000 1200
DIGITAL AMPLITUDE = 0dBFS
40mA FULL-SCALE CURRENT
0dBm SINGLE-TONE
2.7Gsps
1.25Gsps
fOUT (MHz)
0
60
IMD (dBC)
70
80
90
100
110
200 400 600 800
2000A G23
1000 1200
LIN_GN = 100%
LIN_GN = 75%
LIN_GN = 50%
LIN_DIS = 1
DIGITAL AMPLITUDE = –6dBFS
F2 = F1 + 1.25MHz
fOUT (MHz)
0
–170
NSD (dBm/Hz)
–165
–160
–155
–150
60mA
40mA
20mA
–145
200 400 600 800
2000A G27
1000 1200
DIGITAL AMPLITUDE = 0dBFS
fDAC = 2.7Gsps
12.5Ω TOTAL OUTPUT LOAD
fOUT (MHz)
0
50
SFDR (dBc)
60
70
80
90
100
200 400 600 800
2000A G24
1000 1200
LIN_GN = 100%
LIN_GN = 75%
LIN_GN = 50%
LIN_DIS = 1
DIGITAL AMPLITUDE = 0dBFS
LTC2000A
12
2000afb
For more information www.linear.com/LTC2000A
Single Carrier DOCSIS Mid Band
Wideband ACLR, fDAC = 2.7Gsps
Single Carrier DOCSIS Mid Band
Narrowband ACLR, fDAC = 2.7Gsps
Single Carrier DOCSIS Low Band
Wideband ACLR, fDAC = 2.7Gsps
Single Carrier DOCSIS Low Band
Narrowband ACLR, fDAC = 2.7Gsps
TYPICAL PERFORMANCE CHARACTERISTICS
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.
FREQUENCY (MHz)
50
10dB/DIV
–60
–40
–20
850
2000A G28
–80
–100
–70
–50
–30
–90
–110
–120 250 450 650
150 350 550 750 950 1050
RBW = 20kHz
VBW = 2kHz
REF = –20dBm
ATTEN = 5dB
SWEEP = 60s
–11.4dBm/6MHz
–87.2dBm/6MHz
–90.1dBm/6MHz
–88.9dBm/6MHz
FREQUENCY (MHz)
CARRIER POWER = –11.40dBm, CENTER FREQ = 200MHz
173
10dB/DIV
–60
–40
–20
213
2000A G31
–80
–100
–70
–50
–30
–90
–110
–120 183 193 203 223
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–99.97dBm
–95.69dBm
–96.89dBm
–96.68dBm
–96.19dBm
UPPER
–95.33dBm
–95.18dBm
–95.80dBm
–96.60dBm
–95.94dBm
RBW = 30kHz
VBW = 3kHz
REF = –20dBm
ATTEN = 5dB
SWEEP = 24s
FREQUENCY (MHz)
50
10dB/DIV
–60
–40
–20
850
2000A G29
–80
–100
–70
–50
–30
–90
–110
–120 250 450 650
150 350 550 750 950 1050
–11.8dBm/6MHz RBW = 20kHz
VBW = 2kHz
REF = –20dBm
ATTEN = 5dB
SWEEP = 60s
–84.4dBm/6MHz
FREQUENCY (MHz)
CARRIER POWER = –11.85dBm, CENTER FREQ = 550MHz
523
10dB/DIV
–60
–40
–20
563
2000A G32
–80
–100
–70
–50
–30
–90
–110
–120 533 543 553 573
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–95.92dBm
–91.68dBm
–94.58dBm
–94.54dBm
–94.17dBm
UPPER
–92.58dBm
–91.81dBm
–94.33dBm
–94.36dBm
–94.16dBm
RBW = 30kHz
VBW = 3kHz
REF = –20dBm
ATTEN = 5dB
SWEEP = 24s
Single Carrier DOCSIS High Band
Wideband ACLR, fDAC = 2.7Gsps
FREQUENCY (MHz)
50
10dB/DIV
–60
–40
–20
850
2000A G30
–80
–100
–70
–50
–30
–90
–110
–120 250 450 650
150 350 550 750 9501050
–88.5dBm/6MHz
–86.7dBm/6MHz
RBW = 20kHz
VBW = 2kHz
REF = –20dBm
ATTEN = 5dB
SWEEP = 60s
–83.4dBm/6MHz
–13.9dBm/6MHz
Single Carrier DOCSIS High Band
Narrowband ACLR, fDAC = 2.7Gsps
FREQUENCY (MHz)
CARRIER POWER = –13.95dBm, CENTER FREQ = 980MHz
953
10dB/DIV
–60
–40
–20
993
2000A G33
–80
–100
–70
–50
–30
–90
–110
–120 963 973 983 1003
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–89.76dBm
–87.24dBm
–92.87dBm
–93.36dBm
–92.65dBm
UPPER
–90.00dBm
–86.24dBm
–92.16dBm
–92.29dBm
–91.52dBm
RBW = 30kHz
VBW = 3kHz
REF = –20dBm
ATTEN = 5dB
SWEEP = 24s
LTC2000A-16
LTC2000A
13
2000afb
For more information www.linear.com/LTC2000A
32 Carrier DOCSIS Mid Band
Narrowband ACLR, fDAC = 2.7Gsps
32 Carrier DOCSIS High Band
Wideband ACLR, fDAC = 2.7Gsps
32 Carrier DOCSIS High Band
Narrowband ACLR, fDAC = 2.7Gsps
32-Carrier DOCSIS Low Band
Wideband ACLR, fDAC = 2.7Gsps
32-Carrier DOCSIS Low Band
Narrowband ACLR, fDAC = 2.7Gsps
32-Carrier DOCSIS Mid Band
Wideband ACLR, fDAC = 2.7Gsps
FREQUENCY (MHz)
50
10dB/DIV
–60
–40
850
2000A G34
–80
–100
–70
–50
–30
–90
–110
–120
–130 250 450 650
150 350 550 750 950 1050
RBW = 20kHz
VBW = 2kHz
REF = –30dBm
ATTEN = 5dB
SWEEP = 60s
FREQUENCY (MHz)
CARRIER POWER = –28.77dBm, CENTER FREQ = 386MHz
359
10dB/DIV
–60
–40
399
2000A G37
–80
–100
–70
–50
–30
–90
–110
–120
–130 369 379 389 409
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–39.64dBm
–29.39dBm
–28.89dBm
–28.83dBm
–28.74dBm
UPPER
–103.72dBm
–94.79dBm
–94.96dBm
–95.34dBm
–95.75dBm
RBW = 30kHz
VBW = 3kHz
REF = –30dBm
ATTEN = 5dB
SWEEP = 24s
FREQUENCY (MHz)
50
10dB/DIV
–60
–40
850 950
2000A G35
–80
–100
–70
–50
–30
–90
–110
–120
–130 250 450 650
150 350 550 750 1050
RBW = 20kHz
VBW = 2kHz
REF = –30dBm
ATTEN = 5dB
SWEEP = 60s
FREQUENCY (MHz)
CARRIER POWER = –28.59dBm, CENTER FREQ = 500MHz
473
10dB/DIV
–60
–40
513
2000A G38
–80
–100
–70
–50
–30
–90
–110
–120
–130 483 493 503 523
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–102.11dBm
–94.82dBm
–94.42dBm
–94.16dBm
–94.17dBm
UPPER
–39.71dBm
–28.18dBm
–28.96dBm
–29.11dBm
–29.04dBm
RBW = 30kHz
VBW = 3kHz
REF = –30dBm
ATTEN = 5dB
SWEEP = 24s
FREQUENCY (MHz)
50
10dB/DIV
–60
–40
950850
2000A G36
–80
–100
–70
–50
–30
–90
–110
–120
–130 250 450 650
150 350 550 750 1050
RBW = 20kHz
VBW = 2kHz
REF = –30dBm
ATTEN = 5dB
SWEEP = 60s
FREQUENCY (MHz)
CARRIER POWER = –29.43dBm, CENTER FREQ = 800MHz
773
10dB/DIV
–60
–40
813
2000A G39
–80
–100
–70
–50
–30
–90
–110
–120
–130 783 793 803 823
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–97.92dBm
–89.60dBm
–89.45dBm
–89.52dBm
–89.38dBm
UPPER
–40.25dBm
–29.56dBm
–29.23dBm
–29.40dBm
–29.56dBm
RBW = 30kHz
VBW = 3kHz
REF = –30dBm
ATTEN = 5dB
SWEEP = 24s
TYPICAL PERFORMANCE CHARACTERISTICS
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.
LTC2000A-16
LTC2000A
14
2000afb
For more information www.linear.com/LTC2000A
128 Carrier DOCSIS Low Band
Wideband ACLR, fDAC = 2.7Gsps
157 Carrier DOCSIS Gap Channel
Wideband ACLR, fDAC = 2.7Gsps
157 Carrier DOCSIS Gap Channel
Narrowband ACLR, fDAC = 2.7Gsps
157 Carrier Tones with Gap Channel
Wideband ACLR, fDAC = 2.7Gsps
157 Carrier Tones with Gap Channel
Narrowband ACLR, fDAC = 2.7Gsps
128 Carrier DOCSIS Low Band
Narrowband ACLR, fDAC = 2.7Gsps
FREQUENCY (MHz)
50
10dB/DIV
–60
–40
950
850
2000A G40
–80
–100
–70
–50
–30
–90
–110
–120
–130 250 450 650
150 350 550 750 1050
RBW = 20kHz, VBW = 2kHz
REF = –30dBm, ATTEN = 5dB
SWEEP = 60s
FREQUENCY (MHz)
CARRIER POWER = –37.77dBm, CENTER FREQ = 832MHz
805
10dB/DIV
–60
–40
845
2000A G43
–80
–100
–70
–50
–30
–90
–110
–120
–130 815 825 835 855
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–47.75dBm
–38.07dBm
–37.57dBm
–37.39dBm
–37.27dBm
UPPER
–104.61dBm
–95.82dBm
–95.53dBm
–95.43dBm
–95.18dBm
RBW = 30kHz
VBW = 3kHz
REF = –30dBm
ATTEN = 5dB
SWEEP = 24s
TYPICAL PERFORMANCE CHARACTERISTICS
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.
LTC2000A-16
FREQUENCY (MHz)
30
10dB/DIV
–60
–40
830 930
2000A G41
–80
–100
–70
–50
–30
–90
–110
–120
–130 230 430 630
130 330 530 730 1030
RBW = 20kHz, VBW = 2kHz
REF = –30dBm, ATTEN = 5dB
SWEEP = 60s
FREQUENCY (MHz)
30
10dB/DIV
–60
–40
830
2000A G42
–80
–100
–70
–50
–30
–90
–110
–120
–130 230 430 630
130 330 530 730 9301030
RBW = 20kHz, VBW = 2kHz, REF = –30dBm,
ATTEN = 5dB, SWEEP = 60s, LIN_DIS = 1
FREQUENCY (MHz)
GAP CHANNEL POWER = –96.61dBm, CENTER FREQ = 508MHz
481
10dB/DIV
–60
–40
521
2000A G44
–80
–100
–70
–50
–30
–90
–110
–120
–130 491 501 511 531
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
BW
750kHz
5.25MHz
6MHz
6MHz
6MHz
LOWER
–47.17dBm
–36.79dBm
–36.58dBm
–36.76dBm
–36.76dBm
UPPER
–48.00dBm
–36.67dBm
–36.56dBm
–36.60dBm
–36.69dBm
RBW = 30kHz, VBW = 3kHz
REF = –30dBm, ATTEN = 5dB
SWEEP = 24s
FREQUENCY (MHz)
510
–130
10dB/DIV
–120
–100
–90
–80
–30
–60
515 520
2000A G45
–110
–50
–40
–70
525
RBW = 30kHz, VBW = 3kHz
REF = –30dBm, ATTEN = 10dB
SWEEP = 24s, LIN_DIS = 1
LTC2000A
15
2000afb
For more information www.linear.com/LTC2000A
TYPICAL PERFORMANCE CHARACTERISTICS
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.
LTC2000A-16 Single Carrier WCDMA
ACLR vs fOUT, fDAC = 2.7Gsps
LTC2000A-16 Single Carrier WCDMA
ACLR at 350MHz, fDAC = 2.7Gsps
Additive Phase Noise,
fOUT = 65MHz, fDAC = 2.7Gsps
LTC2000A-14 Differential
Nonlinearity (DNL)
LTC2000A-14 Single-Tone NSD
vs fOUT and fDAC
LTC2000A-14 Integral Nonlinearity
(INL)
fOUT (MHz)
0
–90
ACLR (dBc)
–80
–70
–60
–50
200 400 600 800
2000A G46
1000 1200
ADJ CHANNEL
2ND ADJ CHANNEL
5TH ADJ CHANNEL
FREQUENCY (MHz)
CARRIER POWER = –16.44dBm, CENTER FREQ = 350MHz
323
–60
–40
363
2000A G47
–80
10dB/Hz
–100
–70
–50
–30
–90
–110
–120
–130 333 343 353 373
OFFSET FREQ
5.00MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
3.84MHz
LOWER
–95.14dBm
–95.76dBm
–95.41dBm
–95.69dBm
–95.00dBm
UPPER
–94.76dBm
–96.22dBm
–95.10dBm
–96.41dBm
–96.69dBm
RBW = 30kHz
VBW = 3kHz
REF = –20dBm
ATTEN = 5dB
SWEEP = 24s
OFFSET FREQUENCY (kHz)
–160
PHASE NOISE (dBc/Hz)
–150
–130
–110
–100
0.01 1 10 1000
2000A G48
–170
0.1 100
–120
–140
–180
CODE
–8192
INL (LSB)
0
1
8192
2000A G49
–1
–2 –4096 04096
2
fOUT (MHz)
0
–170
NSD (dBm/Hz)
–165
–160
–155
–150
–145
200 400 600 800
2000A G51
1000 1200
2.7Gsps
1.25Gsps
DIGITAL AMPLITUDE = 0dBFS
40mA FULL-SCALE CURRENT
0dBm SINGLE TONE
CODE
–8192
DNL (LSB)
0
0.5
8192
2000 G50
–0.5
–1.0 –4096 04096
1.0
LTC2000A
16
2000afb
For more information www.linear.com/LTC2000A
TYPICAL PERFORMANCE CHARACTERISTICS
IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.86V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.
LTC2000A-11 Differential
Nonlinearity (DNL)
LTC2000A-11 Single-Tone NSD
vs fOUT and fDAC
LTC2000A-11 Integral Nonlinearity
(INL)
CODE
–1024
INL (LSB)
0
0.5
1024
2000A G52
–0.5
–1.0 –512 0512
1.0
CODE
–1024
DNL (LSB)
0
0.25
1024
2000A G53
–0.25
–1.50 –512 0512
0.50
fOUT (MHz)
0
–170
NSD (dBm/Hz)
–165
–160
–155
–150
–145
200 400 600 800
2000A G54
1000 1200
2.7Gsps
1.25Gsps
DIGITAL AMPLITUDE = 0dBFS
40mA FULL-SCALE CURRENT
0dBm SINGLE TONE
LTC2000A
17
2000afb
For more information www.linear.com/LTC2000A
PIN FUNCTIONS
AVDD18: 1.8V Analog Supply Voltage Input. 1.8V to 1.92V.
AVDD33: 3.3V Analog Supply Voltage Input. 3.135V to
3.465V.
CKP, CKN: DAC Sample Clock Inputs. Maximum clock
frequency (fDAC) is 2700MHz. Clock signal should be AC
coupled.
CS: Serial Interface Chip Select Input. When CS is low,
SCK is enabled for shifting data on SDI into the register.
When CS is taken high, SCK is disabled and SDO is high
impedance.
DAP[15:0], DAN[15:0]: Port A LVDS Data Inputs. Maximum
data rate is 1.35Gbps. Port A is used only in dual-port
mode. Connect to GND if not used. The data input format
is two’s complement.
DBP[15:0], DBN[15:0]: Port B LVDS Data Inputs. Maximum
data rate is 1.35Gbps. In single-port mode, only Port B is
used. In dual-port mode, the sample from PortB appears
at IOUTP/N one cycle after the sample from Port A. The data
input format is two’s complement.
DCKIP, DCKIN: LVDS Data Clock Inputs. Maximum
frequency (fDCKI) is 675MHz. In dual-port mode, fDCKI =
fDAC/4. In single-port mode, fDCKI = fDAC/2
DCKOP, DCKON: LVDS Data Clock Outputs. Maximum
frequency is 675MHz. Select frequency (fDAC/4 or fDAC/2),
output current (3.5mA or 7mA), and termination (none or
100Ω) using register 0x02.
DVDD18: 1.8V Digital Supply Voltage Input. 1.8V to 1.92V.
DVDD33: 3.3V Digital Supply Voltage Input. 3.135V to
3.465V.
FSADJ: Full-Scale Adjust Pin. The DAC full-scale current is
16 • (VREFIO/RFSADJ). Connect a 500Ω resistor from FSADJ
to GND to set the full-scale current to 40mA.
GND: Ground.
IOUTP, IOUTN: DAC Analog Current Outputs. Differential
output is nominally ±40mA. Maximum update rate is
2.7Gsps. The output current is evenly divided between
IOUTP and IOUTN when the two’s compliment DAC code is
set to mid-scale (all zeros).
PD (Pin S1): Active Low Power-Down Input. When PD is
low, the LTC2000A supply current is less than 440µA. To
exit power-down mode switch PD high to SVDD.
REFIO: Reference Voltage Input or Output. The 1.25V
internal reference is available at the pin through a 10k
internal resistor. May be overdriven with an external refer-
ence voltage between 1.1V and 1.4V.
SCK: Serial Interface Clock Input. Maximum frequency
is 50MHz.
SDI: Serial Interface Data Input. Data on SDI is clocked
in on the rising edge of SCK.
SDO: Serial Interface Data Output. Data is clocked out onto
SDO by the falling edge of SCK. SDO is high impedance
when CS is high.
SVDD: SPI Supply Voltage Input. 1.71V to 3.465V.
TSTP, TSTN: Test Output Pins. May be optionally used to
measure internal temperature or timing of LVDS inputs.
See Measuring Internal Junction Temperature and Mea-
suring LVDS Input Timing Skew sections in Applications
Information. Use SPI internal registers 0x18 and 0x19 to
control TSTP/N. Connect to GND if not used.
Note: For pin locations, refer to the Pin Locations section
of this data sheet.
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BLOCK DIAGRAM
LVDS RECEIVERS
DDR DATA FLIP-FLOPS
4:1
TSTP/N PD CS SCK SDI SDO SVDD
50Ω
IOUTP
IOUTN
FSADJ
REFIO
50Ω
10k
2000A BD
CKP/NGNDDVDD33
DVDD18 AVDD33
AVDD18
GAIN
ADJUST
CLOCK
SYNC
CLK
RECEIVER
DELAY
ADJUST
DCKOP/N
DCKIP/N
DBP/N[15:0]
DAP/N[15:0]
CLK DIVIDER
÷2 OR ÷4
REF
SPI
PATTERN
GENERATOR
JUNCTION
TEMPERATURE
16-BIT DAC
LTC2000A
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OPERATION
TIMING DIAGRAMS
SDI
SDO
CS
SCK
t2
t13
t10
t5
Hi-Z Hi-Z
t7
t6
t1
t3t4
1 2 3 15 16
2000A F01
DAP/N, DBP/N
t12
DCKI
t11 2000A F02
t12
t11
DAP/N, DBP/N
t11
DCKI
t12
2000A F03
t11
t12
Figure 1. Serial Interface Timing
Figure 2. LVDS Interface Timing (DCKI_Q = 0, DCK_TADJ = 000)
Figure 3. LVDS Interface Timing (DCKI_Q = 1)
Introduction
The LTC2000A is a family of 2.7Gsps current steering
DACs. Three resolutions (16-, 14-, 11-bit) are available
in a 170-lead BGA package. The LTC2000A features high
output bandwidth and output current, while maintaining
a clean output spectrum with low spurs, making it ideal
for generating high frequency or broadband signals. The
LTC2000A output current is nominally 40mA and is a
scaled (16x) replica of the current flowing out of the FSADJ
pin (nominally 2.5mA). The high output current allows
flexibility in the output impedance, and the high FSADJ
current and low scaling factor give excellent close-in phase
noise performance.
The LTC2000A has two 16-, 14-, 11-bit wide LVDS or
DHSTL-compatible parallel data input ports (DAP/N,
DBP/N). Each data input port is capable of receiving two’s
complement data at up to 1.35Gbps using a double data
rate (DDR) data input clock (DCKIP/N) at up to 675MHz.
The DDR data input clock may be either in quadrature or
in phase with the data arriving on the data input ports.
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OPERATION
Note that the sample clock (CKP/N) frequency is always
four times the DDR data input clock (DCKIP/N) frequency
in dual-port mode. For example, to use the DAC at 2.7Gsps,
apply a 2.7GHz clock to CKP/N and a 675MHz clock to
DCKIP/N and send data into both ports A and B (DAP/N,
DBP/N) at 1.35Gsps per port.
Latency is defined as the delay from the DCKIP/N transition
that samples a DAC code to the CKP/N rising transition
which causes that sample to appear at the DAC output
IOUTP/N. In dual-port mode the latency from DAP/N to
IOUTP/N is 10 sample clock cycles and the latency from
DBP/N to IOUTP/N is 11 cycles, starting from the CKP/N
rising edge that immediately follows the DCKIP/N transi-
tion that sampled the DAC code (Figure 4b).
Single-Port Mode
In single-port mode, data is written to port B (DBP/N) only,
allowing DAC output sampling rates of up to 1.35Gsps.
Figures 4c and 4d show a block diagram and sample
waveforms representing single-port operation. Samples are
written to port B (DBP/N) and sampled on both the falling
and rising edges of the DDR data input clock (DCKIP/N) by
two groups of flip-flops. The contents of these flip-flops
are then interleaved into a single data stream by the 2:1
MUX and sampled by the DAC sample clock (CKP/N) at
frequencies up to 1.35GHz.
Note that in single-port mode the sample clock (CKP/N) fre-
quency is always twice the DDR data input clock (DCKIP/N)
frequency. For example, to use the DAC at 1.35Gsps, apply
a 1.35GHz clock to CKP/N and a 675MHz clock to DCKIP/N
and send data into port B (DBP/N) at 1.35Gsps. In single-
port mode, port A (DAP/N) should be grounded. Due to
the design of the internal clock synchronizer in single port
mode, there is a half cycle shift in the single port latency.
The latency from DBP/N to IOUTP/N in single-port mode is
7.5 sample clock cycles, starting from the CKP/N falling
edge that immediately follows the DCKIP/N transition that
sampled the DAC code (Figure 4d).
After incoming data is sampled by DCKIP/N, an internal
multiplexer interleaves the data for resampling by the
DAC sample clock (CKP/N). See Figures 4a and 4b. After
a pipeline delay (latency) of up to 11 DAC sample clock
cycles, the rising edges of CKP/N update the DAC code
and a proportional differential output current is steered
between the two outputs (IOUTP/N). Note it takes about 3ns
(aperture delay) from the CKP/N rising edge that updates a
DAC code to the actual IOUTP/N transition for that DAC code.
An internal clock synchronizer monitors the incoming
phase of DCKIP/N and chooses the appropriate phase for
the multiplexer control signals to ensure that the data is
sampled correctly by CKP/N. The LTC2000A also generates
an LVDS clock output (DCKOP/N) by dividing the sample
clock frequency to simplify clocking of the host FPGA
or ASIC. Additional features such as pattern generation,
LVDS loopout, and junction temperature sensing simplify
system development and testing.
The serial peripheral interface (SPI) port allows configura-
tion and read back of the internal registers which control
the above functions.
Dual-Port Mode
In dual-port mode, data is written to both ports A and B
simultaneously and then subsequently interleaved inside
the LTC2000A, allowing DAC output sampling rates of up
to 2.7Gsps. Figures 4a and 4b show a simplified block
diagram and sample waveforms for dual-port operation.
The LVDS data input ports A and B are sampled on both
the falling and rising edges of the DDR data input clock
(DCKIP/N) by four groups of flip-flops. The contents of
these flip-flops are then interleaved by the 4:1 MUX and
sampled by the DAC sample clock (CKP/N) at frequencies
up to 2.7GHz, with data from port A (DAP/N) preceding
data from port B (DBP/N) at the DAC output.
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OPERATION
16-BIT DAC
4:1 MUX
N+3
N+2
N+1
N
50Ω
IOUTP
IOUTN
50Ω
2000A F04a
CLOCK
SYNC
DBP/N[15:0]
DAP/N[15:0]
DCKIP/N
CKP/N
DAP/N[15:0] N N+2 N+4 N+6 N+8 N+10
DBP/N[15:0]
DCKIP/N
CKP/N
IOUTP/N
N+1 N+3
1 2 3 4 5
10 CYCLE LATENCY
6 7 8 9 10 11
N N+1
2000A F04b
N+5 N+7 N+9 N+11
11 CYCLE LATENCY
Figure 4a. Simplified Block Diagram – Dual-Port Operation
Figure 4b. Sample Waveforms – Dual-Port Operation
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OPERATION
16-BIT DAC
2:1 MUX
N+1
N
50Ω
IOUTP
IOUTN
50Ω
2000 F04c
CLOCK
SYNC
DBP/N[15:0]
DCKIP/N
CKP/N
DBP/N[15:0]
DCKIP/N
CKP/N
IOUTP/N
N N+1
0.5 1.5
7.5 CYCLE LATENCY
2.5 3.5 4.5 5.5 6.5 7.5
N
2000A F04d
N+2 N+3 N+4 N+5 N+6 N+6 N+7
Figure 4c. Simplified Block Diagram – Single-Port Operation
Figure 4d. Sample Waveforms – Single-Port Operation
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OPERATION
R/W
READ/WRITE REGISTER ADDRESS
COMMAND BYTE
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
2000A F05
Figure 5. SPI Command and Data Input
Serial Peripheral Interface (SPI)
The LTC2000A uses an SPI/MICROWIRE-compatible
3-wire serial interface to configure and read back internal
registers. The SVDD pin is the power supply for the SPI
interface (nominally 1.8V or 3.3V). The CS input is level
triggered. When this input is taken low, it acts as a chip-
select signal, enabling the SDI and SCK buffers and the
SPI input register. After the falling edge of CS, the first
data byte clocked into SDI by the rising edges of SCK is
the command byte. The first bit of the command byte
signifies a read (R/W = 1) or write (R/W = 0) operation.
The next seven bits contain the register address, which
completes the command byte.
The next byte transferred after the command byte is the
data byte. For write operations, the data byte is written to
the SPI register specified by the register address set in
the command byte. During read operations, the data byte
is ignored, and the contents of the selected SPI register
are clocked out onto the SDO pin by the falling edges of
SCK. During write operations, SDO will be low. When CS
goes high, SDO is high impedance. Figure 5 shows the
SPI command and data input.
Users wishing to transfer multiple bytes of data at once
may do so, with the address for each subsequent byte
automatically incremented internally. The address will
continue to increment until CS goes high or until address
bits A[4:0] reach 0x1F, after which subsequent bytes will
continue to be written to the same address.
Reserved address and bit locations should not be written
with any value other than zero. Table 11 contains a full
description of all internal SPI registers and can be found
in the SPI Register Summary section.
Power-On Reset
The internal power-on reset circuit will reset the LTC2000A
upon power up and clear the output to mid-scale when
power is first applied, making system initialization con-
sistent and repeatable. All internal registers are reset to
0x00, with the exception of register address 0x08, which
resets to 0x08. A software reset can also be applied by
using the SPI interface to load 0x01 into register address
0x01, setting SW_RST to 1 (see Table 1). Note that the
SW_RST bit is automatically cleared when CS returns
high. It is recommended that users perform a software
reset once all power supplies are stable.
Power Down
Users wishing to save power when the DAC is not being
used may reduce the supply current to less than 440µA by
pulling the PD pin to GND or by writing to register 0x01
to set FULL_PD = 1. Alternatively, users may power down
unused portions of the chip individually using DAC_PD,
CK_PD, DCKO_DIS, DCKI_EN, DA_EN, and DB_EN in
registers 0x01, 0x02, 0x03, and 0x04 (see Table 1).
Reference Operation
The LTC2000A has a 1.25V internal bandgap voltage ref-
erence that drives the REFIO pin through a 10k internal
resistor, and should be buffered if driving any additional
external load. For noise performance, a 0.1µF capacitor
to GND is recommended on the REFIO pin, but is not
required for stability.
In the case where an external reference would be preferred,
the external reference is simply applied to the REFIO pin
and overdrives the internal reference. The acceptable
external reference range is 1.1V to 1.4V.
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Setting the Full-Scale Current
The full-scale DAC output current (IOUTFS) is nominally
40mA, but can be adjusted as low as 10mA or as high as
60mA. The full-scale current is set by placing an external
resistor (RFSADJ) between the FSADJ pin and GND. An
internal reference control loop amplifier sets the current
flowing through RFSADJ such that the voltage at FSADJ
is equal to the voltage at REFIO, which is typically 1.25V.
IOUTFS is set as a scaled replica of the current flowing out
of the FSADJ pin (IFSADJ):
IFSADJ =VREFIO
RFSADJ
IOUTFS =16 •IFSADJ •256
256
+
GAIN _ ADJ
where GAIN_ADJ is a 6-bit two’s complement number from
–32 to 31 (nominally 0) which can be programmed using
SPI register 0x09 as shown in Table 2. For example, for
RFSADJ = 500Ω, VREFIO = 1.25V, and GAIN_ADJ = 0x00,
the control loop will force 1.25V at the FSADJ pin, causing
2.5mA to flow through RFSADJ. IOUTFS will then be set to
16 • 2.5mA = 40mA.
OPERATION
Changing GAIN_ADJ to 0x1F (+31) will decrease the cur-
rent by 10.8% to 35.7mA. Changing GAIN_ADJ to 0x20
(–32) will increase the current by 14.3% to 45.7mA.
Note that GAIN_ADJ appears in the denominator of the
equation for IOUTFS, so the adjustment resolution varies
from 0.5% to 0.3% per step. The circuit shown in Figure
6 may be used to vary the full-scale output current beyond
the range of the GAIN_ADJ register.
DAC linearity and harmonic distortion may be degraded
when using full-scale currents other than 40mA. The full-
scale current must not exceed 60mA, and is recommended
to be at least 10mA.
Table 1. Power-On Reset and Power-Down SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x01 0 SW_RST Software Reset. Set SW_RST = 1 to restore all registers to their power-on reset state. SW_RST is automatically cleared
when CS returns high. All registers reset to 0x00, except address 0x08 which resets to 0x08.
1 DAC_PD DAC Power Down. Set DAC_PD = 1 to power down the DAC and FSADJ bias circuits.
2 FULL_PD Full Power Down. Set FULL_PD = 1 to power down all active circuits on the chip and reduce the supply current to less
than 100µA.
0x02 0 CK_PD CKP/N Clock Receiver Power Down. CKP/N clock receiver is powered down when CK_PD = 1.
4 DCKO_DIS DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1,
DCKOP/N are high impedance.
0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. Set DCKI_EN = 1 to enable the DCKI clock receiver.
0x04 0 DA_EN DAC Data Port A LVDS Receiver Enable. Set DA_EN = 1 to enable port A (DAP/N) LVDS receivers. For DA_EN = 0,
port A LVDS receivers are powered down and port A data will be zeroes.
1 DB_EN DAC Data Port B LVDS Receiver Enable. Set DB_EN = 1 to enable port B (DBP/N) LVDS receivers. For DB_EN = 0,
port B LVDS receivers are powered down and port B data will be zeroes.
Note: Registers 0x01 to 0x04 reset to 0x00 (default).
Figure 6. LTC2000A Full-Scale Adjust from 20mA to 60mA
–
+
REF
LTC2000A
REFIO
1.25V
10k
2000A F06
1k
500Ω
0V TO 2.5V
LTC2630-LM12
FSADJ
LTC2000A
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OPERATION
Table 2. Full-Scale Gain Adjustment
ADDRESS BIT NAME DESCRIPTION
0x09 [5:0] GAIN_ADJ
GAIN_ADJ (HEX) GAIN_ADJ (DECIMAL) GAIN ADJUSTMENT
FULL-SCALE CURRENT
(RFSADJ = 500Ω, VREFIO = 1.25V)
0x1F +31 89.2% 35.68mA
0x1E +30 89.5% 35.80mA
— — — —
0x01 +1 99.6% 39.84mA
0x00 0 100.0% 40.00mA
0x3F –1 100.4% 40.16mA
— — — —
0x21 –31 113.8% 45.51mA
0x20 –32 114.3% 45.71mA
Note: Register 0x09 resets to 0x00 (default).
DAC Transfer Function
The LTC2000A contains an array of current sources
that are steered through differential switches to either
IOUTP or IOUTN, depending on the DAC code programmed
through the LVDS parallel interface. The LTC2000A uses a
16-/14-/11-bit two’s complement DAC code. The comple-
mentary current outputs, IOUTP and IOUTN, source current
from 0mA to IOUTFS. For IOUTFS = 40mA (nominal), IOUTP
swings from 0mA (for zero-scale DAC code) to 40mA (for
full-scale DAC code). IOUTN is complementary to IOUTP.
When the DAC code is set to mid-scale (all zeros), IOUTFS
is evenly divided between IOUTP and IOUTN. IOUTP and IOUTN
are given by the following formulas:
LTC2000A-16:
IOUTP = IOUTFS • (CODE + 32768)/65536 + IOUTCM
IOUTN = IOUTFS • (32768 – CODE – 1)/65536 + IOUTCM
LTC2000A-14:
IOUTP = IOUTFS • (CODE + 8192)/16384 + IOUTCM
IOUTN = IOUTFS • (8192 – CODE – 1/4)/16384 + IOUTCM
LTC2000A-11:
IOUTP = IOUTFS • (CODE + 1024)/2048 + IOUTCM
IOUTN = IOUTFS • (1024 – CODE – 1/32)/2048 + IOUTCM
The DAC code ranges from –2N-1 to 2N-1 – 1, with N
being the DAC resolution (16/14/11). IOUTCM is a small,
constant common-mode output current that is equal to
approximately 0.2% full-scale, or 80µA for IOUTFS = 40mA.
The LTC2000A differential output currents typically drive a
resistive load either directly or drive an equivalent resistive
load through a transformer (see the Output Configurations
section). The voltage outputs generated by the IOUTP and
IOUTN outputs currents are then:
VOUTP = IOUTP • RLOAD
VOUTN = IOUTN • RLOAD
VDIFF = VOUTP – VOUTN = (IOUTP-IOUTN) • RLOAD
Substituting the values above gives:
LTC2000A-16:
VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1)/4096
LTC2000A-14:
VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1/4)/1024
LTC2000A-11:
VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1/32)/128
Note that the gain of the DAC depends on the ratio of RLOAD
to RFSADJ, and the gain error tempco is affected by the
temperature tracking of RLOAD with RFSADJ.
Analog Outputs (IOUTP/N)
The two complementary analog outputs (IOUTP/N) have low
output capacitance that, with appropriate RLOAD values,
can achieve high output bandwidths of 2.1GHz. The analog
outputs also have an internal impedance of 50Ω to GND
that will affect the calculation of RLOAD and the output
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OPERATION
Table 3. DAC Sample Clock, and Divided Clock Output SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x02 0 CK_PD CKP/N Clock Receiver Power Down When CK_PD = 1
1 CK_OK CKP/N Clock Present Indicator. When CK_OK = 1, clock is present at CKP/N pins and fDAC > 50MHz.
When CK_OK = 0, DAC output is forced to mid-scale. CK_OK is read only.
4 DCKO_DIS DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1,
DCKOP/N are high impedance.
5 DCKO_DIV DCKOP/N Divide Select. When DCKO_DIV = 0, fDCKOP/N = fDAC/4. When DCKO_DIV = 1, fDCKOP/N = fDAC/2.
6 DCKO_ISEL DCKOP/N Output Current Select. When DCKO_ISEL = 0, output current is 3.5mA. When DCKO_ISEL = 1,
output current is 7mA.
7 DCKO_TRM DCKOP/N Internal Termination On. When DCKO_TRM = 0, there is no internal termination at DCKOP/N.
When DCKO_TRM = 1, there is 100Ω between DCKOP and DCKON.
Note: Register 0x02 resets to 0x00 (default).
voltage swing of the DAC. For example, loading both IOUTP
and IOUTN with external 50Ω resistors to GND will cause
RLOAD to equal 25Ω. Assuming an IOUTFS of 40mA, VDIFF
will swing between 1V and –1V.
The specified output compliance voltage range is ±1V.
Above 1V, the differential current steering switches will
start to approach the transition from saturation to linear
region and degrade DAC linearity. Below –1V protection
diodes will limit the swing of the DAC. Small voltage
swings and low common-mode voltages typically result
in the best distortion performance.
DAC Sample Clock (CKP/N)
The DAC sample clock (CKP/N) is used to update the
LTC2000A outputs at rates of up to 2.7Gsps. Provide a
clean, low jitter differential clock at up to 2.7GHz on pins
CKP/N (see Generating the DAC Sample Clock section).
The DC bias point of CKP/N is set internally through a
5kΩ impedance. A 0dBm DAC sample clock should be
sufficient to obtain the performance shown in the Typical
Performance Characteristics section. For best jitter and
phase noise, AC couple a differential clock onto CKP/N with
balanced duty cycle and the highest possible amplitude
and slew rate.
Use SPI register 0x02 to control the DAC sample clock
receiver (Table 3). The LTC2000A contains a clock detector
which sets CK_OK = 1 if the DAC sample clock is present
and fDAC > 50MHz. When the sample clock is not present
(CK_OK = 0), the DAC output is forced to mid-scale and
the internal data path is held at reset. Set CK_PD = 1 to
power down the clock receiver and save power when the
DAC is not being used. Note that at power-on reset, the
DAC sample clock receiver is on by default.
Divided Clock Output (DCKOP/N)
The LTC2000A contains a programmable clock divider
and LVDS transmitter which provide a divided version
(either fDAC/4 or fDAC/2) of the DAC sample clock for
use by the host FPGA or ASIC. Use SPI register 0x02 to
control DCKOP/N (Table 3). At power-on reset, the LVDS
transmitter will provide a clock signal at fDAC/4 with a
3.5mA differential output current.
If desired, set DCKO_DIV = 1 to change the divided clock
output frequency to fDAC/2. The output current can be in-
creased to 7mA by setting DCKO_ISEL = 1, and an internal
100Ω differential termination can be enabled by setting
DCKO_TRM = 1. Set DCKO_DIS = 1 to disable the LVDS
transmitter and save power when not in use.
LVDS Data Clock Input (DCKIP/N)
The DAC code data written to the LTC2000A is captured
on both the rising and falling edges of DCKIP/N. For
single-port operation, provide a DDR clock at half the DAC
sample clock frequency (fDCKI = fDAC/2). To use a 1.35GHz
sample clock in single-port mode, provide a 675MHz
clock on DCKIP/N. For dual-port operation, provide a
DDR clock at one quarter the DAC sample clock frequency
(fDCKI = fDAC/4). To use a 2.7GHz sample clock in dual-port
mode, provide a 675MHz clock on DCKIP/N.
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OPERATION
Table 4. LVDS Clock SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables LVDS clock receiver.
1 DCKI_OK DCKIP/N Clock Present Indicator. When DCKI_OK = 1, clock is present at DCKIP/N pins and fDCKIP/N > 25MHz.
When DCKI_OK = 0, DAC output is forced to mid-scale unless pattern generator is enabled (PGEN_EN = 1).
DCKI_OK is read only.
2 DCKI_Q DCKIP/N Quadrature Phase Select. For DCKI_Q = 0, DCKIP/N should be in phase with DAP/N and DBP/N.
Set DCKI_Q = 1 to use DCKIP/N in quadrature with DAP/N and DBP/N.
[6:4] DCKI_TADJ DCKIP/N Delay Adjust. Use with DCKI_Q = 0 to adjust delay of DCKIP/N relative to DAP/N and DBP/N.
For DCKI_Q = 1, DCKIP/N delay matches DAP/N and DBP/N and is unaffected by DCKI_TADJ.
DCKI_TADJ
NOMINAL DCKIP/N DELAY
DCKI_Q = 1 DCKI_Q = 0
110 0ps 230ps
111 0ps 315ps
000 0ps 400ps (Default)
001 0ps 485ps
010 0ps 570ps
Note: Register 0x03 resets to 0x00 (default).
Use SPI register 0x03 to control the LVDS data clock input
(see Table 4). Setting DCKI_EN=1 will enable the LVDS re-
ceiver at DCKIP/N. The LTC2000A contains a clock detector
which sets DCKI_OK=1 if the data input clock is present
and has a frequency greater than 25MHz (fDCKI > 25MHz).
When the data clock is not present (DCKI_OK= 0), the
DAC output is forced to mid-scale and the internal data
path is held at reset.
For maximum setup/hold margin, set DCKI_Q = 1 and
provide DCKIP/N in quadrature (90° out of phase) with
the data on DAP/N and DBP/N (Figure 3 in the Timing
Diagrams section). For DCKI_Q = 1, the internal delays
on DCKIP/N, DAP/N, and DBP/N are nominally matched.
Alternatively, it is possible to leave DCKI_Q = 0 and provide
the clock at DCKIP/N in phase with the data on DAP/N
and DBP/N (see Figure 2 of the Timing Diagram section).
In this case, an internal 400ps delay on DCKIP/N is used
to provide setup/hold margin. Note that for DCKI_Q = 0,
supply and temperature variation may reduce the setup/
hold margin on the bus by up to 150ps. If desired, users
may use the DCKI_TADJ bits in register 0x03 to adjust
the 400ps internal DCKIP/N delay with a typical resolu-
tion of 85ps.
Board trace lengths on DCKIP/N, DAP/N, and DBP/N must
be carefully matched to ensure that phase alignment is
maintained on all inputs. If desired during development,
users may observe the relative timing of neighboring LVDS
inputs on the TSTP/N pins (refer to the Measuring LVDS
Input Timing Skew section).
LVDS Data Input Ports (DAP/N, DBP/N)
The LTC2000A-16/LTC2000A-14/LTC2000A-11 allow for
DAC Code Data to be applied through one or two parallel
16-/14-/11-bit LVDS ports (DAP/N, DBP/N). Each port can
run up to 1.35Gbps using a double-data-rate (DDR) LVDS
data clock (DCKIP/N) at frequencies up to 675MHz. The
data input format is two’s complement.
There are two modes of operation for applying the DAC
code to the LTC2000A — single-port mode and dual-
port mode. Single port operation uses only LVDS port B
(DBP/N) and allows sample rates of up to 1.35Gsps. Dual
port operation uses both LVDS ports (DAP/N and DBP/N)
and allows sample rates up to 2.7Gsps.
Use SPI register 0x04 to control the LVDS data input
ports (see Table 5). After the clocks have stabilized and
the synchronizer has initialized itself, set DATA_EN = 1
to allow the data from ports A and B to be used to update
the DAC code. Clear DATA_EN = 0 to mute the DAC and
force the DAC code to mid-scale as desired.
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OPERATION
For single port operation, set DATA_SP = 1, DA_EN = 0,
DB_EN = 1 and provide data to LVDS port B (DBP/N) only.
For dual port operation leave DATA_SP = 0, set DA_EN =
1 and DB_EN = 1, and provide interleaved data to LVDS
ports A and B (DAP/N, DBP/N). The data on port A will
precede the data on port B at the DAC output.
Table 5. LVDS Data Input SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x04 0 DA_EN DAC Data Port A LVDS Receiver Enable. DA_EN = 1 enables port A receivers. For DA_EN = 0, receivers are powered
down and port A data is 0x0000.
1 DB_EN DAC Data Port B LVDS Receiver Enable. DB_EN = 1 enables port B receivers. For DB_EN = 0, receivers are powered
down and port B data is 0x0000.
2 DATA_SP DAC Data Single Port Mode Select. DATA_SP = 1 sets single port mode and only port B data is used to update the DAC
code. DATA_SP = 0 sets dual-port mode and data from both ports A and B are used.
3 DATA_EN DAC Data Enable. DATA_EN = 0 mutes the DAC output by forcing the DAC code to mid-scale. DATA_EN = 1 allows data
from data ports A and B to be used to update the DAC code.
Note: Register 0x04 resets to 0x00 (default).
Clock Synchronizer
Figure 7 shows a simplified block diagram of the internal
clock synchronizer. The synchronizer monitors the incom-
ing phase of DCKIP/N using a pair of internal phase com-
parators. The synchronizer then automatically adjusts the
4:1 MUX
50Ω
IOUTP
IOUTN
50Ω
2000A F07
÷4
0°
90°
180°
270°
DBP/N[15:0]
DAP/N[15:0]
DCKIP/N
CKP/N
SYNC_PS
SYNC_PH[7:4]
SYNC_PH[3:0]
LOGIC
PHASE
CMP
PHASE
CMP
16-BIT DAC
Figure 7. Simplified Block Diagram — Clock Synchronizer in Dual-Port Mode
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OPERATION
Table 6. Clock Synchronizer SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x05 [1:0] SYNC_PS Synchronizer Phase Select. Selects phase of internal data multiplexer. SYNC_PS is read-only when SYNC_MSYN = 0.
2 SYNC_MSYN Synchronizer Manual Mode Select. When SYNC_MSYN = 0, SYNC_PS is set automatically by the clock synchronizer
based upon SYNC_PH. When SYNC_MSYN = 1, SYNC_PS must be set by the user.
0x06 [7:0] SYNC_PH Synchronizer Phase Comparator Outputs. SYNC_PH indicates the phase of the LVDS data clock (DCKIP/N) relative to
the DAC sample clock (CKP/N) divider used to control the data multiplexer. SYNC_PH is read only.
SYNC_PH
OPTIMAL SYNC_PS SETTING
DUAL-PORT MODE SINGLE-PORT MODE
0x03 10 00
0x04 10 00
0x05 10 00
0x15 10 00
0x25 10 00
0x35 00 10
0x45 00 10
0x55 00 10
0x54 00 10
0x53 00 10
0x52 01 10
0x51 01 10
0x50 01 10
0x40 01 10
0x30 01 10
0x20 11 00
0x10 11 00
0x00 11 00
0x01 11 00
0x02 11 00
Note: Registers 0x05 and 0x06 reset to 0x00 (default).
phase of the MUX control signals as needed to track any
slow drift in the phase between the DCKIP/N and CKP/N
due to supply and temperature variation. This ensures that
data is sampled correctly by CKP/N.
Use SPI registers 0x05 and 0x06 (Table 6) to observe and
control the operation of the synchronizer. Upon power-up,
apply clocks to CKP/N and DCKIP/N and set DCKI_EN =1
(register 0x03) to enable the LVDS data clock receiver.
Allow at least 1ms after the clocks have stabilized for the
synchronizer to initialize, after which the LTC2000A is
ready to accept LVDS input data.
The synchronizer uses phase comparators to monitor
the phase of the data input clock relative to the sample
clock divider which controls the MUX. The outputs of
these phase comparators (SYNC_PH) may be observed
in register 0x06.
The SYNC_PS bits control the phase of the data multiplexer.
For SYNC_MSYN = 0, the SYNC_PS bits are read-only and
are automatically adjusted by the synchronizer as needed,
based upon the phase of DCKIP/N indicated by SYNC_PH.
Users may choose to override the automatic synchronizer
by setting SYNC_MSYN = 1 and writing values manually
to SYNC_PS to set the phase of the internal multiplex-
er. When using SYNC_MSYN = 1, users must monitor
SYNC_PH and adjust SYNC_PS as needed according to
Table 6. For further details see the Synchronizing Multiple
LTC2000As section.
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OPERATION
Minimizing Harmonic Distortion
The LTC2000A contains proprietary dynamic linearization
circuitry which dramatically reduces 3rd order harmonic
distortion in the DAC output. SPI registers 0x07 and 0x08
are used to control these circuits (see Table 7). Optimal
performance is normally achieved by setting LIN_VMX and
LIN_VMN (register 0x08) to correspond to the maximum
and minimum voltages expected at IOUTP/N. At power-on
reset the default values are 0b1000 and 0b0000, which
are appropriate for IOUTP/N swinging between 500mV and
GND. If an application requires a different voltage swing,
LIN_VMX and LIN_VMN can be programmed by writing
to register 0x08 (see Table 7). For applications in which
IOUTP/N swing below GND, use LIN_VMN = 0b0000.
In some applications where 2-tone intermodulation distor-
tion (IMD) is a critical specification, it may be desired to
vary the amount of 3rd order harmonic correction. For high
sampling frequencies (fDAC > 2Gsps), adjusting LIN_GN
in register 0x07 (see Table 7) can improve 2-tone inter-
modulation distortion at the expense of higher 3rd order
harmonic distortion. For best IMD performance at high
sampling frequencies, users may also choose to disable
dynamic linearization by setting LIN_DIS = 1. SFDR and
IMD curves in the Typical Performance Characteristics
section show more detail regarding this effect. Note that
for fDAC < 2Gsps, it is recommended to leave the dynamic
linearization enabled.
Measuring LVDS Input Timing Skew
It is important to ensure that the LVDS inputs (DCKIP/N,
DAP/N, DBP/N) are well aligned. Skew between clock and
data lines, for example due to board trace length mismatch
or output timing mismatch inside the host FPGA or ASIC,
will degrade the setup and hold margin of the incoming
data. The LTC2000A includes an internal test multiplexer
which may be used during development to verify timing
alignment by comparing the timing of LVDS inputs one
pair at a time through the TSTP/N pins.
Use SPI register 0x18 to control this test multiplexer (see
Table8). Be sure TDIO_EN = 0 in register 0x19 and then
set LMX_EN = 1 to enable the test multiplexer output.
The signal from the LVDS data input will be driven onto
TSTP/N by an NMOS differential pair steering a 6.6mA
sink current onto an external load. Connect a pair of 50Ω
resistors from TSTP/N to 3.3V and observe TSTP/N on a
high speed oscilloscope.
Apply clocks to CKP/N and DCKIP/N and apply the pattern
shown in Figure 8 to port B for single-port mode or ports
A and B for dual-port mode. This pattern is designed to
simplify comparison of rising-to-rising and falling-to-
falling edge timing for each input pair. Set LMX_ADR to
select a pair of LVDS inputs for timing comparison. Set
LMX_MSEL = 0 to observe the first signal at TSTP/N. Set
LMX_MSEL = 1 to observe the second signal with inverted
output polarity.
For example, to compare DB15P/N to DCKIP/N, first write
0x60 to register 0x18 to set LMX_EN = 1, LMX_ADR =
10000, and LMX_SEL = 0. The signal from DB15P/N will
be driven onto TSTP/N. Write 0x61 to register 0x18 to set
LMX_SEL = 1 and cause DCKIP/N to appear at TSTP/N
with inverted polarity.
Record the skew between the two signals and repeat
this measurement for each pair of inputs. After all pairs
have been measured, add the skews to calculate the total
skew from DCKIP/N to each data input (DAP/N, DBP/N).
In this way the skew of all LVDS data inputs (DAP/N,
DBP/N) relative to DCKIP/N can be accurately measured
to within 100ps.
Note that due to internal delays inside the test multiplexer,
it is only valid to compare timing between neighboring
LVDS pairs using the same LMX_ADR setting. Similarly,
the multiplexer itself contains up to 400ps of skew between
rising and falling edges, so it is only valid to compare the
timing of a rising edge at TSTP/N to another rising edge,
and a falling edge to another falling edge.
Note that Figure 8 shows the suggested input pattern
for the LTC2000A-16. LTC2000A-14 users should apply
codes 0x1555 and 0x2AAA, and LTC2000A-11 users
should apply codes 0x555 and 0x2AA. Also note that for
the LTC2000A-14 and LTC2000A-11 in dual-port mode,
the timing skew of LVDS port A (DAP/N) cannot be com-
pared to that of the LVDS clock (DCKIP/N) and LVDS port
B (DBP/N), as there is no single test multiplexer address
(LMX_ADR) that enables a timing comparison between
signals DA0N/P and DCKIP/N (see Table 8). It is recom-
mended to keep LMX_EN=0 during normal operation.
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OPERATION
Table 7. Dynamic Linearization SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x07 0 LIN_DIS Dynamic Linearization Disable. Disabled when LIN_DIS = 1.
[3:1] LIN_GN Dynamic Linearization Gain Select. Changing LIN_GN varies the amount of 3rd order harmonic correction applied to the
DAC output. LIN_GN = 000 is normally optimal.
LIN_GN LINEARIZATION PERCENTAGE
110 50%
111 63%
000 75% (default)
001 88%
010 100%
011 113%
100 125%
101 138%
0x08 [3:0] LIN_VMX Dynamic Linearization Max IOUTP/N Voltage Select. For optimal 3rd order harmonic performance, set LIN_VMX to
correspond to the maximum voltage expected at IOUTP/N. Reset state is LIN_VMX = 1000, which corresponds to 0.51V.
LIN_VMX must be greater than LN_VMN.
[7:4] LIN_VMN Dynamic Linearization Min IOUTP/N Voltage Select. For optimal 3rd order harmonic performance, set LIN_VMN to
correspond to the minimum voltage expected at IOUTP/N. Reset state is LIN_VMN = 0000, which corresponds to 0.0V.
LIN_VMN must be less than LN_VMX.
LIN_VMX/N MAX/MIN VOLTAGE EXPECTED AT IOUTP/N
0000 0.00V (Default for LIN_VMN)
0001 0.16V
0010 0.19V
0011 0.22V
0100 0.25V
0101 0.31V
0110 0.38V
0111 0.44V
1000 0.51V (Default for LIN_VMX)
1001 0.63V
1010 0.75V
1011 0.87V
1100 1.00V
Note: Register 0x07 resets to 0x00 (default). Register 0x08 resets to 0x08 (default).
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OPERATION
Table 8. SPI Registers for Measuring LVDS Input Timing Skew
ADDRESS BIT NAME DESCRIPTION
0x18 0 LMX_MSEL LVDS Test MUX Select. Set LMX_MSEL high or low to select between a pair of neighboring LVDS signals for
comparison at TSTP/N.
[5:1] LMX_ADR LVDS Test MUX Address. Use LMX_ADR to select which pair of LVDS signals will be compared at TSTP/N
(See Below).
6 LMX_EN LVDS Test MUX Enable. Set LMX_EN=1 to compare timing of neighboring signals at TSTP/N.
Ensure TDIO_EN = 0 when LMX_EN = 1.
LMX_ADR LTC2000A-16 LTC2000A-14 LTC2000A-11
LMX_MSEL = 0
LMX_MSEL = 1
(INVERTED) LMX_MSEL = 0
LMX_MSEL = 1
(INVERTED) LMX_MSEL = 0
LMX_MSEL = 1
(INVERTED)
00000 DA14P/N DA15N/P DA12P/N DA13N/P DA9P/N DA10N/P
00001…01001 DA[13:5]P/N DA[14:6]N/P DA[11:3]P/N DA[12:4]N/P DA[8:0]P/N DA[9:1]N/P
01010 DA4P/N DA5N/P DA2P/N DA3N/P — DA0N/P
01011 DA3P/N DA4N/P DA1P/N DA2N/P — —
01100 DA2P/N DA3N/P DA0P/N DA1N/P — —
01101 DA1P/N DA2N/P — DA0N/P — —
01110 DA0P/N DA1N/P — — — —
01111 DCKIP/N DA0N/P DCKIP/N — DCKIP/N —
10000 DB15P/N DCKIN/P DB13P/N DCKIN/P DB10P/N DCKIN/P
10001 DB14P/N DB15N/P DB12P/N DB13N/P DB9P/N DB10N/P
10010…11010 DB[13:5]P/N DB[14:6]N/P DB[11:3]P/N DB[12:4]N/P DB[8:0]P/N DB[9:1]N/P
11011 DB4P/N DB5N/P DB2P/N DB3N/P — DB0N/P
11100 DB3P/N DB4N/P DB1P/N DB2N/P — —
11101 DB2P/N DB3N/P DB0P/N DB1N/P — —
11110 DB1P/N DB2N/P — DB0N/P — —
11111 DB0P/N DB1N/P — — — —
Note: Register 0x18 resets to 0x00 (default).
DAP/N[15:0] 0xAAAA
0xAAAA 0xAAAA
2000A F08
0xAAAA0x5555
0x5555 0x5555
0x5555
DBP/N[15:0]
DCKI
Figure 8. Sample Pattern for Measuring LVDS Input Timing Skew (LTC2000A-16)
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OPERATION
Measuring Internal Junction Temperature (TJ)
The LTC2000A test multiplexer may also be used to connect
internal junction temperature measurement diodes to the
TSTP/N pins. Ensure LMX_EN = 0 (register address 0x18)
and use SPI register 0x19 to set TDIO_EN = 1 to enable
this function (Table 9). There are two methods the user can
choose from to measure internal junction temperature (TJ).
For TDIO_SEL = 0, an unbiased NPN transistor is diode-
connected between the TSTP/N pins with a series resistance
of approximately 350Ω. This diode is suitable for use with
external temperature sensors which offer series resistance
cancellation such as the LTC2991 or LTC2997.
If such a temperature sensor is not available, set
TDIO_SEL=1 to directly observe a temperature dependent
voltage between TSTP and TSTN. The typical expected
voltage at TSTP is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25°C).
The junction temperature can be calculated as TJ = 25°C +
(2.02V – VTSTP)/(5.5mV/°C). For best accuracy with
TDIO_SEL=1, use TSTN to sense GND at the bottom of
the diode and calibrate the voltage at a known tempera-
ture. Typical uncalibrated accuracy is ±5°C.
Pattern Generator
A 64 sample deep pattern generator is included in the
LTC2000A to simplify system development and debug. The
pattern generator allows the user to send a repeating 64 sample
pattern to the DAC, completely independent of the presence
or absence of valid signals on DCKIP/N, DAP/N, and DBP/N.
Table 9. Internal Junction Temperature SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x19 0 TDIO_EN TSTP/N Junction Temperature Diode Enable. Set TDIO_EN = 1 to measure internal junction temperature (TJ) at TSTP/N.
Ensure LMX_EN = 0 when TDIO_EN = 1.
1 TDIO_SEL Selects which internal temperature diode is observable at TSTP/N.
For TDIO_SEL = 1, the typical voltage at TSTP with respect to TSTN is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25ºC).
Junction temperature can be calculated as TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). Typical accuracy is ±5°C.
For TDIO_SEL = 0, an unbiased diode is connected b/w TSTP/N for use with external temperature sensors.
Note: Register 0x19 resets to 0x00 (default).
To use this feature, do the following:
1. Set DCKO_DIV = 0 in register 0x02, DATA_SP = 0 and
DATA_EN = 0 in register 0x04, and PGEN_EN = 0 in
register 0x1E.
2. Write 128 bytes of pattern data to address 0x1F (PGEN_D)
to fill the pattern generator with 64 samples. Data is writ-
ten MSB first, and will be applied to the DAC in the order
written. Data may be written one byte at a time or in larger
multi-byte words. For the LTC2000A-14 and LTC2000A-11,
data should be left justified with zeros filling the remaining
two (LTC2000A-14) or five (LTC2000A-11) bits.
3. Set PGEN_EN = 1 to start the pattern generator.
4. Wait at least 1ms to ensure that the synchronizer has
initialized.
5. Set DATA_EN = 1 in register 0x04. The DAC will then
begin to output the 64 sample pattern.
The pattern generator will send the repeating 64 sample
pattern to the DAC until the user writes PGEN_EN = 0 or
DATA_EN = 0.
To read back the pattern, set DATA_EN = 0 and PGEN_EN
= 0 and then read 128 bytes from address 0x1F. Note that
the starting point of the pattern may have changed while the
pattern was running. To modify the pattern, set DATA_EN =
0 and PGEN_EN = 0 and write a new 64 sample pattern to
address 0x1F. Ensure PGEN_EN = 0 when reading or writ-
ing to address 0x1F, and always read or write an entire 64
sample pattern prior to setting PGEN_EN = 1. See Table 10.
Table 10 – Pattern Generator SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x1E 0 PGEN_EN Pattern Generator Enable. Set PGEN_EN = 1 to use the internal 64 sample pattern generator to provide data to the DAC.
Set DATA_SP = 0, DCKO_DIV = 0, and DATA_EN = 1 when PGEN_EN = 1.
0x1F [7:0] PGEN_D Pattern Generator Data. Write 128 bytes of data to this address to fill the pattern generator with 64 samples.
Data is written MSB first. Reading this location causes the pattern generator data to be shifted out through SDO.
Ensure PGEN_EN = 0 when reading or writing to address 0x1F. Read or write an even number of bytes to address
0x1F prior to setting PGEN_EN = 1 to avoid corrupting the data inside the pattern generator.
Note: Registers 0x1E and 0x1F reset to 0x00 (default).
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SPI REGISTER SUMMARY
ADDRESS BIT NAME DESCRIPTION
RESET
VALUE R/W
0x00 [7:0] Reserved Reserved
0x01 0 SW_RST Software Reset. SW_RST = 1 resets all registers. 0 R/W
1 DAC_PD DAC Power Down. DAC_PD = 1 to power down DAC core. 0 R/W
2 FULL_PD Full Power Down. FULL_PD = 1 to power down LTC2000A. 0 R/W
3 Reserved Reserved
[5:4] DAC_RES DAC Resolution Indicator. DAC_RES = 00 for LTC2000A-16. DAC_RES = 01 for LTC2000A-14.
DAC_RES = 11 for LTC2000A-11. Note that for PD = GND or FULL_PD = 1, DAC_RES = 00.
DAC_RES is read only.
00-16b
01-14b
11-11b
R
[7:6] Reserved Reserved
0x02 0 CK_PD CKP/N Clock Receiver Power Down. CK_PD = 1 disables 0 R/W
1 CK_OK CKP/N Clock Present Indicator. CK_OK = 1 clock present 0 R
[3:2] Reserved Reserved
4 DCKO_DIS DCKOP/N Output Disable. DCKO_DIS = 1 disables 0 R/W
5 DCKO_DIV DCKOP/N Divide Select. (0 = fDAC/4, 1 = fDAC/2). 0 R/W
6 DCKO_ISEL DCKOP/N Output Current Select. (0=3.5mA, 1 = 7mA) 0 R/W
7 DCKO_TRM DCKOP/N Internal Termination On. DCKO_TRM = 1 enables internal 100Ω termination 0 R/W
0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables. 0 R/W
1 DCKI_OK DCKIP/N Clock Present Indicator. DCKI_OK = 1 indicates clock present 0 R
2 DCKI_Q DCKIP/N Quadrature Phase Select. (0 = In Phase, 1 = Quadrature) 0 R/W
3 Reserved Reserved
[6:4] DCKI_TADJ DCKIP/N Delay Adjust. (See Table 4) 000 R/W
7Reserved Reserved
0x04 0 DA_EN Port A LVDS Receiver Enable. DA_EN = 1 enables 0 R/W
1 DB_EN Port B LVDS Receiver Enable. DB_EN = 1 enables 0 R/W
2 DATA_SP Port Mode Select. (0 = Dual port, 1 = Single port) 0 R/W
3 DATA_EN DAC Data Enable. DATA_EN = 0 forces DAC output to mid-scale. 0 R/W
[7:4] Reserved Reserved
0x05 [1:0] SYNC_PS Clock Synchronizer Phase Select. 00 R/W
2 SYNC_MSYN Clock Synchronizer Manual Mode Select.
SYNC_MSYN = 0: SYNC_PS is set automatically.
SYNC_MSYN = 1: SYNC_PS is set by the user.
0 R/W
[7:3] Reserved Reserved
0x06 [7:0] SYNC_PH Clock Phase Comparator Outputs. (See Table 6) 0x00 R
0x07 0 LIN_DIS Dynamic Linearization Disable. LIN_DIS = 1 disables. 0 R/W
[3:1] LIN_GN Dynamic Linearization Gain Select. (See Table 7) 000 R/W
[7:4] Reserved Reserved
0x08 [3:0] LIN_VMX Dynamic Linearization Max IOUTP/N Voltage Select. (See Table 7) 1000 R/W
[7:4] LIN_VMN Dynamic Linearization Min IOUTP/N Voltage Select. (See Table 7) 0000 R/W
Table 11. SPI Register List
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SPI REGISTER SUMMARY
ADDRESS BIT NAME DESCRIPTION
RESET
VALUE R/W
0x09 [5:0] GAIN_ADJ DAC Gain Adjustment. (See Table 2) 0x00 R/W
[7:6] Reserved Reserved
0x0A Thru
0x17
[7:0] Reserved Reserved
0x18 0 LMX_MSEL LVDS Test MUX Select. (See Table 8) 0 R/W
[5:1] LMX_ADR LVDS Test MUX Address Select. (See Table 8) 0x00 R/W
6 LMX_EN LVDS Test MUX Enable. LMX_EN = 1 enables LVDS text MUX. Ensure TDIO_EN = 0 when
LMX_EN = 1.
7 Reserved Reserved
0x19 0 TDIO_EN TSTP/N Junction Temperature Diode Enable.
TDIO_EN = 1 enables temperature (TJ) measurement.
Ensure LMX_EN = 0 when TDIO_EN = 1.
0 R/W
1 TDIO_SEL Junction Temperature Select. TDIO_SEL = 0 uses a diode-connected unbiased NPN transistor.
TDIO_SEL = 1 outputs a voltage to calculate internal die temperature using:
TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). (See Table 9)
0 R/W
[7:2] Reserved Reserved
0x1A Thru
0x1D
[7:0] Reserved Reserved
0x1E 0 PGEN_EN Pattern Generator Enable. PGEN_EN = 1 enables. 0 R/W
[7:1] Reserved Reserved
0x1F [7:0] PGEN_D Pattern Generator Data. 0x00 R/W
0x20 Thru
0x7F
[7:0] Reserved Reserved
Table 11. SPI Register List (cont)
APPLICATIONS INFORMATION
Sample Start-Up Sequence
The following is an example of a common start-up
sequence.
1. Apply valid supply voltages to AVDD33, DVDD33,
AVDD18, DVDD18 and SVDD.
2. Write 0x01 to address 0x01 to perform a software
reset.
3. Apply a clock to CKP/N at the desired fDAC frequency.
The LTC2000A will generate a clock at DCKOP/N at
fDAC/4.
4. Apply a clock to DCKIP/N at fDAC/4 for dual-port mode
or fDAC/2 for single-port mode.
5. Apply zeroes to ports A and B (DAP/N, DBP/N) for
dual-port mode, or only to port B for single-port mode.
6. Write to address 0x03 to enable the DCKIP/N LVDS
receiver. Set address 0x03 to 0x01 if the LVDS clock
(DCKI) and data (DA, DB) are in phase with each other.
Set address 0x03 to 0x05 if they are in quadrature.
7. Write 0x03 to address 0x04 for dual-port mode, or
write 0x06 to address 0x04 for single-port mode to
enable the DAP/N and DBP/N LVDS receivers.
8. Wait at least 1ms for the synchronizer to finish
initializing.
9. Write 0x0B to address 0x04 for dual-port mode, or
write 0x0E to address 0x04 for single-port mode to
set DATA_EN = 1.
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APPLICATIONS INFORMATION
10. Apply desired data pattern to ports A and B (DAP/N,
DBP/N) for dual-port mode, or only to port B for
single-port mode. Port A samples will precede portB
samples at the DAC output when using dual-port
mode.
Output Configurations
The LTC2000A’s complementary current outputs (IOUTP/N)
source current into an external load referenced to GND.
Output load configuration, component selection, and layout
are critical to the performance of the LTC2000A. For best
AC performance, the output stages should be configured
for differential (or balanced) operation.
A differential resistor loaded output is a very simple output
stage. Well matched resistors are connected between GND
and IOUTP/N, with the resistance values setting both the
output swing and non-zero output common-mode voltage
(Figure 9). While it is economical, this type of output stage
can drive only differential loads with impedance levels and
amplitudes appropriate for the DAC outputs.
Differential transformer-coupled output configurations
usually give the best AC performance and provide excel-
lent rejection of common mode distortion and noise over
a broad frequency range. Figure 10 shows a transformer
output configuration that uses a Mini-Circuits TC1-1-13M
and a JTX-2-10T RF transformer for differential to single-
ended conversion.
IOUTP
R R
2000A F09
LTC2000A
IOUTN
Figure 9. Differential Resistor Output Load
Figure 10. Transformer-Based Output Configuration
for Differential to Single-Ended Conversion
IOUTP
2000A F10
LTC2000A
MINI-CIRCUITS
TC1-1-13M MINI-CIRCUITS
JTX-2-10T
••
IOUTN
• •
For any output configuration, any imbalances in the output
impedance between the IOUTP and IOUTN pins results in
asymmetrical signal swings that lead to distortion (mostly
even order). Careful consideration is needed to select the
best output configuration for a given application.
Generating the DAC Sample Clock
For best AC performance, it is important that the DAC
sample clock waveforms be clean, with low phase noise
and good jitter performance, as the phase noise and spuri-
ous content of the clock source will appear directly in the
DAC output spectrum.
A differential clock should be AC coupled onto the CKP/N
pins, since the DC bias point of CKP/N is set internally to
1V through a 5kΩ impedance. Figure 11 shows the DAC
sample clock receiver input and common-mode voltage
control. While the differential input voltage range of the
clock receiver spans from ±300mV to ±1.8V, a signal with
the highest possible slew rate and amplitude and a bal-
anced duty cycle is recommended. Traces that carry the
differential clock signal need to have accurately controlled
impedance and accurate termination as close to the CKP/N
pins of the LTC2000A as possible.
There are several ways to generate the DAC sample clock.
For lab evaluation and testing, a high quality RF signal
generator can provide a clean high frequency sine wave
that is converted to the DAC sample clock with a 1:1 RF
transformer or balun (see Figure 12).
Figure 11. DAC Sample Clock Receiver
5k
AVDD18
1V
LTC2000A
5k
CKP
CKN
GND
2000A F11
LTC2000A
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For more information www.linear.com/LTC2000A
APPLICATIONS INFORMATION
A more integrated clock source is one based on a low
phase noise, low jitter PLL. Figure 13 shows how the
DAC sample clock can be generated from the LTC6946,
a high performance PLL with an internal VCO that can
provide output frequencies from 0.37GHz to 5.7GHz. See
the LTC6946 data sheet for details.
Synchronizing Multiple LTC2000As in Dual-Port Mode
In some applications, it is necessary to synchronize mul-
tiple LTC2000As to each other such that related samples
arrive at all DAC outputs simultaneously. Figures 14 and
15a show a block diagram and sample waveforms for
such a system in which two DACs (X and Y) are to be
synchronized in dual-port mode.
Note that in this example a small timing skew between
the two data signals at the DCKIP/N pins of DACs X and
Y has caused the DCKIP/N rising edges to arrive on op-
posite sides of a DAC sample clock (CKP/N) rising edge,
and thus within different CKP/N clock cycles. As a result
the default behavior is for the output of DAC Y to update
with sample N one cycle earlier than the output of DAC X.
It is possible to correct this misalignment and synchro-
nize DACs X and Y by adjusting the clock synchronizer
settings to subtract one cycle of latency from DAC X, as
shown in the adjusted waveform at the bottom of Figure
15a. See the Clock Synchronizer section and Figure 7 for
more details on the operation of the clock synchronizer.
In order to synchronize multiple DACs as shown in Fig-
ures14 and 15a, distribute the DAC sample clock carefully
with matched delays so that it arrives at the CKP/N pins of
all DACs simultaneously. Any remaining timing mismatch
between sample clocks will appear directly as mismatch in
the DAC output timing. Ensure that the timing mismatch
between LVDS data clock signals at the DCKIP/N pins of all
DACs is less than 0.4 cycles of the DAC sample clock, mi-
nus any timing mismatch between the DAC sample clocks.
Be sure to maintain sufficient matching between the timing
of the LVDS data inputs (DAP/N, DBP/N) and DCKIP/N for
each DAC to meet the setup and hold time specifications
(t11, t12) in the Timing Characteristics section.
For example, let us consider a system using multiple DACs
at 2.7Gsps in which the sample clock is designed to arrive
at the CKP/N pins of all DACs within 30ps of one another.
The sample clock period is 370ps, so the maximum allow-
able timing mismatch between the data clock signals at
the DCKIP/N pins of all DACs will be (0.4 • 370ps) – 30ps
= 118ps. For a system using multiple DACs at 1.35Gsps,
the allowable mismatch between DCKIP/N pins will be (0.4
• 740ps) – 30ps = 266ps. In both cases, once the DACs
÷N = 250
÷O = 1
N_DIV
÷R = 10
fPFD REF±
(fREF)fREF*100pF
+
+
100pF
L1
68nH
LTC6946
KPFD
fVCO
KVCO
ICP =
11.2mA VRF+
CP
LOOP FILTER
LF(s)
2000A F13
TUNE
RZ
453Ω
50Ω
50Ω 100pF
CI
0.022µF
R_DIV
O_DIV RF±
*CRYSTEK CVHD-950-100.000 100MHz OSCILLATOR
RF+
RF–
(fRF)
25
15
CP
2700pF
L2
68nH
+
CKP
CKN
LTC2000A
Figure 13. DAC Sample Clock Generation with the LTC6946
Figure 12. DAC Sample Clock Generation with an
RF Signal Generator and a 1:1 Balun
+
50Ω
••
50Ω 100pF
LTC2000A F12
+
+
1nF
1nF
50Ω
LTC2000A
MINI-CIRCUITS
TC1-1-13M
RF SIGNAL
GENERATOR
CKP
CKN
LTC2000A
38
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For more information www.linear.com/LTC2000A
APPLICATIONS INFORMATION
are synchronized the mismatch in the DAC output timing
will be limited to 30ps.
Once all the DAC sample clocks and LVDS data clocks are
aligned, determine whether any DACs are being updated
one cycle late (such as DAC X in Figure 15a) by determining
whether DCKIP/N is arriving at the DACs within the same
CKP/N clock cycle. To do this in dual-port mode, first use
the phase comparator outputs SYNC_PH and Table12
to determine the delay from the DCKIP/N rising edge to
the next CKP/N rising edge for each DAC (measured in
sample clock cycles).
Recall that the DCKIP/N timing mismatch must be kept
below 0.4 cycles of the sample clock. If DCKIP/N ar-
rives at both DACs within the same sample clock cycle,
the difference in DCKIP/N to CKP/N delays indicated by
SYNC_PH will equal the actual DCKIP/N timing mismatch,
and thus will be less than 0.4 cycles. If DCKIP/N arrives
at the DACs within different cycles, as in Figure 15a, the
difference in the delays indicated by SYNC_PH will equal
1 cycle minus the actual DCKIP/N timing mismatch, and
thus will be greater than 0.4 cycles. Thus if the difference
between the delays indicated by SYNC_PH is greater than
CKP/N
DAC X
LTC2000A
DCKIP/N
LVDS DATA
LVDS CLK
MATCHED
DELAYS
MATCHED
DELAYS
DAP/N
DBP/N
CKP/N
DAC Y
LTC2000A
DCKIP/N
2000A F14
LVDS DATA
LVDS CLK
DAP/N
DBP/N
CLOCK
SOURCE
FPGA
DAP/N[15:0] N N+2 N+4 N+6 N+8 N+10
DBP/N[15:0]
DAC X
DCKIP/N
DAC X
IOUTP/N
DAC X
IOUTP/N
(ADJUSTED)
DAC Y
IOUTP/N
DAC Y
DCKIP/N
CKP/N
N+1 N+3
0.9
CYCLES
0.1 CYCLES 10 CYCLES
N
2000A F15a
N+5 N+7 N+9 N+11
N N+1
N N+1
9 CYCLES
10 CYCLES
Figure 14. System with Multiple LTC2000A DACs Synchronized
Figure 15a. Sample Waveforms — Synchronizing Multiple LTC2000As in Dual Port Mode
LTC2000A
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For more information www.linear.com/LTC2000A
APPLICATIONS INFORMATION
0.4 cycles, the DCKIP/N rising edges are arriving in dif-
ferent sample clock cycles.
For the example in Figure 15a, we might read 0x25 for
SYNC_PH on DAC X and 0x52 on DAC Y. Table 12 tells us
that the DCKIP/N to CKP/N delay is greater than 0.8 cycles
for DAC X and less than 0.2 cycles for DAC Y, and thus the
difference between them is at least 0.6 cycles. We conclude
that the DCKIP/N rising edge of DAC X must fall within
a later sample clock cycle than that of DAC Y, and thus
that DAC X is being updated one cycle later than DAC Y.
To correct any such misalignment and synchronize the
DACs, consult Table 12 and adjust the SYNC_PS settings
for those DACs which are being updated one cycle late
(DAC X in the above example) by setting the synchronizer
to manual mode (SYNC_MSYN = 1) and overwriting the
SYNC_PS value.
In this example, reading register 0x06 of DAC X shows
SYNC_PH = 0x25 and that the SYNC_PS setting needs to
change from the default (10) to the desired adjusted value
(00), subtracting one cycle from the latency of DAC X (refer
to Table 12). Write 0x04 to register 0x05 of DAC X to set
SYNC_MSYN = 1 and SYNC_PS = 00. The outputs of DAC
X should now align with DAC Y as shown in Figure15a.
See Table 6 for details regarding the synchronizer registers
0x05 and 0x06. Sample verilog code implementing the
synchronization of multiple LTC2000As using Tables 12
and 13 can be found at:
http://www.linear.com/docs/44845
Synchronizing Multiple LTC2000As in Single-Port Mode
Figure 15b shows sample waveforms for synchronizing two
LTC2000As in single port mode. Synchronizing multiple
LTC2000As in single port mode is essentially the same
Table 12. Adjusting Latency in Dual-Port Mode
PHASE COMPARATOR OUTPUTS
SYNC_PH (REG 0x06)
DELAY FROM DCKIP/N RISING
EDGE TO NEXT CKP/N RISING EDGE
(CKP/N CYCLES)
SYNC_PS SETTING
(DEFAULT)
(ADJUSTED TO REDUCE LATENCY
BY 1 CYCLE)*
0x03 0 to 0.2 10 N/A
0x04 0.2 to 0.4 10 N/A
0x05 0.4 to 0.6 10 N/A
0x15 0.6 to 0.8 10 00
0x25 0.8 to 1.0 10 00
0x35 0 to 0.2 00 N/A
0x45 0.2 to 0.4 00 N/A
0x55 0.4 to 0.6 00 N/A
0x54 0.6 to 0.8 00 01
0x53 0.8 to 1.0 00 01
0x52 0 to 0.2 01 N/A
0x51 0.2 to 0.4 01 N/A
0x50 0.4 to 0.6 01 N/A
0x40 0.6 to 0.8 01 11
0x30 0.8 to 1.0 01 11
0x20 0 to 0.2 11 N/A
0x10 0.2 to 0.4 11 N/A
0x00 0.4 to 0.6 11 N/A
0x01 0.6 to 0.8 11 10
0x02 0.8 to 1.0 11 10
*N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs,
keep SYNC_PS as the default value.
LTC2000A
40
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For more information www.linear.com/LTC2000A
APPLICATIONS INFORMATION
procedure as when operating in dual port mode—DAC
sample clocks must all be aligned to arrive at the CKP/N
pins of all DACs simultaneously and timing mismatch
between LVDS data clock signals at the DCKIP/N pins of
all DACs must be less than 0.4 cycles of the DAC sample
clock, minus any timing mismatch between the DAC
sample clocks.
To determine whether any DACs are being updated one
cycle late in single port mode, first use the phase compara-
tor outputs SYNC_PH and Table 13 to determine the delay
from the DCKIP/N rising edge to the next CKP/N falling
edge (as opposed to rising edge in dual port mode) for
each DAC. If the difference between the delays indicated
by SYNC_PH is greater than 0.4 cycles, the DCKIP/N ris-
ing edges are arriving in different sample clock cycles.
For the example in Figure 15b, we might read 0x15 for
SYNC_PH on DAC X and 0x20 on DAC Y. Table 13 shows
that the DCKIP/N to CKP/N delay is greater than 0.8 cycles
for DAC X and less than 0.1 cycles for DAC Y, and thus the
difference between them is at least 0.7 cycles. This indicates
that DAC X is being updated one cycle later than DAC Y.
Consult Table 13 and use the same procedure described
above in the dual-port mode case to correct the SYNC_PS
settings for those DACs that are updating one cycle late.
In this single port example, writing 0x06 to register 0x05
of DAC X would set SYNC_MSYN = 1 and SYNC_PS = 10,
reducing the latency of DAC X by one cycle and aligning
its output with DAC Y, as shown in Figure 15b.
Note that variations in system temperature or supply
voltage may cause the phase of the data clock (DCKIP/N)
and sample clock (CKP/N) to vary with time. When using
the LTC2000A with SYNC_MSYN = 1, it is recommended
that users monitor SYNC_PH and adjust SYNC_PS using
Tables 12 or 13 as needed to maintain proper alignment.
The synchronization procedures described above also work
for systems with more than two DACs. Simply determine
the minimum DCKIP/N to CKP/N delay of all DACs by
reading SYNC_PH, and then adjust the SYNC_PS settings
to subtract one cycle of latency to those DACs whose
DCKIP/N to CKP/N delays are at least 0.4 cycles more
than the minimum. Sample verilog code implementing the
synchronization of multiple LTC2000As using Tables12
and 13 can be found at:
http://www.linear.com/docs/44845
DBP/N[15:0]
DAC X
DCKIP/N
DAC X
IOUTP/N
DAC X
IOUTP/N
(ADJUSTED)
DAC Y
IOUTP/N
DAC Y
DCKIP/N
CKP/N
N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
0.8 CYCLES
0.1 CYCLES 7.5 CYCLES
N
2000A F15b
N N+2N+1
N N+2N+1
N+1
6.5 CYCLES
7.5 CYCLES
Figure 15b. Sample Waveforms — Synchronizing Multiple LTC2000As in Single Port Mode
LTC2000A
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APPLICATIONS INFORMATION
Table 13. Adjusting Latency in Single-Port Mode
PHASE COMPARATOR OUTPUTS
SYNC_PH (REG 0x06)
DELAY FROM DCKIP/N RISING
EDGE TO NEXT CKP/N FALLING
EDGE (CKP/N CYCLES)
SYNC_PS SETTING
(DEFAULT)
(ADJUSTED TO REDUCE LATENCY
BY 1 CYCLE)*
0x03 0.5 to 0.6 00 N/A
0x04 0.6 to 0.7 00 10
0x05 0.7 to 0.8 00 10
0x15 0.8 to 0.9 00 10
0x25 0.9 to 1.0 00 10
0x35 0 to 0.1 10 N/A
0x45 0.1 to 0.2 10 N/A
0x55 0.2 to 0.3 10 N/A
0x54 0.3 to 0.4 10 N/A
0x53 0.4 to 0.5 10 N/A
0x52 0.5 to 0.6 10 N/A
0x51 0.6 to 0.7 10 00
0x50 0.7 to 0.8 10 00
0x40 0.8 to 0.9 10 00
0x30 0.9 to 1.0 10 00
0x20 0 to 0.1 00 N/A
0x10 0.1 to 0.2 00 N/A
0x00 0.2 to 0.3 00 N/A
0x01 0.3 to 0.4 00 N/A
0x02 0.4 to 0.5 00 N/A
*N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs,
keep SYNC_PS as the default value.
PCB Layout Considerations
The close proximity of high frequency digital data lines
and high dynamic range, wideband analog signals make
clean printed circuit board design and layout an absolute
necessity. Figures 16 and 17 show a schematic and PCB
layers for an evaluation circuit for the LTC2000A. A single,
solid ground plane should be used, while separate supply
planes for AVDD18, DVDD18, AVDD33, and DVDD33 should
be kept all the way to the individual supply or LDO. All
LVDS input (DCKIP/N, DAP/N, DBP/N) board traces must
be carefully matched to ensure proper phase alignment.
These LVDS inputs should be kept far away from both the
IOUTP/N and CKP/N traces to avoid any data dependent
coupling into the analog output and DAC sample clock.
The CKP/N traces should be routed either over the analog
ground plane or over their own section on the ground plane.
These traces also need to have accurately controlled imped-
ance and should be well terminated near the LTC2000A.
The IOUTP/N traces should also be carefully matched to
each other, routed over the ground plane, away from the
LVDS inputs and CKP/N signals.
Bypass capacitors are required on AVDD18, DVDD18, AVDD33,
and DVDD33, and should all be connected to the analog
ground plane. 2.2µF ceramic capacitors with low ESR
are recommended to be placed close to the LTC2000A
with minimum trace lengths. A sample PCB layout and
schematic can be found below.
LTC2000A
42
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For more information www.linear.com/LTC2000A
APPLICATIONS INFORMATION
DAP[15:0]
DAN[15:0]
DCKIP
DCKIN
DBP[15:0]
DBN[15:0]
SVDD
AVDD33
DVDD33
AVDD18
DVDD18
DCKOP
DCKON
CKP
R29
50Ω
R26
50Ω CKN
TSTP
TSTN
IOUTP
IOUTN
S1
S2
S3
S4
S5
R4
R3
REFIO
FSADJ
2000A F16
M1
M2
H1
J1
PD
CS
SDO
SDI
SCK
J10
MATCHED LVDS
DATA AND CLOCK
LINES FROM FPGA
SPI
PORTS
J8
K8
K7
3.3V
1.8V
47µF
47µF
LTC2000A
GND
C43
0.01µF
C66
1pF
C42
100pF
6
1
2
3
5
GND
GND
IN
4
C41
100pF
T1
ANAREN
B0430J50100AHF
C47
10pF
L6
1nH
CLOCK
SOURCE
R40
50Ω
R46
50Ω
R45
500Ω
C40
10µF
R47
50Ω
R48
50Ω
Figure 16
Layer 2Layer 1
LTC2000A
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For more information www.linear.com/LTC2000A
PIN LOCATIONS (LTC2000A-16)
LTC2000A-16 BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND
A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND
A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND
A4 GND B4 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND
A5 DVDD18 B5 DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND
A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND
A7 DAN15 B7 DAN14 C7 DAN13 D7 DAN12 E7 DAN11 F7 DAN10
A8 DAP15 B8 DAP14 C8 DAP13 D8 DAP12 E8 DAP11 F8 DAP10
A9 DBN15 B9 DBN14 C9 DBN13 D9 DBN12 E9 DBN11 F9 DBN10
A10 DBP15 B10 DBP14 C10 DBP13 D10 DBP12 E10 DBP11 F10 DBP10
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO
G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ
G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND
G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33
G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33
G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND
G7 DAN9 H7 DAN8 J7 DCKON K7 DAN7 L7 DAN6 M7 DAN5
G8 DAP9 H8 DAP8 J8 DCKOP K8 DAP7 L8 DAP6 M8 DAP5
G9 DBN9 H9 DBN8 J9 DCKIN K9 DBN7 L9 DBN6 M9 DBN5
G10 DBP9 H10 DBP8 J10 DCKIP K10 DBP7 L10 DBP6 M10 DBP5
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD
N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS
N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO
N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI
N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK
N6 GND P6 GND Q6 GND R6 GND S6 SVDD
N7 DAN4 P7 DAN3 Q7 DAN2 R7 DAN1 S7 DAN0
N8 DAP4 P8 DAP3 Q8 DAP2 R8 DAP1 S8 DAP0
N9 DBN4 P9 DBN3 Q9 DBN2 R9 DBN1 S9 DBN0
N10 DBP4 P10 DBP3 Q10 DBP2 R10 DBP1 S10 DBPO
LTC2000A
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For more information www.linear.com/LTC2000A
PIN LOCATIONS (LTC2000A-16)
1
S
R
Q
P
N
M
L
K
J
H
DVDD33
AVDD33
GND
GND
GND
GND
REFIO FSADJ
PD CS
GND
CKN CKP
GND
GND DAN2 DAP2 DBN2 DBP2
DAN3 DAP3 DBN3 DBP3
DAN4 DAP4 DBN4 DBP4
DAN5 DAP5 DBN5 DBP5
DAN6 DAP6 DBN6 DBP6
DAN7 DAP7 DBN7 DBP7
DCKON DCKOP
IOUTN
IOUTP
DCKIPDCKIN
DAN8 DAP8 DBN8 DBP8
DAN9 DAP9 DBN9 DBP9
DAN10 DAP10 DBN10 DBP10
DAN11 DAP11 DBN11 DBP11
DAN12 DAP12 DBN12 DBP12
DAN13 DAP13 DBN13 DBP13
DAN14 DAP14 DBN14 DBP14
DAN15 DAP15 DBN15 DBP15
TSTN TSTP DAN1 DAP1 DBN1 DBP1
SDO SDI SCK SVDD DAN0 DAP0 DBN0 DBP0
G
F
E
D
C
B
A
2345678910
TOP VIEW
AVDD18
DVDD18
LTC2000A
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For more information www.linear.com/LTC2000A
PIN LOCATIONS (LTC2000A-14)
LTC2000A-14 BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND
A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND
A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND
A4 GND B4 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND
A5 DVDD18 B5 DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND
A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND
A7 DAN13 B7 DAN12 C7 DAN11 D7 DAN10 E7 DAN9 F7 DAN8
A8 DAP13 B8 DAP12 C8 DAP11 D8 DAP10 E8 DAP9 F8 DAP8
A9 DBN13 B9 DBN12 C9 DBN11 D9 DBN10 E9 DBN9 F9 DBN8
A10 DBP13 B10 DBP12 C10 DBP11 D10 DBP10 E10 DBP9 F10 DBP8
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO
G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ
G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND
G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33
G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33
G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND
G7 DAN7 H7 DAN6 J7 DCKON K7 DAN5 L7 DAN4 M7 DAN3
G8 DAP7 H8 DAP6 J8 DCKOP K8 DAP5 L8 DAP4 M8 DAP3
G9 DBN7 H9 DBN6 J9 DCKIN K9 DBN5 L9 DBN4 M9 DBN3
G10 DBP7 H10 DBP6 J10 DCKIP K10 DBP5 L10 DBP4 M10 DBP3
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD
N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS
N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO
N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI
N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK
N6 GND P6 GND Q6 GND R6 GND S6 SVDD
N7 DAN2 P7 DAN1 Q7 DAN0 R7 GND S7 GND
N8 DAP2 P8 DAP1 Q8 DAP0 R8 GND S8 GND
N9 DBN2 P9 DBN1 Q9 DBN0 R9 GND S9 GND
N10 DBP2 P10 DBP1 Q10 DBP0 R10 GND S10 GND
LTC2000A
49
2000afb
For more information www.linear.com/LTC2000A
PIN LOCATIONS (LTC2000A-14)
1
S
R
Q
P
N
M
L
K
J
H
GND
AVDD33
DVDD33
TSTN TSTP
PD CS SDO SDI SCK SVDD
GND
DAN0 DAP0 DBN0 DBP0
DAN1 DAP1 DBN1 DBP1
DAN2 DAP2 DBN2 DBP2
DAN3 DAP3 DBN3 DBP3
DAN4 DAP4 DBN4 DBP4
DAN5 DAP5 DBN5 DBP5
DCKON DCKOP DCKIN DCKIP
DAN6 DAP6 DBN6 DBP6
DAN7 DAP7 DBN7 DBP7
DAN8 DAP8 DBN8 DBP8
DAN9 DAP9 DBN9 DBP9
DAN10 DAP10 DBN10 DBP10
DAN11 DAP11 DBN11 DBP11
DAN12 DAP12 DBN12 DBP12
DAN13 DAP13 DBN13 DBP13
GND
GND
GND
AVDD18
IOUTP
IOUTN
REFIO FSADJ
DVDD18
CKN CKP
G
F
E
D
C
B
A
2345678910
TOP VIEW
LTC2000A
50
2000afb
For more information www.linear.com/LTC2000A
PIN LOCATIONS (LTC2000A-11)
LTC2000A-11 BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND
A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND
A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND
A4 GND B4 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND
A5 DVDD18 B5 DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND
A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND
A7 DAN10 B7 DAN9 C7 DAN8 D7 DAN7 E7 DAN6 F7 DAN5
A8 DAP10 B8 DAP9 C8 DAP8 D8 DAP7 E8 DAP6 F8 DAP5
A9 DBN10 B9 DBN9 C9 DBN8 D9 DBN7 E9 DBN6 F9 DBN5
A10 DBP10 B10 DBP9 C10 DBP8 D10 DBP7 E10 DBP6 F10 DBP5
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO
G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ
G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND
G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33
G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33
G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND
G7 DAN4 H7 DAN3 J7 DCKON K7 DAN2 L7 DAN1 M7 DAN0
G8 DAP4 H8 DAP3 J8 DCKOP K8 DAP2 L8 DAP1 M8 DAP0
G9 DBN4 H9 DBN3 J9 DCKIN K9 DBN2 L9 DBN1 M9 DBN0
G10 DBP4 H10 DBP3 J10 DCKIP K10 DBP2 L10 DBP1 M10 DBP0
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD
N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS
N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO
N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI
N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK
N6 GND P6 GND Q6 GND R6 GND S6 SVDD
N7 GND P7 GND Q7 GND R7 GND S7 GND
N8 GND P8 GND Q8 GND R8 GND S8 GND
N9 GND P9 GND Q9 GND R9 GND S9 GND
N10 GND P10 GND Q10 GND R10 GND S10 GND
LTC2000A
51
2000afb
For more information www.linear.com/LTC2000A
PIN LOCATIONS (LTC2000A-11)
1
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2345678910
TOP VIEW
GND
PD CS SDO SDI
TSTN TSTP
SCK SVDD
GND
DANO DAPO DBNO DBPO
DAN1 DAP1 DBN1 DBP1
DAN2 DAP2 DBN2 DBP2
DAN3 DAP3 DBN3 DBP3
DAN4 DAP4 DBN4 DBP4
DAN5 DAP5 DBN5 DBP5
DAN6 DAP6 DBN6 DBP6
DAN7 DAP7 DBN7 DBP7
DAN8 DAP8 DBN8 DBP8
DAN9 DAP9 DBN9 DBP9
DAN10 DAP10 DBN10 DBP10
DCKON DCKOP DCKIN DCKIP
GND
AVDD33
DVDD18
AVDD18
DVDD33
GND
IOUTP
IOUTN
REFIO FSADJ
GND
CKN CKP
LTC2000A
52
2000afb
For more information www.linear.com/LTC2000A
PACKAGE DESCRIPTION
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
12345610 9 8 7
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
YX
aaa Z
aaa Z
DETAIL A
PACKAGE BOTTOM VIEW
3
SEE NOTES PIN 1
BGA Package
170-Lead (15.00mm × 9.00mm × 1.54mm)
(Reference LTC DWG# 05-08-1890 Rev C)
BGA 170 0517 REV C
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
DETAIL A
Øb (170 PLACES)
A
DETAIL B
PACKAGE SIDE VIEW
MX YZddd
MZeee
A2
D
E
e
e
b
F
G
SUGGESTED PCB LAYOUT
TOP VIEW
0.00
3.20
3.20
6.40
4.00
4.00
4.80
4.80
5.60
5.60
6.40
0.80
0.80
1.60
1.60
2.40
2.40
3.60
2.80
2.00
2.80
1.20
0.40
2.00
1.20
0.40
3.60
0.00
5.35
5.85
LTXXXXXX
b
0.40 ±0.025 Ø 170x
3.05
2.55
6
SEE NOTES
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
1.39
0.35
1.04
0.45
0.37
0.39
0.65
NOM
1.54
0.40
1.14
0.50
0.40
15.00
9.00
0.80
12.80
7.20
0.44
0.70
MAX
1.69
0.45
1.24
0.55
0.43
0.49
0.75
0.15
0.10
0.12
0.15
0.08
TOTAL NUMBER OF BALLS: 170
DIMENSIONS
NOTES
BALL HT
BALL DIMENSION
PAD DIMENSION
SUBSTRATE THK
MOLD CAP HT
Z
5. PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
DETAIL B
SUBSTRATE
A1
ccc Z
Z
// bbb Z
H2
H1
b1
MOLD
CAP
Please refer to http://www.linear.com/product/LTC2000A#packaging for the most recent package drawings.
LTC2000A
53
2000afb
For more information www.linear.com/LTC2000A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 05/17 Added lead-finish option 4
B 12/17 Updated Measuring Internal Junction Temperature text to clarify series cancellation requirement 33
LTC2000A
54
2000afb
For more information www.linear.com/LTC2000A
LT 1217 REV B • PRINTED IN USA
www.linear.com/LTC2000A
ANALOG DEVICES, INC. 2015
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DAP[15:0]
DAN[15:0]
DCKIP
DCKIN
DBP[15:0]
DBN[15:0]
SVDD
AVDD18
DVDD18
DCKOP
DCKON
CKP
R29
50Ω
R26
50Ω CKN
TSTP
TSTN
IOUTN
IOUTP
S1
S2
S3
S4
S5
R4
R3
S6
REFIO
FSADJ
2000A TA01
M1
M2
H1
J1
PD
CS
SDO
SDI
SCK
J10
MATCHED LVDS
DATA AND CLOCK
LINES FROM FPGA
SPI
PORTS
J8
A3
A2
K8
K7
3.3V
LTC2000A-16
AVDD33
LT1763CS8-3.3
LT1763CS8-3.3
DVDD33
GND
C43
0.01µF
C66
1pF
C42
100pF
6
1
2
3
5
GND
GND
IN
4
C41
100pF
T1
ANAREN
B0430J50100AHF
C65
10pF
L6
1nH
CLOCK
SOURCE
R52
20Ω C66
47pF
L9
2.7nH
L8
2.7nH
L11
1.5nH 4
3
1 2
1 2
1 2
1 2
22
15
L10
1.5nH
L12
1.8nH
LO
INPUT
RF
OUTPUT
C65
47pF
R50
0Ω
R49
0Ω
C25
0.1µF
C26
0.1µF
R51
20Ω
1k
7.15k
R45
500Ω
C40
10µF
R53
11.5Ω
R54
11.5Ω
C68
82pF
C67
82pF
C68
22pF
C69
1.2pF
C74
10µF
C73
1µF
C72
100pF
C71
10pF
SHDN
IN
GND
GND
GND
OUT
SEN
BYP
1
2
5
8
3
6
7 4
0.01µF 47µF1µF
5V
SHDN
IN
GND
GND
GND
OUT
SEN
BYP
1
2
5
8
3
6
7 4
0.01µF 47µF1µF
5V SHDN
VIN
GND
GND
OUTF
OUTS
GND
GND
7
6
8
5
1
2
3
410µF
3.24k
4.7µF 1µF
1µF
5V
47µF
1µF
3.3V
IF–
LT5579
0.1dB CHEBYCHEV, BW = 535MHz
VCC
3.3V
GND
IF+
LO
RF
LTC6655CH
MS8-2.048
VOUT
VOUT
VOUT
PAD
SET
7
8
5
3
2
1
9
VIN
VIN
VCTRL
LT3080EDD 3.3V
3.24k
4.7µF
5V
47µF
VOUT
VOUT
VOUT
PAD
SET
7
8
5
3
2
1
9
VIN
VIN
VCTRL
LT3080EDD 3.3V
