HS3120B-2 - Spectrum Controls, Inc.

Double Buffered 12-Bit MD AC

H S 3120

Data Converter Line

FEA TURES

• M onolithic Construction

• 12-Bit Resolution

• 0.01% Non-Linearity

• jup Compatible

• 4-Quadrant M ultiplication

• Latch-up Protected

DESCRIPTION

The HS 3120 is a precision monolithic 12-bit

multiplying DAC with internal two-stage input

storage registers for easy interfacing with

microprocessor busses. It is packaged in a 28-pin DIP

to give high I/O design f lexibility.

DOUBLE BUFFERED —The input registers are sectioned

into 3 segments of 4 bits each, all individually

addressable. The DAC register, following the input

registers, is a parallel 12-bit register for holding the

DAC data while the input registers are updated. Only

the data held in the DA C register determines the

analog output value of the converter.

M ICRO PROCESSOR COM PA TIBLE — The HS 3120 has

been designed for great flexibility in connecting to

bus-oriented systems. The 12 data inputs are

organized into 3 independent addressable 4-bit input

registers such that the HS 3120 can be connected to

either a 4, 8 or 16-bit data bus. The control logic of

the HS 3120 includes chip enable and latch enable

inputs for flexible memory mapping. A ll

controls are level-triggered to allow static or dynamic

operation.

VERSA TILE OUTPUTS —A total of 5 output lines are

provided by the HS 3120 to allow unipolar and

bipolar output connection with a minimum of

external components. The feedback resistor is

internal. The resistor ladder network termination is

externally available, thus eliminating an external

resistor for the 1 LSB offset in bipolar mode.

M ONOLITHIC CM OS CONSTRUCTION —The HS 3120

is a one-chip CM OS circuit with a resistor ladder

network designed for 0.01% linearity without laser

trimming. Small chip size and high manufacturing

yields result in greatly reduced cost.

FUNCTIONAL DIAGRAM (M SB)

BIT 2

109

BIT 12

(LSB)

VREF

INPUT REGISTERINPUT REGISTER INPUT REGISTER

CO NTROL

LOGIC

DA C REG ISTE R 12 BIT M DA C

HBE

M BE

LBE

LDA C

28 26 27 8 2

VDD1 VDD2 GND GND LDTR

R/2R/2

FB1

I01

I02

FB4

FB3

HS 3120

165 Cedar Hill Street,Marlborough, MA01752 Tel:508.485.6350 Fax: 508.485.5168

www.SpectrumMicrowave.com

SPEC IFI CATI O N S

(Typical @ 25ºC, nominal power supply, VREF=+10V, unipolar unless otherwise noted).

M ODEL HS3120-2 HS 3120-0

TY PE M ULTIPLY ING, DO UBLE BUFFERED INPUTS

DIGITAL INPUT

Resolution 12-Bits

2-Quad. Unipolar Coding Binary1, Comp. Binary1

4-Quad. Bipolar Coding Offset Binary

Logic Compatibility2CM O S, TTL

Input Current ±1 µA (max)

Data Set-up Time3250nS (min)

Strobe W idth3250nS (min)

Data Hold Time3OnS (min)

REFERENCE INPUT

Voltage Range ±25V (max)

Input Impedance 8k ±50%

ANALOG OUTPUT

Scale Factor 125µA/V Ref ±50%

Scale Factor Accuracy4±0.4%

Output Leakage5

@25ºC <10nA (max)

@125ºC <200nA (max)

Output Capacitance

COUT 1, all inputs high 80pF

COUT 1, all inputs low 40pF

COUT 2, all inputs high 40pF

COUT 2, all inputs low 80pF

STA TIC PERFORM ANCE

Integral Linearity ±0.015% F.S.R. (max) ±0.05% F.S.R. (max)

Dif ferential Linearity ±0.024% F.S.R. (max) ±0.097% F.S.R. (max)

M onotonicity Guaranteed to 12 bits Guaranteed to 10 bits

M onotonicity Temp. Range

C-M odels 0ºC to +70ºC

B-M odels –55ºC to +125ºC

DY NAM IC PERFORM ANCE

Digital Small Signal Settling 1.0µsec

Full Scale Transition Settling

to 0.01% (strobed) 2.0µsec

Reference Feedthrough Error (V Ref=20V pp)

@1kHz <1mV

@10kHz 2mV

Delay to output

from Bits input 100nS6

from LDA C 200nS6

from CE 120nS6

STABILITY (Over Specif ied Temp. Range)

Scale Factor42 ppm F.S.R./ºC (max)

Integral Linearity 0.2 ppm F.S.R./ºC (max)

Dif ferential Linearity 0.2 ppm F.S.R./ºC (max)

M onotonicity Temp. Range

C-Option 0ºC to +70ºC

B-Option –55ºC to +125ºC

POW ER SUPPLY (V DD)

Operating Voltage (specif ications guaranteed) +15V ±5%

M aximum V oltage Range +5V to 16V

Current 2.5mA (max)

Rejection Ratio 0.002% /% (max)

TEM PERATURE RA NGE

Operating C-Option 0ºC to +70ºC

Operating B-Option 55ºC to +125ºC

Storage –65ºC to +150ºC

M ECHA NICA L

Case Style 28-pin double DIP

C-Option ceramic

B-Option ceramic

NOTES:

* Same as HS 3120-2

1. The input coding is complementary binary if IO 2 is used.

2. Digital input voltage must not exceed supply voltage or go below –0.5V . “ 0” <0.8V , 2.4V < “ 1” VDD

3. All strobes are level triggered. See TIM ING DIA GRAM .

4. Using the internal feedback resistor and an external opamp.

5. The output leakage current w ill create an offset voltage at the external opamps output. It doubles every 10ºC temperature increase.

6. Delay times are twice the amount show n at TA =+125ºC

HS3120

Continued on next page.

PIN FUNCTION

1 FB4, Feedback Bipolar Operation

2 LDTR, Ladder Termination

3 FB3, Feedback Bipolar Operation

4 VREF Reference Voltage Input

5 FB1, Feedback, Unipolar/Bipolar

6 I01, Current out into virtual ground

7 I02, Current out-complement of I01

8 VSS, Ground, A nalog and DA C Register

9 Bit 1,M SB

10 Bit 2

11 Bit 3

12 Bit 4

13 Bit 5

14 Bit 6

15 Bit 7

16 Bit 8

17 Bit 9

18 Bit 10

19 Bit 11

20 Bit 12

21 LDAC, Transfers data f rom input to DAC register

22 CE, Chip Enable, active low

23 LBE, Bit 12 to Bit 9 Enable

24 M BE, Bit 8 to Bit 5 Enable

25 HBE, Bit 4 to Bit 1 Enable

26 VDD2, Supply A nalog and DA C Register

27 VSS1, Ground input latches

28 VDD1, Supply input latches

NOTE: Pins 8 and 27 and pins 26 and 28 must be connected externally.

CONNECTIONS

Unipolar Operation: Connect I01 and FB1

Tie I02, (Pin 7). FB3, (Pin 3), FB4, (Pin 1)

all to Ground (Pin 8)

Bipolar Operation: Connect I01, I02, FB1, FB3, FB4

Tie LDTR to I02

Grounding: Connect all GRD to system analog ground

and tie this to digital ground.

NOTE: All unused input must be grounded

PIN ASSIGNM ENTS 0.1

(2.54)

TOP VIEW

PIN 1

0.05

(1.27)

TY P

0.05

(1.27)

0.610

(15.49)

0.006

(0.152)

0.01

(0.25) TY P

0.17

(4.3)

0.17

(4.3)

DIM ENSIO NS

inch

(mm)

1.3

(33.02) 1.4

(35.56)

M ECHANICA L

CA UTION: ESD (Electro-Static Discharge) sensitive device.

Permanent damage may occur w hen unconnected devices are

subjected to high energy electrostatic f ields. Unused devices must

be stored in conductive foam or shunts. Protective foam should be

discharged to the destination socket before devices are removed.

Devices should be handled at static safe workstations only. Unused

digital inputs must be grounded or tied to the logic supply voltage.

Unless otherwise noted, the supply voltage at any digital input

should never exceed the supply voltage by more than 0.5 volts or

go below –0.5 volts. If this condition cannot be maintained, limit

input current on digital inputs by using series resistors or contact

Hybrid Systems f or technical assistance.

Specif ications subject to change without notice.

ORDERING INFORM A TION

M ODEL DESCRIPTIO N

HS 312000 Double Buf fered 12-Bit M DA C. Commercial

HS 3120C-2 Double Buffered 12-Bit M DA C. Commercial

HS 3120B-0 Double Buff ered 12-Bit M DA C. M IL-STD-883C

HS 3120B-2 Double Buff ered 12-Bit M DA C. M IL-STD-883C

Consult factory for application information.

HS3120